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JonasDC |
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---- ----
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---- adder_n.vhd ----
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---- ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- Description ----
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---- This file contains the implementation of a n-bit adder ----
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---- using the adder blocks. ----
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---- used as the montgommery multiplier pre- and post- ----
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---- computation adder ----
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---- ----
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---- Dependencies: ----
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---- - adder_block ----
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---- ----
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---- Author(s): ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity adder_n is
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generic ( width : integer := 1536;
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block_width : integer := 8
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);
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Port ( core_clk : in STD_LOGIC;
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a : in STD_LOGIC_VECTOR((width-1) downto 0);
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b : in STD_LOGIC_VECTOR((width-1) downto 0);
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cin : in STD_LOGIC;
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cout : out STD_LOGIC;
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s : out STD_LOGIC_VECTOR((width-1) downto 0)
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);
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end adder_n;
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architecture Structural of adder_n is
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component adder_block
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generic ( width : integer := 32
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);
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Port ( core_clk : in STD_LOGIC;
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a : in STD_LOGIC_VECTOR((width-1) downto 0);
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b : in STD_LOGIC_VECTOR((width-1) downto 0);
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cin : in STD_LOGIC;
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cout : out STD_LOGIC;
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s : out STD_LOGIC_VECTOR((width-1) downto 0)
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);
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end component;
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constant nr_of_blocks : integer := width/block_width;
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signal carry : std_logic_vector(nr_of_blocks downto 0);
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begin
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carry(0) <= cin;
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adder_block_chain: for i in 0 to (nr_of_blocks-1) generate
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adder_blocks: adder_block
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generic map( width => block_width
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)
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port map( core_clk => core_clk,
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a => a((((i+1)*block_width)-1) downto (i*block_width)),
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b => b((((i+1)*block_width)-1) downto (i*block_width)),
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cin => carry(i),
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cout => carry(i+1),
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s => s((((i+1)*block_width)-1) downto (i*block_width))
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);
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end generate;
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cout <= carry(nr_of_blocks);
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end Structural;
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