OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [bench/] [vhdl/] [axi_tb.vhd] - Blame information for rev 94

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 84 JonasDC
----------------------------------------------------------------------  
2
----  axi_tb                                                      ---- 
3
----                                                              ---- 
4
----  This file is part of the                                    ----
5
----    Modular Simultaneous Exponentiation Core project          ---- 
6
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
7
----                                                              ---- 
8
----  Description                                                 ---- 
9
----    testbench for the AXI-Lite interface, functions are       ----
10
----    provided to read and write data                           ----
11
----    writes bus transfers to out/axi_output                    ----
12
----                                                              ----
13
----  Dependencies:                                               ----
14
----    - mod_sim_exp_core                                        ----
15
----                                                              ----
16
----  Authors:                                                    ----
17
----      - Geoffrey Ottoy, DraMCo research group                 ----
18
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
19
----                                                              ---- 
20
---------------------------------------------------------------------- 
21
----                                                              ---- 
22
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
23
----                                                              ---- 
24
---- This source file may be used and distributed without         ---- 
25
---- restriction provided that this copyright statement is not    ---- 
26
---- removed from the file and that any derivative work contains  ---- 
27
---- the original copyright notice and the associated disclaimer. ---- 
28
----                                                              ---- 
29
---- This source file is free software; you can redistribute it   ---- 
30
---- and/or modify it under the terms of the GNU Lesser General   ---- 
31
---- Public License as published by the Free Software Foundation; ---- 
32
---- either version 2.1 of the License, or (at your option) any   ---- 
33
---- later version.                                               ---- 
34
----                                                              ---- 
35
---- This source is distributed in the hope that it will be       ---- 
36
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
37
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
38
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
39
---- details.                                                     ---- 
40
----                                                              ---- 
41
---- You should have received a copy of the GNU Lesser General    ---- 
42
---- Public License along with this source; if not, download it   ---- 
43
---- from http://www.opencores.org/lgpl.shtml                     ---- 
44
----                                                              ---- 
45
----------------------------------------------------------------------
46
library ieee;
47
use ieee.std_logic_1164.all;
48
use ieee.std_logic_unsigned.all;
49
 
50
library std;
51
use std.textio.all;
52
 
53
library ieee;
54
use ieee.std_logic_textio.all;
55
 
56
entity axi_tb is
57
end axi_tb;
58
 
59
architecture arch of axi_tb is
60
  -- constants
61
  constant CLK_PERIOD : time := 10 ns;
62 94 JonasDC
  constant CORE_CLK_PERIOD : time := 4 ns;
63 84 JonasDC
  constant C_S_AXI_DATA_WIDTH : integer := 32;
64
  constant C_S_AXI_ADDR_WIDTH : integer := 32;
65
 
66
  file output : text open write_mode is "out/axi_output.txt";
67
 
68
  ------------------------------------------------------------------
69
  -- Core parameters
70
  ------------------------------------------------------------------
71
  constant C_NR_BITS_TOTAL   : integer := 1536;
72
  constant C_NR_STAGES_TOTAL : integer := 96;
73
  constant C_NR_STAGES_LOW   : integer := 32;
74
  constant C_SPLIT_PIPELINE  : boolean := true;
75 94 JonasDC
  constant C_FIFO_AW         : integer := 7; -- set to log2( (maximum exponent width)/16 )
76 84 JonasDC
  constant C_MEM_STYLE       : string  := "generic"; -- xil_prim, generic, asym are valid options
77
  constant C_FPGA_MAN        : string  := "xilinx";  -- xilinx, altera are valid options
78
  constant C_BASEADDR        : std_logic_vector(0 to 31) := x"A0000000";
79
  constant C_HIGHADDR        : std_logic_vector(0 to 31) := x"A0007FFF";
80
 
81 94 JonasDC
 
82
  signal core_clk     : std_logic := '0';
83 84 JonasDC
  -------------------------
84
  -- AXI4lite interface
85
  -------------------------
86
  --- Global signals
87
  signal S_AXI_ACLK    : std_logic;
88
  signal S_AXI_ARESETN : std_logic;
89
  --- Write address channel
90
  signal S_AXI_AWADDR  : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
91
  signal S_AXI_AWVALID : std_logic;
92
  signal S_AXI_AWREADY : std_logic;
93
  --- Write data channel
94
  signal S_AXI_WDATA  : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
95
  signal S_AXI_WVALID : std_logic;
96
  signal S_AXI_WREADY : std_logic;
97
  signal S_AXI_WSTRB  : std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
98
  --- Write response channel
99
  signal S_AXI_BVALID : std_logic;
100
  signal S_AXI_BREADY : std_logic;
101
  signal S_AXI_BRESP  : std_logic_vector(1 downto 0);
102
  --- Read address channel
103
  signal S_AXI_ARADDR  : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
104
  signal S_AXI_ARVALID : std_logic;
105
  signal S_AXI_ARREADY : std_logic;
106
  --- Read data channel
107
  signal S_AXI_RDATA  : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
108
  signal S_AXI_RVALID : std_logic;
109
  signal S_AXI_RREADY : std_logic;
110
  signal S_AXI_RRESP  : std_logic_vector(1 downto 0);
111
 
112
begin
113
 
114
  ------------------------------------------
115
  -- Generate clk
116
  ------------------------------------------
117
  clk_process : process
118
  begin
119
    while (true) loop
120
      S_AXI_ACLK <= '0';
121
      wait for CLK_PERIOD/2;
122
      S_AXI_ACLK <= '1';
123
      wait for CLK_PERIOD/2;
124
    end loop;
125
  end process;
126 94 JonasDC
 
127
  core_clk_process : process
128
  begin
129
    while (true) loop
130
      core_clk <= '0';
131
      wait for CORE_CLK_PERIOD/2;
132
      core_clk <= '1';
133
      wait for CORE_CLK_PERIOD/2;
134
    end loop;
135
  end process;
136
 
137 84 JonasDC
 
138
  stim_proc : process
139
 
140
    variable Lw : line;
141
 
142
    procedure waitclk(n : natural := 1) is
143
    begin
144
      for i in 1 to n loop
145
        wait until rising_edge(S_AXI_ACLK);
146
      end loop;
147
    end waitclk;
148
 
149
    procedure axi_write( address : std_logic_vector(31 downto 0);
150
                         data    : std_logic_vector(31 downto 0) ) is
151
      variable counter : integer := 0;
152
    begin
153
      -- place address on the bus
154
      wait until rising_edge(S_AXI_ACLK);
155
      S_AXI_AWADDR <= address;
156
      S_AXI_AWVALID <= '1';
157
      S_AXI_WDATA <= data;
158
      S_AXI_WVALID <= '1';
159
      S_AXI_WSTRB <= "1111";
160
      while (counter /= 2) loop -- wait for slave response
161
        wait until rising_edge(S_AXI_ACLK);
162
        if (S_AXI_AWREADY='1') then
163
          S_AXI_AWVALID <= '0';
164
          counter := counter+1;
165
        end if;
166
        if (S_AXI_WREADY='1') then
167
          S_AXI_WVALID <= '0';
168
          counter := counter+1;
169
        end if;
170
      end loop;
171
      S_AXI_BREADY <= '1';
172
      if S_AXI_BVALID/='1' then
173
        wait until S_AXI_BVALID='1';
174
      end if;
175
 
176
      write(Lw, string'("Wrote "));
177
      hwrite(Lw, data);
178
      write(Lw, string'(" to   "));
179
      hwrite(Lw, address);
180
 
181
      if (S_AXI_BRESP /= "00") then
182
        write(Lw, string'("   --> Error! Status: "));
183
        write(Lw, S_AXI_BRESP);
184
      end if;
185
      writeline(output, Lw);
186
 
187
      wait until rising_edge(S_AXI_ACLK);
188
      S_AXI_BREADY <= '0';
189
    end axi_write;
190
 
191
    procedure axi_read( address  : std_logic_vector(31 downto 0) ) is
192
    begin
193
      -- place address on the bus
194
      wait until rising_edge(S_AXI_ACLK);
195
      S_AXI_ARADDR <= address;
196
      S_AXI_ARVALID <= '1';
197
      wait until S_AXI_ARREADY='1';
198
      wait until rising_edge(S_AXI_ACLK);
199
      S_AXI_ARVALID <= '0';
200
      -- wait for read data
201
      S_AXI_RREADY <= '1';
202
      wait until S_AXI_RVALID='1';
203
      wait until rising_edge(S_AXI_ACLK);
204
 
205
      write(Lw, string'("Read  "));
206
      hwrite(Lw, S_AXI_RDATA);
207
      write(Lw, string'(" from "));
208
      hwrite(Lw, address);
209
 
210
      if (S_AXI_RRESP /= "00") then
211
        write(Lw, string'("   --> Error! Status: "));
212
        write(Lw, S_AXI_RRESP);
213
      end if;
214
      writeline(output, Lw);
215
      S_AXI_RREADY <= '0';
216
 
217
      --assert false report "Wrote " & " to " & " Status=" & to_string(S_AXI_BRESP) severity note;
218
    end axi_read;
219
 
220
 
221
  begin
222
 
223
    write(Lw, string'("----------------------------------------------"));
224
    writeline(output, Lw);
225
    write(Lw, string'("--            AXI BUS SIMULATION            --"));
226
    writeline(output, Lw);
227
    write(Lw, string'("----------------------------------------------"));
228
    writeline(output, Lw);
229
    S_AXI_AWADDR <= (others=>'0');
230
    S_AXI_AWVALID <= '0';
231
    S_AXI_WDATA <= (others=>'0');
232
    S_AXI_WVALID <= '0';
233
    S_AXI_WSTRB <= (others=>'0');
234
    S_AXI_BREADY <= '0';
235
    S_AXI_ARADDR <= (others=>'0');
236
    S_AXI_ARVALID <= '0';
237
    S_AXI_RREADY <= '0';
238
 
239
    S_AXI_ARESETN <= '0';
240
    waitclk(10);
241
    S_AXI_ARESETN <= '1';
242
    waitclk(20);
243
 
244
    axi_write(x"A0000000", x"11111111");
245
    axi_read(x"A0000000");
246
    axi_write(x"A0001000", x"01234567");
247
    axi_read(x"A0001000");
248
    axi_write(x"A0002000", x"AAAAAAAA");
249
    axi_read(x"A0002000");
250
    axi_write(x"A0003000", x"BBBBBBBB");
251
    axi_read(x"A0003000");
252
    axi_write(x"A0004000", x"CCCCCCCC");
253
    axi_read(x"A0004000");
254
    axi_write(x"A0005000", x"DDDDDDDD");
255
    axi_read(x"A0005000");
256
    axi_write(x"A0006000", x"EEEEEEEE");
257
    axi_read(x"A0006000");
258
    axi_write(x"A0007000", x"FFFFFFFF");
259
    axi_read(x"A0007000");
260
    axi_write(x"A0008000", x"22222222");
261
    axi_read(x"A0008000");
262
    axi_write(x"A0009000", x"33333333");
263
    axi_read(x"A0009000");
264
    axi_write(x"A000A000", x"44444444");
265
    axi_read(x"A000A000");
266
    waitclk(100);
267
 
268
    assert false report "End of simulation" severity failure;
269
 
270
  end process;
271
 
272
 
273
  -------------------------
274
  -- Unit Under Test
275
  -------------------------
276
  uut : entity work.msec_ipcore_axilite
277
  generic map(
278
    C_NR_BITS_TOTAL   => C_NR_BITS_TOTAL,
279
    C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
280
    C_NR_STAGES_LOW   => C_NR_STAGES_LOW,
281
    C_SPLIT_PIPELINE  => C_SPLIT_PIPELINE,
282 94 JonasDC
    C_FIFO_AW         => C_FIFO_AW,
283 84 JonasDC
    C_MEM_STYLE       => C_MEM_STYLE, -- xil_prim, generic, asym are valid options
284
    C_FPGA_MAN        => C_FPGA_MAN,   -- xilinx, altera are valid options
285
    C_BASEADDR        => C_BASEADDR,
286
    C_HIGHADDR        => C_HIGHADDR
287
  )
288
  port map(
289
    --USER ports
290 94 JonasDC
    core_clk => core_clk,
291 84 JonasDC
    -------------------------
292
    -- AXI4lite interface
293
    -------------------------
294
    --- Global signals
295
    S_AXI_ACLK    => S_AXI_ACLK,
296
    S_AXI_ARESETN => S_AXI_ARESETN,
297
    --- Write address channel
298
    S_AXI_AWADDR  => S_AXI_AWADDR,
299
    S_AXI_AWVALID => S_AXI_AWVALID,
300
    S_AXI_AWREADY => S_AXI_AWREADY,
301
    --- Write data channel
302
    S_AXI_WDATA  => S_AXI_WDATA,
303
    S_AXI_WVALID => S_AXI_WVALID,
304
    S_AXI_WREADY => S_AXI_WREADY,
305
    S_AXI_WSTRB  => S_AXI_WSTRB,
306
    --- Write response channel
307
    S_AXI_BVALID => S_AXI_BVALID,
308
    S_AXI_BREADY => S_AXI_BREADY,
309
    S_AXI_BRESP  => S_AXI_BRESP,
310
    --- Read address channel
311
    S_AXI_ARADDR  => S_AXI_ARADDR,
312
    S_AXI_ARVALID => S_AXI_ARVALID,
313
    S_AXI_ARREADY => S_AXI_ARREADY,
314
    --- Read data channel
315
    S_AXI_RDATA  => S_AXI_RDATA,
316
    S_AXI_RVALID => S_AXI_RVALID,
317
    S_AXI_RREADY => S_AXI_RREADY,
318
    S_AXI_RRESP  => S_AXI_RRESP
319
  );
320
 
321
end arch;
322
 

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.