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1 3 JonasDC
----------------------------------------------------------------------  
2 24 JonasDC
----  mod_sim_exp_core_tb                                               ---- 
3 3 JonasDC
----                                                              ---- 
4
----  This file is part of the                                    ----
5
----    Modular Simultaneous Exponentiation Core project          ---- 
6
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
7
----                                                              ---- 
8
----  Description                                                 ---- 
9
----    testbench for the modular simultaneous exponentiation     ----
10
----    core. Performs some exponentiations to verify the design  ----
11
----    Takes input parameters from sim_input.txt en writes       ----
12
----    result and output to sim_output.txt                       ----
13
----                                                              ----
14
----  Dependencies:                                               ----
15
----    - multiplier_core                                         ----
16
----                                                              ----
17
----  Authors:                                                    ----
18
----      - Geoffrey Ottoy, DraMCo research group                 ----
19
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
20
----                                                              ---- 
21
---------------------------------------------------------------------- 
22
----                                                              ---- 
23
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
24
----                                                              ---- 
25
---- This source file may be used and distributed without         ---- 
26
---- restriction provided that this copyright statement is not    ---- 
27
---- removed from the file and that any derivative work contains  ---- 
28
---- the original copyright notice and the associated disclaimer. ---- 
29
----                                                              ---- 
30
---- This source file is free software; you can redistribute it   ---- 
31
---- and/or modify it under the terms of the GNU Lesser General   ---- 
32
---- Public License as published by the Free Software Foundation; ---- 
33
---- either version 2.1 of the License, or (at your option) any   ---- 
34
---- later version.                                               ---- 
35
----                                                              ---- 
36
---- This source is distributed in the hope that it will be       ---- 
37
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
38
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
39
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
40
---- details.                                                     ---- 
41
----                                                              ---- 
42
---- You should have received a copy of the GNU Lesser General    ---- 
43
---- Public License along with this source; if not, download it   ---- 
44
---- from http://www.opencores.org/lgpl.shtml                     ---- 
45
----                                                              ---- 
46
----------------------------------------------------------------------
47
 
48 2 JonasDC
library ieee;
49
use ieee.std_logic_1164.all;
50
use ieee.std_logic_unsigned.all;
51
use ieee.std_logic_arith.all;
52
 
53
library std;
54
use std.textio.all;
55
 
56
library ieee;
57
use ieee.std_logic_textio.all;
58
 
59 3 JonasDC
library mod_sim_exp;
60
use mod_sim_exp.mod_sim_exp_pkg.all;
61
 
62 24 JonasDC
entity mod_sim_exp_core_tb is
63
end mod_sim_exp_core_tb;
64 2 JonasDC
 
65 24 JonasDC
architecture test of mod_sim_exp_core_tb is
66 43 JonasDC
  constant CLK_PERIOD : time := 10 ns;
67 2 JonasDC
  signal clk          : std_logic := '0';
68
  signal reset        : std_logic := '1';
69 3 JonasDC
  file input          : text open read_mode is "src/sim_input.txt";
70
  file output         : text open write_mode is "out/sim_output.txt";
71 2 JonasDC
 
72
  ------------------------------------------------------------------
73 43 JonasDC
  -- Core parameters
74
  ------------------------------------------------------------------
75
  constant C_NR_BITS_TOTAL   : integer := 1536;
76
  constant C_NR_STAGES_TOTAL : integer := 96;
77
  constant C_NR_STAGES_LOW   : integer := 32;
78
  constant C_SPLIT_PIPELINE  : boolean := true;
79
 
80
  -- extra calculated constants
81
  constant NR_BITS_LOW : integer := (C_NR_BITS_TOTAL/C_NR_STAGES_TOTAL)*C_NR_STAGES_LOW;
82
  constant NR_BITS_HIGH : integer := C_NR_BITS_TOTAL-NR_BITS_LOW;
83
 
84
  ------------------------------------------------------------------
85 2 JonasDC
  -- Signals for multiplier core memory space
86
  ------------------------------------------------------------------
87
  signal core_rw_address   : std_logic_vector (8 downto 0);
88
  signal core_data_in      : std_logic_vector(31 downto 0);
89
  signal core_fifo_din     : std_logic_vector(31 downto 0);
90
  signal core_data_out     : std_logic_vector(31 downto 0);
91
  signal core_write_enable : std_logic;
92
  signal core_fifo_push    : std_logic;
93
  ------------------------------------------------------------------
94
  -- Signals for multiplier core control
95
  ------------------------------------------------------------------
96
  signal core_start          : std_logic;
97 46 JonasDC
  signal core_exp_m          : std_logic;
98 2 JonasDC
  signal core_p_sel          : std_logic_vector(1 downto 0);
99
  signal core_dest_op_single : std_logic_vector(1 downto 0);
100
  signal core_x_sel_single   : std_logic_vector(1 downto 0);
101
  signal core_y_sel_single   : std_logic_vector(1 downto 0);
102
  signal calc_time           : std_logic;
103
  ------------------------------------------------------------------
104
  -- Signals for multiplier core interrupt
105
  ------------------------------------------------------------------
106
  signal core_fifo_full   : std_logic;
107
  signal core_fifo_nopush : std_logic;
108
  signal core_ready       : std_logic;
109
  signal core_mem_collision : std_logic;
110
 
111
begin
112
 
113
------------------------------------------
114
-- Generate clk
115
------------------------------------------
116
clk_process : process
117
begin
118
  while (true) loop
119
    clk <= '0';
120 43 JonasDC
    wait for CLK_PERIOD/2;
121 2 JonasDC
    clk <= '1';
122 43 JonasDC
    wait for CLK_PERIOD/2;
123 2 JonasDC
  end loop;
124
end process;
125
 
126
------------------------------------------
127
-- Stimulus Process
128
------------------------------------------
129
stim_proc : process
130
  procedure waitclk(n : natural := 1) is
131
  begin
132
    for i in 1 to n loop
133
      wait until rising_edge(clk);
134
    end loop;
135
  end waitclk;
136
 
137
  procedure loadOp(constant op_sel : std_logic_vector(2 downto 0);
138
               variable op_data : std_logic_vector(2047 downto 0)) is
139
  begin
140
    wait until rising_edge(clk);
141
    core_rw_address <= op_sel & "000000";
142
    wait until rising_edge(clk);
143
    core_write_enable <= '1';
144
    for i in 0 to (1536/32)-1 loop
145
      assert (core_mem_collision='0')
146
        report "collision detected while writing operand!!" severity failure;
147
      case (core_p_sel) is
148
        when "11" =>
149
          core_data_in <= op_data(((i+1)*32)-1 downto (i*32));
150
        when "01" =>
151
          if (i < 16) then core_data_in <= op_data(((i+1)*32)-1 downto (i*32));
152
          else core_data_in <= x"00000000"; end if;
153
        when "10" =>
154
          if (i >= 16) then core_data_in <= op_data(((i-15)*32)-1 downto ((i-16)*32));
155
          else core_data_in <= x"00000000"; end if;
156
        when others =>
157
          core_data_in <= x"00000000";
158
      end case;
159
 
160
      wait until rising_edge(clk);
161
      core_rw_address <= core_rw_address+"000000001";
162
    end loop;
163
    core_write_enable <= '0';
164
    wait until rising_edge(clk);
165
  end loadOp;
166
 
167
  procedure readOp(constant op_sel : std_logic_vector(2 downto 0);
168
                  variable op_data  : out std_logic_vector(2047 downto 0);
169
                  variable op_width : integer) is
170
  begin
171
      wait until rising_edge(clk);
172
      core_dest_op_single <= op_sel(1 downto 0);
173
      if (core_p_sel = "10") then
174
        core_rw_address <= op_sel & "010000";
175
      else
176
        core_rw_address <= op_sel & "000000";
177
      end if;
178
      waitclk(2);
179
 
180
      for i in 0 to (op_width/32)-2 loop
181
          op_data(((i+1)*32)-1 downto (i*32)) := core_data_out;
182
          core_rw_address <= core_rw_address+"000000001";
183
          waitclk(2);
184
      end loop;
185
      op_data(op_width-1 downto op_width-32) := core_data_out;
186
      wait until rising_edge(clk);
187
  end readOp;
188
 
189
  function ToString(constant Timeval : time) return string is
190
    variable StrPtr : line;
191
  begin
192
    write(StrPtr,Timeval);
193
    return StrPtr.all;
194
  end ToString;
195
 
196
  -- variables to read file
197
  variable L : line;
198
  variable Lw : line;
199
  variable base_width : integer;
200
  variable exponent_width : integer;
201
  variable g0 : std_logic_vector(2047 downto 0) := (others=>'0');
202
  variable g1 : std_logic_vector(2047 downto 0) := (others=>'0');
203
  variable e0 : std_logic_vector(2047 downto 0) := (others=>'0');
204
  variable e1 : std_logic_vector(2047 downto 0) := (others=>'0');
205
  variable m : std_logic_vector(2047 downto 0) := (others=>'0');
206
  variable R2 : std_logic_vector(2047 downto 0) := (others=>'0');
207
  variable R : std_logic_vector(2047 downto 0) := (others=>'0');
208
  variable gt0 : std_logic_vector(2047 downto 0) := (others=>'0');
209
  variable gt1 : std_logic_vector(2047 downto 0) := (others=>'0');
210
  variable gt01 : std_logic_vector(2047 downto 0) := (others=>'0');
211
  variable one : std_logic_vector(2047 downto 0) := std_logic_vector(conv_unsigned(1, 2048));
212
  variable result : std_logic_vector(2047 downto 0) := (others=>'0');
213
  variable data_read : std_logic_vector(2047 downto 0) := (others=>'0');
214
  variable good_value : boolean;
215
  variable param_count : integer := 0;
216
 
217
  -- constants for operand selection
218
  constant op_modulus : std_logic_vector(2 downto 0) := "100";
219
  constant op_0 : std_logic_vector(2 downto 0) := "000";
220
  constant op_1 : std_logic_vector(2 downto 0) := "001";
221
  constant op_2 : std_logic_vector(2 downto 0) := "010";
222
  constant op_3 : std_logic_vector(2 downto 0) := "011";
223
 
224
  variable timer : time;
225
begin
226
  -- initialisation
227
  -- memory
228
  core_write_enable <= '0';
229
  core_data_in <= x"00000000";
230
  core_rw_address <= "000000000";
231
  -- fifo
232
  core_fifo_din <= x"00000000";
233
  core_fifo_push <= '0';
234
  -- control
235
  core_start <= '0';
236 46 JonasDC
  core_exp_m <= '0';
237 2 JonasDC
  core_x_sel_single <= "00";
238
  core_y_sel_single <= "01";
239
  core_dest_op_single <= "01";
240
  core_p_sel <= "11";
241
 
242
  -- Generate active high reset signal
243
  reset <= '1';
244
  waitclk(100);
245
  reset <= '0';
246
  waitclk(100);
247
 
248
  while not endfile(input) loop
249
    readline(input, L); -- read next line
250
    next when L(1)='-'; -- skip comment lines
251
    -- read input values
252
    case param_count is
253
      when 0 => -- base width
254
        read(L, base_width, good_value);
255
        assert good_value report "Can not read base width" severity failure;
256
        assert false report "Simulating exponentiation" severity note;
257
        write(Lw, string'("----------------------------------------------"));
258
        writeline(output, Lw);
259
        write(Lw, string'("--              EXPONENTIATION              --"));
260
        writeline(output, Lw);
261
        write(Lw, string'("----------------------------------------------"));
262
        writeline(output, Lw);
263
        write(Lw, string'("----- Variables used:"));
264
        writeline(output, Lw);
265
        write(Lw, string'("base width: "));
266
        write(Lw, base_width);
267
        writeline(output, Lw);
268
        case (base_width) is
269 43 JonasDC
          when C_NR_BITS_TOTAL => when NR_BITS_HIGH => when NR_BITS_LOW =>
270 2 JonasDC
          when others =>
271
            write(Lw, string'("=> incompatible base width!!!")); writeline(output, Lw);
272
            assert false report "incompatible base width!!!" severity failure;
273
        end case;
274
 
275
      when 1 => -- exponent width
276
        read(L, exponent_width, good_value);
277
        assert good_value report "Can not read exponent width" severity failure;
278
        write(Lw, string'("exponent width: "));
279
        write(Lw, exponent_width);
280
        writeline(output, Lw);
281
 
282
      when 2 => -- g0
283
        hread(L, g0(base_width-1 downto 0), good_value);
284
        assert good_value report "Can not read g0! (wrong lenght?)" severity failure;
285
        write(Lw, string'("g0: "));
286
        hwrite(Lw, g0(base_width-1 downto 0));
287
        writeline(output, Lw);
288
 
289
      when 3 => -- g1
290
        hread(L, g1(base_width-1 downto 0), good_value);
291
        assert good_value report "Can not read g1! (wrong lenght?)" severity failure;
292
        write(Lw, string'("g1: "));
293
        hwrite(Lw, g1(base_width-1 downto 0));
294
        writeline(output, Lw);
295
 
296
      when 4 => -- e0
297
        hread(L, e0(exponent_width-1 downto 0), good_value);
298
        assert good_value report "Can not read e0! (wrong lenght?)" severity failure;
299
        write(Lw, string'("e0: "));
300
        hwrite(Lw, e0(exponent_width-1 downto 0));
301
        writeline(output, Lw);
302
 
303
      when 5 => -- e1
304
        hread(L, e1(exponent_width-1 downto 0), good_value);
305
        assert good_value report "Can not read e1! (wrong lenght?)" severity failure;
306
        write(Lw, string'("e1: "));
307
        hwrite(Lw, e1(exponent_width-1 downto 0));
308
        writeline(output, Lw);
309
 
310
      when 6 => -- m
311
        hread(L, m(base_width-1 downto 0), good_value);
312
        assert good_value report "Can not read m! (wrong lenght?)" severity failure;
313
        write(Lw, string'("m:  "));
314
        hwrite(Lw, m(base_width-1 downto 0));
315
        writeline(output, Lw);
316
 
317
      when 7 => -- R^2
318
        hread(L, R2(base_width-1 downto 0), good_value);
319
        assert good_value report "Can not read R2! (wrong lenght?)" severity failure;
320
        write(Lw, string'("R2: "));
321
        hwrite(Lw, R2(base_width-1 downto 0));
322
        writeline(output, Lw);
323
 
324
      when 8 => -- R
325
        hread(L, R(base_width-1 downto 0), good_value);
326
        assert good_value report "Can not read R! (wrong lenght?)" severity failure;
327
 
328
      when 9 => -- gt0
329
        hread(L, gt0(base_width-1 downto 0), good_value);
330
        assert good_value report "Can not read gt0! (wrong lenght?)" severity failure;
331
 
332
      when 10 => -- gt1
333
        hread(L, gt1(base_width-1 downto 0), good_value);
334
        assert good_value report "Can not read gt1! (wrong lenght?)" severity failure;
335
 
336
      when 11 => -- gt01
337
        hread(L, gt01(base_width-1 downto 0), good_value);
338
        assert good_value report "Can not read gt01! (wrong lenght?)" severity failure;
339
 
340
        -- select pipeline for all computations
341
        ----------------------------------------
342
        writeline(output, Lw);
343
        write(Lw, string'("----- Selecting pipeline: "));
344
        writeline(output, Lw);
345
        case (base_width) is
346 43 JonasDC
          when C_NR_BITS_TOTAL =>  core_p_sel <= "11"; write(Lw, string'("  Full pipeline selected"));
347
          when NR_BITS_HIGH =>  core_p_sel <= "10"; write(Lw, string'("  Upper pipeline selected"));
348
          when NR_BITS_LOW  =>  core_p_sel <= "01"; write(Lw, string'("  Lower pipeline selected"));
349 2 JonasDC
          when others =>
350
            write(Lw, string'("  Invallid bitwidth for design"));
351
            assert false report "impossible basewidth!" severity failure;
352
        end case;
353
        writeline(output, Lw);
354
 
355
        writeline(output, Lw);
356
        write(Lw, string'("----- Writing operands:"));
357
        writeline(output, Lw);
358
 
359
        -- load the modulus
360
        --------------------
361
        loadOp(op_modulus, m); -- visual check needed
362
        write(Lw, string'("  m written"));
363
        writeline(output, Lw);
364
 
365
        -- load g0
366
        -----------
367
        loadOp(op_0, g0);
368
        -- verify
369
        readOp(op_0, data_read, base_width);
370
        if (g0(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
371
          write(Lw, string'("  g0 written in operand_0")); writeline(output, Lw);
372
        else
373
          write(Lw, string'("  failed to write g0 to operand_0!")); writeline(output, Lw);
374
          assert false report "Load g0 to op0 data verify failed!!" severity failure;
375
        end if;
376
 
377
        -- load g1
378
        -----------
379
        loadOp(op_1, g1);
380
        -- verify
381
        readOp(op_1, data_read, base_width);
382
        if (g1(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
383
          write(Lw, string'("  g1 written in operand_1")); writeline(output, Lw);
384
        else
385
          write(Lw, string'("  failed to write g1 to operand_1!")); writeline(output, Lw);
386
          assert false report "Load g1 to op1 data verify failed!!" severity failure;
387
        end if;
388
 
389
        -- load R2
390
        -----------
391
        loadOp(op_2, R2);
392
        -- verify
393
        readOp(op_2, data_read, base_width);
394
        if (R2(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
395
          write(Lw, string'("  R^2 written in operand_2")); writeline(output, Lw);
396
        else
397
          write(Lw, string'("  failed to write R^2 to operand_2!")); writeline(output, Lw);
398
          assert false report "Load R2 to op2 data verify failed!!" severity failure;
399
        end if;
400
 
401
        -- load a=1
402
        ------------
403
        loadOp(op_3, one);
404
        -- verify
405
        readOp(op_3, data_read, base_width);
406
        if (one(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
407
          write(Lw, string'("  1 written in operand_3")); writeline(output, Lw);
408
        else
409
          write(Lw, string'("  failed to write 1 to operand_3!")); writeline(output, Lw);
410
          assert false report "Load 1 to op3 data verify failed!!" severity failure;
411
        end if;
412
 
413
        writeline(output, Lw);
414
        write(Lw, string'("----- Pre-computations: "));
415
        writeline(output, Lw);
416
 
417
        -- compute gt0
418
        ---------------
419
        core_x_sel_single <= "00"; -- g0
420
        core_y_sel_single <= "10"; -- R^2
421
        core_dest_op_single <= "00"; -- op_0 = (g0 * R) mod m
422
        wait until rising_edge(clk);
423
        timer := NOW;
424
        core_start <= '1';
425
        wait until rising_edge(clk);
426
        core_start <= '0';
427
        wait until core_ready = '1';
428
        timer := NOW-timer;
429
        waitclk(10);
430
        readOp(op_0, data_read, base_width);
431
        write(Lw, string'("  Computed gt0: "));
432
        hwrite(Lw, data_read(base_width-1 downto 0));
433
        writeline(output, Lw);
434
        write(Lw, string'("  Read gt0:     "));
435
        hwrite(Lw, gt0(base_width-1 downto 0));
436
        writeline(output, Lw);
437
        write(Lw, string'("  => calc time is "));
438
        write(Lw, string'(ToString(timer)));
439
        writeline(output, Lw);
440
        write(Lw, string'("  => expected time is "));
441 43 JonasDC
        write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
442 2 JonasDC
        writeline(output, Lw);
443
        if (gt0(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
444
          write(Lw, string'("  => gt0 is correct!")); writeline(output, Lw);
445
        else
446
          write(Lw, string'("  => Error: gt0 is incorrect!!!")); writeline(output, Lw);
447
          assert false report "gt0 is incorrect!!!" severity failure;
448
        end if;
449
 
450
        -- compute gt1
451
        ---------------
452
        core_x_sel_single <= "01"; -- g1
453
        core_y_sel_single <= "10"; -- R^2
454
        core_dest_op_single <= "01"; -- op_1 = (g1 * R) mod m
455
        wait until rising_edge(clk);
456
        timer := NOW;
457
        core_start <= '1';
458
        wait until rising_edge(clk);
459
        core_start <= '0';
460
        wait until core_ready = '1';
461
        timer := NOW-timer;
462
        waitclk(10);
463
        readOp(op_1, data_read, base_width);
464
        write(Lw, string'("  Computed gt1: "));
465
        hwrite(Lw, data_read(base_width-1 downto 0));
466
        writeline(output, Lw);
467
        write(Lw, string'("  Read gt1:     "));
468
        hwrite(Lw, gt1(base_width-1 downto 0));
469
        writeline(output, Lw);
470
        write(Lw, string'("  => calc time is "));
471
        write(Lw, string'(ToString(timer)));
472
        writeline(output, Lw);
473
        write(Lw, string'("  => expected time is "));
474 43 JonasDC
        write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
475 2 JonasDC
        writeline(output, Lw);
476
        if (gt1(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
477
          write(Lw, string'("  => gt1 is correct!")); writeline(output, Lw);
478
        else
479
          write(Lw, string'("  => Error: gt1 is incorrect!!!")); writeline(output, Lw);
480
          assert false report "gt1 is incorrect!!!" severity failure;
481
        end if;
482
 
483
        -- compute a
484
        -------------
485
        core_x_sel_single <= "10"; -- R^2
486
        core_y_sel_single <= "11"; -- 1
487
        core_dest_op_single <= "11"; -- op_3 = (R) mod m
488
        wait until rising_edge(clk);
489
        core_start <= '1';
490
        timer := NOW;
491
        wait until rising_edge(clk);
492
        core_start <= '0';
493
        wait until core_ready = '1';
494
        timer := NOW-timer;
495
        waitclk(10);
496
        readOp(op_3, data_read, base_width);
497
        write(Lw, string'("  Computed a=(R)mod m: "));
498
        hwrite(Lw, data_read(base_width-1 downto 0));
499
        writeline(output, Lw);
500
        write(Lw, string'("  Read (R)mod m:       "));
501
        hwrite(Lw, R(base_width-1 downto 0));
502
        writeline(output, Lw);
503
        write(Lw, string'("  => calc time is "));
504
        write(Lw, string'(ToString(timer)));
505
        writeline(output, Lw);
506
        write(Lw, string'("  => expected time is "));
507 43 JonasDC
        write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
508 2 JonasDC
        writeline(output, Lw);
509
        if (R(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
510
          write(Lw, string'("  => (R)mod m is correct!")); writeline(output, Lw);
511
        else
512
          write(Lw, string'("  => Error: (R)mod m is incorrect!!!")); writeline(output, Lw);
513
          assert false report "(R)mod m is incorrect!!!" severity failure;
514
        end if;
515
 
516
        -- compute gt01
517
        ---------------
518
        core_x_sel_single <= "00"; -- gt0
519
        core_y_sel_single <= "01"; -- gt1
520
        core_dest_op_single <= "10"; -- op_2 = (gt0 * gt1) mod m
521
        wait until rising_edge(clk);
522
        core_start <= '1';
523
        timer := NOW;
524
        wait until rising_edge(clk);
525
        core_start <= '0';
526
        wait until core_ready = '1';
527
        timer := NOW-timer;
528
        waitclk(10);
529
        readOp(op_2, data_read, base_width);
530
        write(Lw, string'("  Computed gt01: "));
531
        hwrite(Lw, data_read(base_width-1 downto 0));
532
        writeline(output, Lw);
533
        write(Lw, string'("  Read gt01:     "));
534
        hwrite(Lw, gt01(base_width-1 downto 0));
535
        writeline(output, Lw);
536
        write(Lw, string'("  => calc time is "));
537
        write(Lw, string'(ToString(timer)));
538
        writeline(output, Lw);
539
        write(Lw, string'("  => expected time is "));
540 43 JonasDC
        write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
541 2 JonasDC
        writeline(output, Lw);
542
        if (gt01(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
543
          write(Lw, string'("  => gt01 is correct!")); writeline(output, Lw);
544
        else
545
          write(Lw, string'("  => Error: gt01 is incorrect!!!")); writeline(output, Lw);
546
          assert false report "gt01 is incorrect!!!" severity failure;
547
        end if;
548
 
549
        -- load exponent fifo
550
        ----------------------
551
        writeline(output, Lw);
552
        write(Lw, string'("----- Loading exponent fifo: "));
553
        writeline(output, Lw);
554
        for i in (exponent_width/16)-1 downto 0 loop
555
          core_fifo_din <= e1((i*16)+15 downto (i*16)) & e0((i*16)+15 downto (i*16));
556
          wait until rising_edge(clk);
557
          core_fifo_push <= '1';
558
          wait until rising_edge(clk);
559
          assert (core_fifo_full='0' and core_fifo_nopush='0')
560
            report "Fifo error, full or nopush" severity failure;
561
          core_fifo_push <= '0';
562
          wait until rising_edge(clk);
563
        end loop;
564
        waitclk(10);
565 3 JonasDC
        write(Lw, string'("  => Done"));
566 2 JonasDC
        writeline(output, Lw);
567
 
568
        -- start exponentiation
569
        ------------------------
570
        writeline(output, Lw);
571
        write(Lw, string'("----- Starting exponentiation: "));
572
        writeline(output, Lw);
573 46 JonasDC
        core_exp_m <= '1';
574 2 JonasDC
        wait until rising_edge(clk);
575
        timer := NOW;
576
        core_start <= '1';
577
        wait until rising_edge(clk);
578
        core_start <= '0';
579
        wait until core_ready='1';
580
        timer := NOW-timer;
581
        waitclk(10);
582
        write(Lw, string'("  => calc time is "));
583
        write(Lw, string'(ToString(timer)));
584
        writeline(output, Lw);
585
        write(Lw, string'("  => expected time is "));
586 43 JonasDC
        write(Lw, ((C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD*7*exponent_width)/4);
587 2 JonasDC
        writeline(output, Lw);
588
        write(Lw, string'("  => Done"));
589 46 JonasDC
        core_exp_m <= '0';
590 2 JonasDC
        writeline(output, Lw);
591
 
592
        -- post-computations
593
        ---------------------
594
        writeline(output, Lw);
595
        write(Lw, string'("----- Post-computations: "));
596
        writeline(output, Lw);
597
        -- load in 1 to operand 2
598
        loadOp(op_2, one);
599
        -- verify
600
        readOp(op_2, data_read, base_width);
601
        if (one(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
602
          write(Lw, string'("  1 written in operand_2")); writeline(output, Lw);
603
        else
604
          write(Lw, string'("  failed to write 1 to operand_2!")); writeline(output, Lw);
605
          assert false report "Load 1 to op2 data verify failed!!" severity failure;
606
        end if;
607
        -- compute result
608
        core_x_sel_single <= "11"; -- a
609
        core_y_sel_single <= "10"; -- 1
610
        core_dest_op_single <= "11"; -- op_3 = (a) mod m
611
        wait until rising_edge(clk);
612
        timer := NOW;
613
        core_start <= '1';
614
        wait until rising_edge(clk);
615
        core_start <= '0';
616
        wait until core_ready = '1';
617
        timer := NOW-timer;
618
        waitclk(10);
619
        readOp(op_3, data_read, base_width);
620
        write(Lw, string'("  Computed result: "));
621
        hwrite(Lw, data_read(base_width-1 downto 0));
622
        writeline(output, Lw);
623
        write(Lw, string'("  => calc time is "));
624
        write(Lw, string'(ToString(timer)));
625
        writeline(output, Lw);
626
        write(Lw, string'("  => expected time is "));
627 43 JonasDC
        write(Lw, (C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD);
628 2 JonasDC
        writeline(output, Lw);
629
 
630
      when 12 => -- check with result
631
        hread(L, result(base_width-1 downto 0), good_value);
632
        assert good_value report "Can not read result! (wrong lenght?)" severity failure;
633
        writeline(output, Lw);
634
        write(Lw, string'("----- verifying result: "));
635
        writeline(output, Lw);
636
        write(Lw, string'("  Read result:     "));
637
        hwrite(Lw, result(base_width-1 downto 0));
638
        writeline(output, Lw);
639
        write(Lw, string'("  Computed result: "));
640
        hwrite(Lw, data_read(base_width-1 downto 0));
641
        writeline(output, Lw);
642
        if (result(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
643
          write(Lw, string'("  => Result is correct!")); writeline(output, Lw);
644
        else
645
          write(Lw, string'("  Error: result is incorrect!!!")); writeline(output, Lw);
646
          assert false report "result is incorrect!!!" severity failure;
647
        end if;
648
        writeline(output, Lw);
649
 
650
      when others =>
651
        assert false report "undefined state!" severity failure;
652
    end case;
653
 
654
    if (param_count = 12) then
655
      param_count := 0;
656
    else
657
      param_count := param_count+1;
658
    end if;
659
  end loop;
660
 
661
  wait for 1 us;
662
  assert false report "End of simulation" severity failure;
663
 
664
end process;
665
 
666
------------------------------------------
667
-- Multiplier core instance
668
------------------------------------------
669 24 JonasDC
the_multiplier : mod_sim_exp.mod_sim_exp_pkg.mod_sim_exp_core
670 43 JonasDC
generic map(
671
  C_NR_BITS_TOTAL   => C_NR_BITS_TOTAL,
672
  C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
673
  C_NR_STAGES_LOW   => C_NR_STAGES_LOW,
674
  C_SPLIT_PIPELINE  => C_SPLIT_PIPELINE
675
)
676 2 JonasDC
port map(
677
  clk   => clk,
678
  reset => reset,
679
-- operand memory interface (plb shared memory)
680
  write_enable => core_write_enable,
681
  data_in      => core_data_in,
682
  rw_address   => core_rw_address,
683
  data_out     => core_data_out,
684
  collision    => core_mem_collision,
685
-- op_sel fifo interface
686
  fifo_din    => core_fifo_din,
687
  fifo_push   => core_fifo_push,
688
  fifo_full   => core_fifo_full,
689
  fifo_nopush => core_fifo_nopush,
690
-- ctrl signals
691
  start          => core_start,
692 46 JonasDC
  exp_m          => core_exp_m,
693 2 JonasDC
  ready          => core_ready,
694
  x_sel_single   => core_x_sel_single,
695
  y_sel_single   => core_y_sel_single,
696
  dest_op_single => core_dest_op_single,
697
  p_sel          => core_p_sel,
698
  calc_time      => calc_time
699
);
700
 
701
end test;

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