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[/] [mod_sim_exp/] [trunk/] [bench/] [vhdl/] [multiplier_tb.vhd] - Blame information for rev 26

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1 26 JonasDC
----------------------------------------------------------------------  
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----  mod_sim_exp_core_tb                                               ---- 
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----                                                              ---- 
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----  This file is part of the                                    ----
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----    Modular Simultaneous Exponentiation Core project          ---- 
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----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
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----                                                              ---- 
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----  Description                                                 ---- 
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----    testbench for the modular simultaneous exponentiation     ----
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----    core. Performs some exponentiations to verify the design  ----
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----    Takes input parameters from sim_input.txt en writes       ----
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----    result and output to sim_output.txt                       ----
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----                                                              ----
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----  Dependencies:                                               ----
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----    - multiplier_core                                         ----
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----                                                              ----
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----  Authors:                                                    ----
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----      - Geoffrey Ottoy, DraMCo research group                 ----
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----      - Jonas De Craene, JonasDC@opencores.org                ---- 
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----                                                              ---- 
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---------------------------------------------------------------------- 
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----                                                              ---- 
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
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----                                                              ---- 
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---- This source file may be used and distributed without         ---- 
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---- restriction provided that this copyright statement is not    ---- 
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---- removed from the file and that any derivative work contains  ---- 
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---- the original copyright notice and the associated disclaimer. ---- 
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----                                                              ---- 
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---- This source file is free software; you can redistribute it   ---- 
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---- and/or modify it under the terms of the GNU Lesser General   ---- 
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---- Public License as published by the Free Software Foundation; ---- 
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---- either version 2.1 of the License, or (at your option) any   ---- 
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---- later version.                                               ---- 
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----                                                              ---- 
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---- This source is distributed in the hope that it will be       ---- 
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---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
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---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
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---- details.                                                     ---- 
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----                                                              ---- 
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---- You should have received a copy of the GNU Lesser General    ---- 
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---- Public License along with this source; if not, download it   ---- 
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---- from http://www.opencores.org/lgpl.shtml                     ---- 
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----                                                              ---- 
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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library std;
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use std.textio.all;
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library ieee;
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use ieee.std_logic_textio.all;
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library mod_sim_exp;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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entity multiplier_tb is
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end multiplier_tb;
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architecture test of multiplier_tb is
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  constant nr_stages  : integer := 96;
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  constant clk_period : time := 10 ns;
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  signal clk          : std_logic := '0';
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  signal reset        : std_logic := '1';
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  file input          : text open read_mode is "src/sim_mult_input.txt";
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  file output         : text open write_mode is "out/sim_mult_output.txt";
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  ------------------------------------------------------------------
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  -- Signals for multiplier core memory space
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  ------------------------------------------------------------------
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  constant n : integer := 1536;
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  constant t : integer := 96;
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  constant tl : integer := 0;
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  -- data busses
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  signal xy   : std_logic_vector(n-1 downto 0);  -- x and y operand data bus RAM -> multiplier
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  signal m    : std_logic_vector(n-1 downto 0);  -- modulus data bus RAM -> multiplier
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  signal r    : std_logic_vector(n-1 downto 0);  -- result data bus RAM <- multiplier
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  -- control signals
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  signal p_sel           : std_logic_vector(1 downto 0); -- operand selection 
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  signal result_dest_op   : std_logic_vector(1 downto 0); -- result destination operand
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  signal ready       : std_logic;
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  signal start       : std_logic;
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  signal load_op          : std_logic;
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  signal load_x         : std_logic;
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  signal load_m           : std_logic;
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  signal load_result      : std_logic;
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begin
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------------------------------------------
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-- Generate clk
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------------------------------------------
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clk_process : process
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begin
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  while (true) loop
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    clk <= '0';
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    wait for clk_period/2;
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    clk <= '1';
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    wait for clk_period/2;
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  end loop;
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end process;
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------------------------------------------
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-- Stimulus Process
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------------------------------------------
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stim_proc : process
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  procedure waitclk(n : natural := 1) is
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  begin
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    for i in 1 to n loop
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      wait until rising_edge(clk);
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    end loop;
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  end waitclk;
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  function ToString(constant Timeval : time) return string is
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    variable StrPtr : line;
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  begin
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    write(StrPtr,Timeval);
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    return StrPtr.all;
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  end ToString;
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  -- variables to read file
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  variable L : line;
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  variable Lw : line;
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  variable x_op : std_logic_vector((n-1) downto 0) := (others=>'0');
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  variable y_op : std_logic_vector((n-1) downto 0) := (others=>'0');
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  variable m_op : std_logic_vector((n-1) downto 0) := (others=>'0');
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  variable result : std_logic_vector((n-1) downto 0) := (others=>'0');
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  variable one : std_logic_vector(2047 downto 0) := std_logic_vector(conv_unsigned(1, 2048));
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  variable data_read : std_logic_vector(2047 downto 0) := (others=>'0');
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  variable good_value : boolean;
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  variable param_count : integer := 0;
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  variable timer : time;
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begin
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  -- initialisation
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  xy <= (others=>'0');
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  m <= (others=>'0');
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  start <='0';
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  reset <= '0';
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  p_sel <= "11";
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  load_x <= '0';
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  -- Generate active high reset signal
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  reset <= '1';
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  waitclk(10);
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  reset <= '0';
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  waitclk(10);
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  while not endfile(input) loop
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    readline(input, L); -- read next line
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    next when L(1)='-'; -- skip comment lines
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    -- read input values
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    case param_count is
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      when 0 => -- base width
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        hread(L, x_op, good_value);
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        assert good_value report "Can not read x operand" severity failure;
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        assert false report "Simulating multiplication" severity note;
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        write(Lw, string'("----------------------------------------------"));
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        writeline(output, Lw);
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        write(Lw, string'("--              MULTIPLICATION              --"));
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        writeline(output, Lw);
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        write(Lw, string'("----------------------------------------------"));
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        writeline(output, Lw);
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        write(Lw, string'("----- Variables used:"));
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        writeline(output, Lw);
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        write(Lw, string'("x: "));
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        hwrite(Lw, x_op);
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        writeline(output, Lw);
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      when 1 =>
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        hread(L, y_op, good_value);
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        assert good_value report "Can not read y operand" severity failure;
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        write(Lw, string'("y: "));
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        hwrite(Lw, y_op);
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        writeline(output, Lw);
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      when 2 =>
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        hread(L, m_op, good_value);
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        assert good_value report "Can not read m operand" severity failure;
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        write(Lw, string'("m: "));
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        hwrite(Lw, m_op);
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        writeline(output, Lw);
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        -- load in x
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        xy <= x_op;
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        wait until rising_edge(clk);
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        load_x <='1';
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        wait until rising_edge(clk);
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        load_x <='0';
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        -- put y and m on the bus
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        xy <= y_op;
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        m <= m_op;
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        wait until rising_edge(clk);
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        -- start multiplication and wait for result
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        start <= '1';
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        wait until rising_edge(clk);
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        start <= '0';
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        wait until ready='1';
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        wait until rising_edge(clk);
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        writeline(output, Lw);
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        write(Lw, string'("  Computed result: "));
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        hwrite(Lw, r);
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        writeline(output, Lw);
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      when 3 =>
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        hread(L, result, good_value);
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        assert good_value report "Can not read result" severity failure;
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        write(Lw, string'("  Read result:     "));
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        hwrite(Lw, result);
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        writeline(output, Lw);
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        if (r = result) then
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          write(Lw, string'("  => result is correct!")); writeline(output, Lw);
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        else
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          write(Lw, string'("  => Error: result is incorrect!!!")); writeline(output, Lw);
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          assert false report "result is incorrect!!!" severity error;
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        end if;
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      when others =>
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        assert false report "undefined state!" severity failure;
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    end case;
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    if (param_count = 3) then
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      param_count := 0;
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    else
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      param_count := param_count+1;
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    end if;
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  end loop;
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  wait for 1 us;
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  assert false report "End of simulation" severity failure;
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end process;
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------------------------------------------
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-- Multiplier instance
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------------------------------------------
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the_multiplier : mont_multiplier
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  generic map(
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    n          => n,
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    nr_stages  => t,
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    stages_low => tl
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  )
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  port map(
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    core_clk => clk,
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    xy       => xy,
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    m        => m,
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    r        => r,
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    start    => start,
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    reset    => reset,
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    p_sel    => p_sel,
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    load_x   => load_x,
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    ready    => ready
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  );
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end test;

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