OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_core.vhd] - Blame information for rev 75

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 JonasDC
----------------------------------------------------------------------  
2 24 JonasDC
----  mod_sim_exp_core                                            ---- 
3 3 JonasDC
----                                                              ---- 
4
----  This file is part of the                                    ----
5
----    Modular Simultaneous Exponentiation Core project          ---- 
6
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
7
----                                                              ---- 
8
----  Description                                                 ---- 
9
----    toplevel of a modular simultaneous exponentiation core    ----
10
----    using a pipelined montgommery multiplier with split       ----
11 24 JonasDC
----    pipeline and auto-run support                             ----
12 3 JonasDC
----                                                              ----
13
----  Dependencies:                                               ----
14
----    - mont_mult_sys_pipeline                                  ----
15
----    - operand_mem                                             ----
16
----    - fifo_primitive                                          ----
17
----    - mont_ctrl                                               ----
18
----                                                              ----
19
----  Authors:                                                    ----
20
----      - Geoffrey Ottoy, DraMCo research group                 ----
21
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
22
----                                                              ---- 
23
---------------------------------------------------------------------- 
24
----                                                              ---- 
25
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
26
----                                                              ---- 
27
---- This source file may be used and distributed without         ---- 
28
---- restriction provided that this copyright statement is not    ---- 
29
---- removed from the file and that any derivative work contains  ---- 
30
---- the original copyright notice and the associated disclaimer. ---- 
31
----                                                              ---- 
32
---- This source file is free software; you can redistribute it   ---- 
33
---- and/or modify it under the terms of the GNU Lesser General   ---- 
34
---- Public License as published by the Free Software Foundation; ---- 
35
---- either version 2.1 of the License, or (at your option) any   ---- 
36
---- later version.                                               ---- 
37
----                                                              ---- 
38
---- This source is distributed in the hope that it will be       ---- 
39
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
40
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
41
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
42
---- details.                                                     ---- 
43
----                                                              ---- 
44
---- You should have received a copy of the GNU Lesser General    ---- 
45
---- Public License along with this source; if not, download it   ---- 
46
---- from http://www.opencores.org/lgpl.shtml                     ---- 
47
----                                                              ---- 
48
----------------------------------------------------------------------
49 2 JonasDC
 
50 3 JonasDC
library ieee;
51
use ieee.std_logic_1164.all;
52
use ieee.std_logic_arith.all;
53
use ieee.std_logic_unsigned.all;
54 2 JonasDC
 
55 3 JonasDC
library mod_sim_exp;
56
use mod_sim_exp.mod_sim_exp_pkg.all;
57 63 JonasDC
use mod_sim_exp.std_functions.all;
58 3 JonasDC
 
59 24 JonasDC
-- toplevel of the modular simultaneous exponentiation core
60
-- contains an operand and modulus ram, multiplier, an exponent fifo
61
-- and control logic
62
entity mod_sim_exp_core is
63 43 JonasDC
  generic(
64
    C_NR_BITS_TOTAL   : integer := 1536;
65
    C_NR_STAGES_TOTAL : integer := 96;
66
    C_NR_STAGES_LOW   : integer := 32;
67 63 JonasDC
    C_SPLIT_PIPELINE  : boolean := true;
68 69 JonasDC
    C_FIFO_DEPTH      : integer := 32;
69 75 JonasDC
    C_MEM_STYLE       : string  := "asym"; -- xil_prim, generic, asym are valid options
70 69 JonasDC
    C_DEVICE          : string  := "xilinx"   -- xilinx, altera are valid options
71 43 JonasDC
  );
72 3 JonasDC
  port(
73
    clk   : in  std_logic;
74
    reset : in  std_logic;
75
      -- operand memory interface (plb shared memory)
76 24 JonasDC
    write_enable : in  std_logic; -- write data to operand ram
77
    data_in      : in  std_logic_vector (31 downto 0);  -- operand ram data in
78 74 JonasDC
    rw_address   : in  std_logic_vector (8 downto 0); -- operand ram address bus
79 24 JonasDC
    data_out     : out std_logic_vector (31 downto 0);  -- operand ram data out
80
    collision    : out std_logic; -- write collision
81 3 JonasDC
      -- op_sel fifo interface
82 24 JonasDC
    fifo_din    : in  std_logic_vector (31 downto 0); -- exponent fifo data in
83
    fifo_push   : in  std_logic;  -- push data in exponent fifo
84
    fifo_full   : out std_logic;  -- high if fifo is full
85
    fifo_nopush : out std_logic;  -- high if error during push
86
      -- control signals
87
    start          : in  std_logic; -- start multiplication/exponentiation
88 45 JonasDC
    exp_m          : in  std_logic; -- single multiplication if low, exponentiation if high
89 24 JonasDC
    ready          : out std_logic; -- calculations done
90 74 JonasDC
    x_sel_single   : in  std_logic_vector (1 downto 0); -- single multiplication x operand selection
91
    y_sel_single   : in  std_logic_vector (1 downto 0); -- single multiplication y operand selection
92
    dest_op_single : in  std_logic_vector (1 downto 0); -- result destination operand selection
93 24 JonasDC
    p_sel          : in  std_logic_vector (1 downto 0); -- pipeline part selection
94 63 JonasDC
    calc_time      : out std_logic;
95 74 JonasDC
    modulus_sel    : in  std_logic   -- selects which modulus to use for multiplications
96 3 JonasDC
  );
97 24 JonasDC
end mod_sim_exp_core;
98 2 JonasDC
 
99 3 JonasDC
 
100 24 JonasDC
architecture Structural of mod_sim_exp_core is
101 74 JonasDC
  -- constants
102
  constant nr_op : integer := 4;
103
  constant nr_m  : integer := 2;
104
 
105 24 JonasDC
  -- data busses
106 69 JonasDC
  signal xy : std_logic_vector(C_NR_BITS_TOTAL-1 downto 0);  -- x and y operand data bus RAM -> multiplier
107
  signal m  : std_logic_vector(C_NR_BITS_TOTAL-1 downto 0);  -- modulus data bus RAM -> multiplier
108
  signal r  : std_logic_vector(C_NR_BITS_TOTAL-1 downto 0);  -- result data bus RAM <- multiplier
109
 
110 24 JonasDC
  -- control signals
111 69 JonasDC
  signal op_sel         : std_logic_vector(1 downto 0); -- operand selection
112
  signal result_dest_op : std_logic_vector(1 downto 0); -- result destination operand
113
  signal mult_ready     : std_logic;
114
  signal start_mult     : std_logic;
115 24 JonasDC
  signal load_x         : std_logic;
116 69 JonasDC
  signal load_result    : std_logic;
117 74 JonasDC
  signal modulus_sel_i  : std_logic_vector(0 downto 0);
118 69 JonasDC
 
119 24 JonasDC
  -- fifo signals
120 3 JonasDC
  signal fifo_empty : std_logic;
121
  signal fifo_pop   : std_logic;
122
  signal fifo_nopop : std_logic;
123
  signal fifo_dout  : std_logic_vector(31 downto 0);
124 2 JonasDC
begin
125
 
126 3 JonasDC
  -- The actual multiplier
127 36 JonasDC
  the_multiplier : mont_multiplier
128 24 JonasDC
  generic map(
129 69 JonasDC
    n     => C_NR_BITS_TOTAL,
130
    t     => C_NR_STAGES_TOTAL,
131
    tl    => C_NR_STAGES_LOW,
132 43 JonasDC
    split => C_SPLIT_PIPELINE
133 3 JonasDC
  )
134
  port map(
135
    core_clk => clk,
136 24 JonasDC
    xy       => xy,
137 3 JonasDC
    m        => m,
138
    r        => r,
139
    start    => start_mult,
140
    reset    => reset,
141
    p_sel    => p_sel,
142 24 JonasDC
    load_x   => load_x,
143 3 JonasDC
    ready    => mult_ready
144
  );
145
 
146
  -- Block ram memory for storing the operands and the modulus
147 69 JonasDC
  the_memory : operand_mem
148 34 JonasDC
  generic map(
149 69 JonasDC
    width     => C_NR_BITS_TOTAL,
150 74 JonasDC
    nr_op     => nr_op,
151
    nr_m      => nr_m,
152 69 JonasDC
    mem_style => C_MEM_STYLE,
153
    device    => C_DEVICE
154 34 JonasDC
  )
155 24 JonasDC
  port map(
156 3 JonasDC
    data_in        => data_in,
157
    data_out       => data_out,
158
    rw_address     => rw_address,
159 39 JonasDC
    write_enable   => write_enable,
160 3 JonasDC
    op_sel         => op_sel,
161 24 JonasDC
    xy_out         => xy,
162 3 JonasDC
    m              => m,
163
    result_in      => r,
164
    load_result    => load_result,
165 24 JonasDC
    result_dest_op => result_dest_op,
166 3 JonasDC
    collision      => collision,
167 63 JonasDC
    clk            => clk,
168 74 JonasDC
    modulus_sel    => modulus_sel_i
169 3 JonasDC
  );
170 39 JonasDC
 
171 74 JonasDC
  modulus_sel_i(0) <= modulus_sel;
172 45 JonasDC
        result_dest_op <= dest_op_single when exp_m = '0' else "11"; -- in autorun mode we always store the result in operand3
173 2 JonasDC
 
174 69 JonasDC
  -- A fifo for exponentiation mode
175
  xil_prim_fifo : if C_MEM_STYLE="xil_prim" generate
176
    the_exponent_fifo : fifo_primitive
177
    port map(
178
      clk    => clk,
179
      din    => fifo_din,
180
      dout   => fifo_dout,
181
      empty  => fifo_empty,
182
      full   => fifo_full,
183
      push   => fifo_push,
184
      pop    => fifo_pop,
185
      reset  => reset,
186
      nopop  => fifo_nopop,
187
      nopush => fifo_nopush
188
    );
189
  end generate;
190
        gen_fifo : if (C_MEM_STYLE="generic") or (C_MEM_STYLE="asym") generate
191
    the_exponent_fifo : fifo_generic
192
    generic map(
193
      depth => C_FIFO_DEPTH
194
    )
195
    port map(
196
      clk    => clk,
197
      din    => fifo_din,
198
      dout   => fifo_dout,
199
      empty  => fifo_empty,
200
      full   => fifo_full,
201
      push   => fifo_push,
202
      pop    => fifo_pop,
203
      reset  => reset,
204
      nopop  => fifo_nopop,
205
      nopush => fifo_nopush
206
    );
207
  end generate;
208
 
209 3 JonasDC
  -- The control logic for the core
210 24 JonasDC
  the_control_unit : mont_ctrl
211
  port map(
212 3 JonasDC
    clk              => clk,
213
    reset            => reset,
214
    start            => start,
215
    x_sel_single     => x_sel_single,
216
    y_sel_single     => y_sel_single,
217 45 JonasDC
    run_auto         => exp_m,
218 3 JonasDC
    op_buffer_empty  => fifo_empty,
219
    op_sel_buffer    => fifo_dout,
220
    read_buffer      => fifo_pop,
221
    done             => ready,
222
    calc_time        => calc_time,
223
    op_sel           => op_sel,
224 24 JonasDC
    load_x           => load_x,
225 3 JonasDC
    load_result      => load_result,
226
    start_multiplier => start_mult,
227
    multiplier_ready => mult_ready
228
  );
229 2 JonasDC
 
230 24 JonasDC
end Structural;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.