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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_pkg.vhd] - Blame information for rev 3

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Line No. Rev Author Line
1 3 JonasDC 
 
2 
library ieee;
3 
use ieee.std_logic_1164.all;
4 
use ieee.std_logic_unsigned.all;
5 
 
6 
package mod_sim_exp_pkg is
7 
 
8 
  component adder_n is
9 
    generic (
10 
      width       : integer := 1536;
11 
      block_width : integer := 8
12 
    );
13 
    port (
14 
      core_clk : in std_logic;
15 
      a        : in std_logic_vector((width-1) downto 0);
16 
      b        : in std_logic_vector((width-1) downto 0);
17 
      cin      : in std_logic;
18 
      cout     : out std_logic;
19 
      s        : out std_logic_vector((width-1) downto 0)
20 
    );
21 
  end component adder_n;
22 
 
23 
  component adder_block is
24 
    generic (
25 
      width : integer := 32
26 
    );
27 
    port (
28 
      core_clk : in std_logic;
29 
      a        : in  std_logic_vector((width-1) downto 0);
30 
      b        : in  std_logic_vector((width-1) downto 0);
31 
      cin      : in std_logic;
32 
      cout     : out std_logic;
33 
      s        : out  std_logic_vector((width-1) downto 0)
34 
    );
35 
  end component adder_block;
36 
 
37 
  component autorun_cntrl is
38 
    port (
39 
      clk              : in  std_logic;
40 
      reset            : in  std_logic;
41 
      start            : in  std_logic;
42 
      done             : out  std_logic;
43 
      op_sel           : out  std_logic_vector (1 downto 0);
44 
      start_multiplier : out  std_logic;
45 
      multiplier_done  : in  std_logic;
46 
      read_buffer      : out  std_logic;
47 
      buffer_din       : in  std_logic_vector (31 downto 0);
48 
      buffer_empty     : in  std_logic
49 
    );
50 
  end component autorun_cntrl;
51 
 
52 
  component cell_1b_adder is
53 
    port (
54 
      a          : in  std_logic;
55 
      mux_result : in  std_logic;
56 
      cin        : in  std_logic;
57 
      cout       : out  std_logic;
58 
      r          : out  std_logic
59 
    );
60 
  end component cell_1b_adder;
61 
 
62 
  component cell_1b_mux is
63 
    port (
64 
      my     : in  std_logic;
65 
      y      : in  std_logic;
66 
      m      : in  std_logic;
67 
      x      : in  std_logic;
68 
      q      : in  std_logic;
69 
      result : out std_logic
70 
    );
71 
  end component cell_1b_mux;
72 
 
73 
  component cell_1b is
74 
    port (
75 
      my   : in  std_logic;
76 
      y    : in  std_logic;
77 
      m    : in  std_logic;
78 
      x    : in  std_logic;
79 
      q    : in  std_logic;
80 
      a    : in  std_logic;
81 
      cin  : in  std_logic;
82 
      cout : out std_logic;
83 
      r    : out std_logic
84 
    );
85 
  end component cell_1b;
86 
 
87 
  component counter_sync is
88 
    generic(
89 
      max_value : integer := 1024
90 
    );
91 
    port(
92 
      reset_value : in integer;
93 
      core_clk    : in std_logic;
94 
      ce          : in std_logic;
95 
      reset       : in std_logic;
96 
      overflow    : out std_logic
97 
    );
98 
  end component counter_sync;
99 
 
100 
  component d_flip_flop is
101 
    port(
102 
      core_clk : in  std_logic;
103 
      reset    : in  std_logic;
104 
      din      : in  std_logic;
105 
      dout     : out std_logic
106 
    );
107 
  end component d_flip_flop;
108 
 
109 
  component fifo_primitive is
110 
    port (
111 
      clk    : in  std_logic;
112 
      din    : in  std_logic_vector (31 downto 0);
113 
      dout   : out  std_logic_vector (31 downto 0);
114 
      empty  : out  std_logic;
115 
      full   : out  std_logic;
116 
      push   : in  std_logic;
117 
      pop    : in  std_logic;
118 
      reset  : in std_logic;
119 
      nopop  : out std_logic;
120 
      nopush : out std_logic
121 
    );
122 
  end component fifo_primitive;
123 
 
124 
  component first_stage is
125 
    generic(
126 
      width : integer := 16 -- must be the same as width of the standard stage
127 
    );
128 
    port(
129 
      core_clk : in  std_logic;
130 
      my       : in  std_logic_vector((width) downto 0);
131 
      y        : in  std_logic_vector((width) downto 0);
132 
      m        : in  std_logic_vector((width) downto 0);
133 
      xin      : in  std_logic;
134 
      xout     : out std_logic;
135 
      qout     : out std_logic;
136 
      a_msb    : in  std_logic;
137 
      cout     : out std_logic;
138 
      start    : in  std_logic;
139 
      reset    : in  std_logic;
140 
      done     : out std_logic;
141 
      r        : out std_logic_vector((width-1) downto 0)
142 
    );
143 
  end component first_stage;
144 
 
145 
  component last_stage is
146 
    generic(
147 
      width : integer := 16 -- must be the same as width of the standard stage
148 
    );
149 
    port(
150 
      core_clk : in  std_logic;
151 
      my       : in  std_logic_vector((width-1) downto 0);
152 
      y        : in  std_logic_vector((width-2) downto 0);
153 
      m        : in  std_logic_vector((width-2) downto 0);
154 
      xin      : in  std_logic;
155 
      qin      : in  std_logic;
156 
      cin      : in  std_logic;
157 
      start    : in  std_logic;
158 
      reset    : in  std_logic;
159 
      r        : out std_logic_vector((width+1) downto 0)
160 
    );
161 
  end component last_stage;
162 
 
163 
  component modulus_ram is
164 
    port(
165 
      clk           : in std_logic;
166 
      modulus_addr  : in std_logic_vector(5 downto 0);
167 
      write_modulus : in std_logic;
168 
      modulus_in    : in std_logic_vector(31 downto 0);
169 
      modulus_out   : out std_logic_vector(1535 downto 0)
170 
    );
171 
  end component modulus_ram;
172 
 
173 
  component mont_ctrl is
174 
    port (
175 
      clk   : in std_logic;
176 
      reset : in std_logic;
177 
        -- bus side
178 
      start           : in std_logic;
179 
      x_sel_single    : in std_logic_vector(1 downto 0);
180 
      y_sel_single    : in std_logic_vector(1 downto 0);
181 
      run_auto        : in std_logic;
182 
      op_buffer_empty : in std_logic;
183 
      op_sel_buffer   : in std_logic_vector(31 downto 0);
184 
      read_buffer     : out std_logic;
185 
      buffer_noread   : in std_logic;
186 
      done            : out std_logic;
187 
      calc_time       : out std_logic;
188 
        -- multiplier side
189 
      op_sel           : out std_logic_vector(1 downto 0);
190 
      load_x           : out std_logic;
191 
      load_result      : out std_logic;
192 
      start_multiplier : out std_logic;
193 
      multiplier_ready : in std_logic
194 
    );
195 
  end component mont_ctrl;
196 
 
197 
  component mont_mult_sys_pipeline is
198 
    generic (
199 
      n          : integer := 1536;
200 
      nr_stages  : integer := 96; --(divides n, bits_low & (n-bits_low))
201 
      stages_low : integer := 32
202 
    );
203 
    port (
204 
      core_clk : in std_logic;
205 
      xy       : in std_logic_vector((n-1) downto 0);
206 
      m        : in std_logic_vector((n-1) downto 0);
207 
      r        : out std_logic_vector((n-1) downto 0);
208 
      start    : in std_logic;
209 
      reset    : in std_logic;
210 
      p_sel    : in std_logic_vector(1 downto 0);
211 
      load_x   : in std_logic;
212 
      ready    : out std_logic
213 
    );
214 
  end component mont_mult_sys_pipeline;
215 
 
216 
  component multiplier_core is
217 
    port(
218 
      clk   : in  std_logic;
219 
      reset : in  std_logic;
220 
        -- operand memory interface (plb shared memory)
221 
      write_enable : in  std_logic;
222 
      data_in      : in  std_logic_vector (31 downto 0);
223 
      rw_address   : in  std_logic_vector (8 downto 0);
224 
      data_out     : out std_logic_vector (31 downto 0);
225 
      collision    : out std_logic;
226 
        -- op_sel fifo interface
227 
      fifo_din    : in  std_logic_vector (31 downto 0);
228 
      fifo_push   : in  std_logic;
229 
      fifo_full   : out std_logic;
230 
      fifo_nopush : out std_logic;
231 
        -- ctrl signals
232 
      start          : in  std_logic;
233 
      run_auto       : in  std_logic;
234 
      ready          : out std_logic;
235 
      x_sel_single   : in  std_logic_vector (1 downto 0);
236 
      y_sel_single   : in  std_logic_vector (1 downto 0);
237 
      dest_op_single : in  std_logic_vector (1 downto 0);
238 
      p_sel          : in  std_logic_vector (1 downto 0);
239 
      calc_time      : out std_logic
240 
    );
241 
  end component multiplier_core;
242 
 
243 
  component operand_dp is
244 
    port (
245 
      clka  : in std_logic;
246 
      wea   : in std_logic_vector(0 downto 0);
247 
      addra : in std_logic_vector(5 downto 0);
248 
      dina  : in std_logic_vector(31 downto 0);
249 
      douta : out std_logic_vector(511 downto 0);
250 
      clkb  : in std_logic;
251 
      web   : in std_logic_vector(0 downto 0);
252 
      addrb : in std_logic_vector(5 downto 0);
253 
      dinb  : in std_logic_vector(511 downto 0);
254 
      doutb : out std_logic_vector(31 downto 0)
255 
    );
256 
  end component operand_dp;
257 
 
258 
  component operand_mem is
259 
    generic(n : integer := 1536
260 
    );
261 
    port(
262 
        -- data interface (plb side)
263 
      data_in    : in  std_logic_vector(31 downto 0);
264 
      data_out   : out  std_logic_vector(31 downto 0);
265 
      rw_address : in  std_logic_vector(8 downto 0);
266 
        -- address structure:
267 
        -- bit:  8   -> '1': modulus
268 
        --              '0': operands
269 
        -- bits: 7-6 -> operand_in_sel in case of bit 8 = '0'
270 
        --              don't care in case of modulus
271 
        -- bits: 5-0 -> modulus_addr / operand_addr resp.
272 
 
273 
        -- operand interface (multiplier side)
274 
      op_sel    : in  std_logic_vector(1 downto 0);
275 
      xy_out    : out  std_logic_vector(1535 downto 0);
276 
      m         : out  std_logic_vector(1535 downto 0);
277 
      result_in : in std_logic_vector(1535 downto 0);
278 
        -- control signals
279 
      load_op        : in std_logic;
280 
      load_m         : in std_logic;
281 
      load_result    : in std_logic;
282 
      result_dest_op : in std_logic_vector(1 downto 0);
283 
      collision      : out std_logic;
284 
        -- system clock
285 
      clk : in  std_logic
286 
    );
287 
  end component operand_mem;
288 
 
289 
  component operand_ram is
290 
    port( -- write_operand_ack voorzien?
291 
      -- global ports
292 
      clk       : in std_logic;
293 
      collision : out std_logic;
294 
      -- bus side connections (32-bit serial)
295 
      operand_addr   : in std_logic_vector(5 downto 0);
296 
      operand_in     : in std_logic_vector(31 downto 0);
297 
      operand_in_sel : in std_logic_vector(1 downto 0);
298 
      result_out     : out std_logic_vector(31 downto 0);
299 
      write_operand  : in std_logic;
300 
      -- multiplier side connections (1536 bit parallel)
301 
      result_dest_op  : in std_logic_vector(1 downto 0);
302 
      operand_out     : out std_logic_vector(1535 downto 0);
303 
      operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side
304 
      write_result    : in std_logic;
305 
      result_in       : in std_logic_vector(1535 downto 0)
306 
    );
307 
  end component operand_ram;
308 
 
309 
  component operands_sp is
310 
    port (
311 
      clka  : in std_logic;
312 
      wea   : in std_logic_vector(0 downto 0);
313 
      addra : in std_logic_vector(4 downto 0);
314 
      dina  : in std_logic_vector(31 downto 0);
315 
      douta : out std_logic_vector(511 downto 0)
316 
    );
317 
  end component operands_sp;
318 
 
319 
  component register_1b is
320 
    port(
321 
      core_clk : in  std_logic;
322 
      ce       : in  std_logic;
323 
      reset    : in  std_logic;
324 
      din      : in  std_logic;
325 
      dout     : out std_logic
326 
    );
327 
  end component register_1b;
328 
 
329 
  component register_n is
330 
    generic(
331 
      n : integer := 4
332 
    );
333 
    port(
334 
      core_clk : in  std_logic;
335 
      ce       : in  std_logic;
336 
      reset    : in  std_logic;
337 
      din      : in  std_logic_vector((n-1) downto 0);
338 
      dout     : out std_logic_vector((n-1) downto 0)
339 
    );
340 
  end component register_n;
341 
 
342 
  component standard_cell_block is
343 
    generic (
344 
      width : integer := 16
345 
    );
346 
    port (
347 
      my   : in  std_logic_vector((width-1) downto 0);
348 
      y    : in  std_logic_vector((width-1) downto 0);
349 
      m    : in  std_logic_vector((width-1) downto 0);
350 
      x    : in  std_logic;
351 
      q    : in  std_logic;
352 
      a    : in  std_logic_vector((width-1) downto 0);
353 
      cin  : in std_logic;
354 
      cout : out std_logic;
355 
      r    : out  std_logic_vector((width-1) downto 0)
356 
    );
357 
  end component standard_cell_block;
358 
 
359 
  component standard_stage is
360 
    generic(
361 
      width : integer := 32
362 
    );
363 
    port(
364 
      core_clk : in  std_logic;
365 
      my       : in  std_logic_vector((width-1) downto 0);
366 
      y        : in  std_logic_vector((width-1) downto 0);
367 
      m        : in  std_logic_vector((width-1) downto 0);
368 
      xin      : in  std_logic;
369 
      qin      : in  std_logic;
370 
      xout     : out std_logic;
371 
      qout     : out std_logic;
372 
      a_msb    : in  std_logic;
373 
      cin      : in  std_logic;
374 
      cout     : out std_logic;
375 
      start    : in  std_logic;
376 
      reset    : in  std_logic;
377 
      done : out std_logic;
378 
      r    : out std_logic_vector((width-1) downto 0)
379 
    );
380 
  end component standard_stage;
381 
 
382 
  component stepping_logic is
383 
    generic(
384 
      n : integer := 1536; -- max nr of steps required to complete a multiplication
385 
      t : integer := 192 -- total nr of steps in the pipeline
386 
    );
387 
    port(
388 
      core_clk          : in  std_logic;
389 
      start             : in  std_logic;
390 
      reset             : in  std_logic;
391 
      t_sel             : in integer range 0 to t; -- nr of stages in the pipeline piece
392 
      n_sel             : in integer range 0 to n; -- nr of steps required for a complete multiplication
393 
      start_first_stage : out std_logic;
394 
      stepping_done     : out std_logic
395 
    );
396 
  end component stepping_logic;
397 
 
398 
  component systolic_pipeline is
399 
    generic(
400 
      n  : integer := 1536; -- width of the operands (# bits)
401 
      t  : integer := 192;  -- number of stages (divider of n) >= 2
402 
      tl : integer := 64    -- best take t = sqrt(n)
403 
    );
404 
    port(
405 
      core_clk : in  std_logic;
406 
      my       : in  std_logic_vector((n) downto 0);
407 
      y        : in  std_logic_vector((n-1) downto 0);
408 
      m        : in  std_logic_vector((n-1) downto 0);
409 
      xi       : in  std_logic;
410 
      start    : in  std_logic;
411 
      reset    : in  std_logic;
412 
      p_sel    : in  std_logic_vector(1 downto 0); -- select which piece of the multiplier will be used
413 
      ready    : out std_logic;
414 
      next_x   : out std_logic;
415 
      r        : out std_logic_vector((n+1) downto 0)
416 
    );
417 
  end component systolic_pipeline;
418 
 
419 
  component x_shift_reg is
420 
    generic(
421 
      n  : integer := 1536;
422 
      t  : integer := 48;
423 
      tl : integer := 16
424 
    );
425 
    port(
426 
      clk    : in  std_logic;
427 
      reset  : in  std_logic;
428 
      x_in   : in  std_logic_vector((n-1) downto 0);
429 
      load_x : in  std_logic;
430 
      next_x : in  std_logic;
431 
      p_sel  : in  std_logic_vector(1 downto 0);
432 
      x_i    : out std_logic
433 
    );
434 
  end component x_shift_reg;
435 
 
436 
end package mod_sim_exp_pkg;

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