OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_pkg.vhd] - Blame information for rev 41

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 9 JonasDC
----------------------------------------------------------------------  
2
----  mod_sim_exp_pkg                                             ---- 
3
----                                                              ---- 
4
----  This file is part of the                                    ----
5
----    Modular Simultaneous Exponentiation Core project          ---- 
6
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
7
----                                                              ---- 
8
----  Description                                                 ---- 
9
----    Package for the Modular Simultaneous Exponentiation Core  ----
10
----    Project. Contains the component declarations and used     ----
11
----    constants.                                                ----
12
----                                                              ---- 
13
----  Dependencies: none                                          ---- 
14
----                                                              ---- 
15
----  Authors:                                                    ----
16
----      - Geoffrey Ottoy, DraMCo research group                 ----
17
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
18
----                                                              ---- 
19
---------------------------------------------------------------------- 
20
----                                                              ---- 
21
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
22
----                                                              ---- 
23
---- This source file may be used and distributed without         ---- 
24
---- restriction provided that this copyright statement is not    ---- 
25
---- removed from the file and that any derivative work contains  ---- 
26
---- the original copyright notice and the associated disclaimer. ---- 
27
----                                                              ---- 
28
---- This source file is free software; you can redistribute it   ---- 
29
---- and/or modify it under the terms of the GNU Lesser General   ---- 
30
---- Public License as published by the Free Software Foundation; ---- 
31
---- either version 2.1 of the License, or (at your option) any   ---- 
32
---- later version.                                               ---- 
33
----                                                              ---- 
34
---- This source is distributed in the hope that it will be       ---- 
35
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
36
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
37
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
38
---- details.                                                     ---- 
39
----                                                              ---- 
40
---- You should have received a copy of the GNU Lesser General    ---- 
41
---- Public License along with this source; if not, download it   ---- 
42
---- from http://www.opencores.org/lgpl.shtml                     ---- 
43
----                                                              ---- 
44
----------------------------------------------------------------------
45 3 JonasDC
 
46
library ieee;
47
use ieee.std_logic_1164.all;
48
use ieee.std_logic_unsigned.all;
49
 
50 9 JonasDC
 
51 3 JonasDC
package mod_sim_exp_pkg is
52 37 JonasDC
  --------------------------------------------------------------------
53
  ------------------------- CORE PARAMETERS --------------------------
54
  --------------------------------------------------------------------
55
  -- These 4 parameters affect core workings
56
  constant nr_bits_total    : integer := 1536;
57
  constant nr_stages_total  : integer := 96;
58
  constant nr_stages_low    : integer := 32;
59
  constant split_pipeline   : boolean := true;
60 3 JonasDC
 
61 37 JonasDC
  -- extra calculated parameters
62
  constant nr_bits_low      : integer := (nr_bits_total/nr_stages_total)*nr_stages_low;
63
  constant nr_bits_high     : integer := nr_bits_total-nr_bits_low;
64
  constant nr_stages_high   : integer := nr_stages_total-nr_stages_low;
65
 
66
 
67 16 JonasDC
  --------------------------------------------------------------------
68 37 JonasDC
  ---------------------- COMPONENT DECLARATIONS ----------------------
69
  --------------------------------------------------------------------
70
 
71
  --------------------------------------------------------------------
72 16 JonasDC
  -- d_flip_flop
73
  --------------------------------------------------------------------
74
  --    1-bit D flip-flop with asynchronous active high reset
75
  -- 
76 9 JonasDC
  component d_flip_flop is
77
    port(
78
      core_clk : in  std_logic; -- clock signal
79
      reset    : in  std_logic; -- active high reset
80
      din      : in  std_logic; -- data in
81
      dout     : out std_logic  -- data out
82 3 JonasDC
    );
83 9 JonasDC
  end component d_flip_flop;
84
 
85 16 JonasDC
  --------------------------------------------------------------------
86
  -- register_1b
87
  --------------------------------------------------------------------
88
  --    1-bit register with asynchronous reset and clock enable
89
  -- 
90 9 JonasDC
  component register_1b is
91
    port(
92
      core_clk : in  std_logic; -- clock input
93
      ce       : in  std_logic; -- clock enable (active high)
94
      reset    : in  std_logic; -- reset (active high)
95
      din      : in  std_logic; -- data in
96
      dout     : out std_logic  -- data out
97 3 JonasDC
    );
98 9 JonasDC
  end component register_1b;
99 3 JonasDC
 
100 16 JonasDC
  --------------------------------------------------------------------
101
  -- register_n
102
  --------------------------------------------------------------------
103
  --    n-bit register with asynchronous reset and clock enable
104
  -- 
105 9 JonasDC
  component register_n is
106
    generic(
107 16 JonasDC
      width : integer := 4
108 3 JonasDC
    );
109 9 JonasDC
    port(
110
      core_clk : in  std_logic; -- clock input
111
      ce       : in  std_logic; -- clock enable (active high)
112
      reset    : in  std_logic; -- reset (active high)
113 16 JonasDC
      din      : in  std_logic_vector((width-1) downto 0);  -- data in (width)-bit
114
      dout     : out std_logic_vector((width-1) downto 0)   -- data out (width)-bit
115 3 JonasDC
    );
116 9 JonasDC
  end component register_n;
117 3 JonasDC
 
118 16 JonasDC
  --------------------------------------------------------------------
119
  -- cell_1b_adder
120
  --------------------------------------------------------------------
121
  --    1-bit full adder cell using combinatorial logic
122
  --    
123 3 JonasDC
  component cell_1b_adder is
124
    port (
125 9 JonasDC
      -- input operands a, b
126
      a    : in  std_logic;
127
      b    : in  std_logic;
128
      -- carry in, out
129
      cin  : in  std_logic;
130
      cout : out  std_logic;
131
      -- result out
132
      r    : out  std_logic
133 3 JonasDC
    );
134
  end component cell_1b_adder;
135
 
136 16 JonasDC
  --------------------------------------------------------------------
137
  -- cell_1b_mux
138
  --------------------------------------------------------------------
139
  --    1-bit mux for a standard cell in the montgommery multiplier 
140
  --    systolic array
141
  -- 
142 3 JonasDC
  component cell_1b_mux is
143
    port (
144 9 JonasDC
      -- input bits
145
      my     : in  std_logic;
146 3 JonasDC
      y      : in  std_logic;
147
      m      : in  std_logic;
148 9 JonasDC
      -- selection bits
149 3 JonasDC
      x      : in  std_logic;
150
      q      : in  std_logic;
151 9 JonasDC
      -- mux out
152 3 JonasDC
      result : out std_logic
153
    );
154
  end component cell_1b_mux;
155
 
156 16 JonasDC
  --------------------------------------------------------------------
157
  -- cell_1b
158
  --------------------------------------------------------------------
159
  --    1-bit cell for the systolic array
160
  -- 
161 3 JonasDC
  component cell_1b is
162
    port (
163 9 JonasDC
      -- operand input bits (m+y, y and m)
164 3 JonasDC
      my   : in  std_logic;
165
      y    : in  std_logic;
166
      m    : in  std_logic;
167 16 JonasDC
      -- operand x input bit and q
168 3 JonasDC
      x    : in  std_logic;
169
      q    : in  std_logic;
170 9 JonasDC
      -- previous result input bit
171 3 JonasDC
      a    : in  std_logic;
172 9 JonasDC
      -- carry's
173 3 JonasDC
      cin  : in  std_logic;
174
      cout : out std_logic;
175 9 JonasDC
      -- cell result out
176 3 JonasDC
      r    : out std_logic
177
    );
178
  end component cell_1b;
179
 
180 16 JonasDC
  --------------------------------------------------------------------
181
  -- adder_block
182
  --------------------------------------------------------------------
183
  --    (width)-bit full adder block using cell_1b_adders with buffered
184
  --    carry out
185
  -- 
186 9 JonasDC
  component adder_block is
187
    generic (
188
      width : integer := 32 --adder operand widths
189
    );
190
    port (
191
      -- clock input
192
      core_clk : in std_logic;
193
      -- adder input operands a, b (width)-bit
194
      a : in std_logic_vector((width-1) downto 0);
195
      b : in std_logic_vector((width-1) downto 0);
196
      -- carry in, out
197
      cin   : in std_logic;
198
      cout  : out std_logic;
199
      -- adder result out (width)-bit
200
      r : out std_logic_vector((width-1) downto 0)
201
    );
202
  end component adder_block;
203
 
204 16 JonasDC
  --------------------------------------------------------------------
205 17 JonasDC
  -- standard_cell_block
206
  --------------------------------------------------------------------
207
  --    a standard cell block of (width)-bit for the montgommery multiplier 
208
  --    systolic array
209
  -- 
210
  component standard_cell_block is
211
    generic (
212
      width : integer := 16
213
    );
214
    port (
215
      -- modulus and y operand input (width)-bit
216
      my   : in  std_logic_vector((width-1) downto 0);
217
      y    : in  std_logic_vector((width-1) downto 0);
218
      m    : in  std_logic_vector((width-1) downto 0);
219
      -- q and x operand input (serial input)
220
      x    : in  std_logic;
221
      q    : in  std_logic;
222
      -- previous result in (width)-bit
223
      a    : in  std_logic_vector((width-1) downto 0);
224
      -- carry in and out
225
      cin  : in std_logic;
226
      cout : out std_logic;
227
      -- result out (width)-bit
228
      r    : out  std_logic_vector((width-1) downto 0)
229
    );
230
  end component standard_cell_block;
231
 
232
  --------------------------------------------------------------------
233 19 JonasDC
  -- counter_sync
234
  --------------------------------------------------------------------
235
  --    counter with synchronous count enable. It generates an
236
  --    overflow when max_value is reached
237
  -- 
238
  component counter_sync is
239
    generic(
240
      max_value : integer := 1024 -- maximum value (constraints the nr bits for counter)
241
    );
242
    port(
243
      reset_value : in integer;   -- value the counter counts to
244
      core_clk    : in std_logic; -- clock input
245
      ce          : in std_logic; -- count enable
246
      reset       : in std_logic; -- reset input
247
      overflow    : out std_logic -- gets high when counter reaches reset_value
248
    );
249
  end component counter_sync;
250 18 JonasDC
 
251 19 JonasDC
  --------------------------------------------------------------------
252
  -- stepping_logic
253
  --------------------------------------------------------------------
254
  --    stepping logic for the pipeline, generates the start pulses for the
255
  --    first stage and keeps track of when the last stages are done
256
  -- 
257
  component stepping_logic is
258
    generic(
259
      n : integer := 1536;  -- max nr of steps required to complete a multiplication
260
      t : integer := 192    -- total nr of steps in the pipeline
261
    );
262
    port(
263
      core_clk          : in  std_logic;  -- clock input
264
      start             : in  std_logic;  -- start signal for pipeline (one multiplication)
265
      reset             : in  std_logic;  -- reset signal
266
      t_sel             : in integer range 0 to t; -- nr of stages in the pipeline piece
267
      n_sel             : in integer range 0 to n; -- nr of steps(bits in operands) required for a complete multiplication
268
      start_first_stage : out std_logic;  -- start pulse output for first stage
269
      stepping_done     : out std_logic   -- done signal
270
    );
271
  end component stepping_logic;
272
 
273 20 JonasDC
  --------------------------------------------------------------------
274
  -- x_shift_reg
275
  --------------------------------------------------------------------
276
  --    shift register for the x operand of the multiplier
277
  --    outputs the lsb of the register or bit at offset according to the
278
  --    selected pipeline part 
279
  -- 
280
  component x_shift_reg is
281
    generic(
282
      n  : integer := 1536; -- width of the operands (# bits)
283
      t  : integer := 48;   -- total number of stages
284
      tl : integer := 16    -- lower number of stages
285
    );
286
    port(
287
      -- clock input
288
      clk    : in  std_logic;
289
      -- x operand in (n-bit)
290
      x_in   : in  std_logic_vector((n-1) downto 0);
291
      -- control signals
292
      reset  : in  std_logic; -- reset, clears register
293
      load_x : in  std_logic; -- load operand into shift register   
294
      next_x : in  std_logic; -- next bit of x
295
      p_sel  : in  std_logic_vector(1 downto 0);  -- pipeline selection
296
      -- x operand bit out (serial)
297 21 JonasDC
      xi     : out std_logic
298 20 JonasDC
    );
299
  end component x_shift_reg;
300 23 JonasDC
 
301 24 JonasDC
  --------------------------------------------------------------------
302
  -- mod_sim_exp_core
303
  --------------------------------------------------------------------
304
  --    toplevel of the modular simultaneous exponentiation core
305
  --    contains an operand and modulus ram, multiplier, an exponent fifo
306
  --    and control logic
307
  -- 
308
  component mod_sim_exp_core is
309
    port(
310
      clk   : in  std_logic;
311
      reset : in  std_logic;
312
        -- operand memory interface (plb shared memory)
313
      write_enable : in  std_logic; -- write data to operand ram
314
      data_in      : in  std_logic_vector (31 downto 0);  -- operand ram data in
315
      rw_address   : in  std_logic_vector (8 downto 0);   -- operand ram address bus
316
      data_out     : out std_logic_vector (31 downto 0);  -- operand ram data out
317
      collision    : out std_logic; -- write collision
318
        -- op_sel fifo interface
319
      fifo_din    : in  std_logic_vector (31 downto 0); -- exponent fifo data in
320
      fifo_push   : in  std_logic;  -- push data in exponent fifo
321
      fifo_full   : out std_logic;  -- high if fifo is full
322
      fifo_nopush : out std_logic;  -- high if error during push
323
        -- control signals
324
      start          : in  std_logic; -- start multiplication/exponentiation
325
      run_auto       : in  std_logic; -- single multiplication if low, exponentiation if high
326
      ready          : out std_logic; -- calculations done
327
      x_sel_single   : in  std_logic_vector (1 downto 0); -- single multiplication x operand selection
328
      y_sel_single   : in  std_logic_vector (1 downto 0); -- single multiplication y operand selection
329
      dest_op_single : in  std_logic_vector (1 downto 0); -- result destination operand selection
330
      p_sel          : in  std_logic_vector (1 downto 0); -- pipeline part selection
331
      calc_time      : out std_logic
332
    );
333
  end component mod_sim_exp_core;
334
 
335 9 JonasDC
  component autorun_cntrl is
336
    port (
337
      clk              : in  std_logic;
338
      reset            : in  std_logic;
339
      start            : in  std_logic;
340
      done             : out  std_logic;
341
      op_sel           : out  std_logic_vector (1 downto 0);
342
      start_multiplier : out  std_logic;
343
      multiplier_done  : in  std_logic;
344
      read_buffer      : out  std_logic;
345
      buffer_din       : in  std_logic_vector (31 downto 0);
346
      buffer_empty     : in  std_logic
347
    );
348
  end component autorun_cntrl;
349
 
350 3 JonasDC
  component fifo_primitive is
351
    port (
352
      clk    : in  std_logic;
353
      din    : in  std_logic_vector (31 downto 0);
354
      dout   : out  std_logic_vector (31 downto 0);
355
      empty  : out  std_logic;
356
      full   : out  std_logic;
357
      push   : in  std_logic;
358
      pop    : in  std_logic;
359
      reset  : in std_logic;
360
      nopop  : out std_logic;
361
      nopush : out std_logic
362
    );
363
  end component fifo_primitive;
364
 
365
  component modulus_ram is
366
    port(
367
      clk           : in std_logic;
368
      modulus_addr  : in std_logic_vector(5 downto 0);
369
      write_modulus : in std_logic;
370
      modulus_in    : in std_logic_vector(31 downto 0);
371
      modulus_out   : out std_logic_vector(1535 downto 0)
372
    );
373
  end component modulus_ram;
374
 
375 39 JonasDC
  --------------------------------------------------------------------
376
  -- mont_ctrl
377
  --------------------------------------------------------------------
378
  --    This module controls the montgommery mutliplier and controls traffic between
379
  --    RAM and multiplier. Also contains the autorun logic for exponentiations.
380
  -- 
381 3 JonasDC
  component mont_ctrl is
382
    port (
383
      clk   : in std_logic;
384
      reset : in std_logic;
385
        -- bus side
386
      start           : in std_logic;
387
      x_sel_single    : in std_logic_vector(1 downto 0);
388
      y_sel_single    : in std_logic_vector(1 downto 0);
389
      run_auto        : in std_logic;
390
      op_buffer_empty : in std_logic;
391
      op_sel_buffer   : in std_logic_vector(31 downto 0);
392
      read_buffer     : out std_logic;
393
      done            : out std_logic;
394
      calc_time       : out std_logic;
395
        -- multiplier side
396
      op_sel           : out std_logic_vector(1 downto 0);
397
      load_x           : out std_logic;
398
      load_result      : out std_logic;
399
      start_multiplier : out std_logic;
400
      multiplier_ready : in std_logic
401
    );
402
  end component mont_ctrl;
403
 
404
  component operand_dp is
405
    port (
406
      clka  : in std_logic;
407
      wea   : in std_logic_vector(0 downto 0);
408
      addra : in std_logic_vector(5 downto 0);
409
      dina  : in std_logic_vector(31 downto 0);
410
      douta : out std_logic_vector(511 downto 0);
411
      clkb  : in std_logic;
412
      web   : in std_logic_vector(0 downto 0);
413
      addrb : in std_logic_vector(5 downto 0);
414
      dinb  : in std_logic_vector(511 downto 0);
415
      doutb : out std_logic_vector(31 downto 0)
416
    );
417
  end component operand_dp;
418
 
419
  component operand_mem is
420 39 JonasDC
    generic(
421
      n : integer := 1536
422 3 JonasDC
    );
423
    port(
424
        -- data interface (plb side)
425
      data_in    : in  std_logic_vector(31 downto 0);
426
      data_out   : out  std_logic_vector(31 downto 0);
427
      rw_address : in  std_logic_vector(8 downto 0);
428 39 JonasDC
      write_enable : in  std_logic;
429 3 JonasDC
        -- address structure:
430
        -- bit:  8   -> '1': modulus
431
        --              '0': operands
432
        -- bits: 7-6 -> operand_in_sel in case of bit 8 = '0'
433
        --              don't care in case of modulus
434
        -- bits: 5-0 -> modulus_addr / operand_addr resp.
435
 
436
        -- operand interface (multiplier side)
437
      op_sel    : in  std_logic_vector(1 downto 0);
438 34 JonasDC
      xy_out    : out  std_logic_vector((n-1) downto 0);
439
      m         : out  std_logic_vector((n-1) downto 0);
440
      result_in : in std_logic_vector((n-1) downto 0);
441 39 JonasDC
      -- control signals
442 3 JonasDC
      load_result    : in std_logic;
443
      result_dest_op : in std_logic_vector(1 downto 0);
444
      collision      : out std_logic;
445
        -- system clock
446
      clk : in  std_logic
447
    );
448
  end component operand_mem;
449
 
450
  component operand_ram is
451
    port( -- write_operand_ack voorzien?
452
      -- global ports
453
      clk       : in std_logic;
454
      collision : out std_logic;
455
      -- bus side connections (32-bit serial)
456
      operand_addr   : in std_logic_vector(5 downto 0);
457
      operand_in     : in std_logic_vector(31 downto 0);
458
      operand_in_sel : in std_logic_vector(1 downto 0);
459
      result_out     : out std_logic_vector(31 downto 0);
460
      write_operand  : in std_logic;
461
      -- multiplier side connections (1536 bit parallel)
462
      result_dest_op  : in std_logic_vector(1 downto 0);
463
      operand_out     : out std_logic_vector(1535 downto 0);
464
      operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side
465
      write_result    : in std_logic;
466
      result_in       : in std_logic_vector(1535 downto 0)
467
    );
468
  end component operand_ram;
469
 
470
  component operands_sp is
471
    port (
472
      clka  : in std_logic;
473
      wea   : in std_logic_vector(0 downto 0);
474
      addra : in std_logic_vector(4 downto 0);
475
      dina  : in std_logic_vector(31 downto 0);
476
      douta : out std_logic_vector(511 downto 0)
477
    );
478
  end component operands_sp;
479
 
480 25 JonasDC
 
481
  component sys_stage is
482
    generic(
483
      width : integer := 32 -- width of the stage
484
    );
485
    port(
486
      -- clock input
487
      core_clk : in  std_logic;
488
      -- modulus and y operand input (width)-bit
489
      y        : in  std_logic_vector((width-1) downto 0);
490
      m        : in  std_logic_vector((width) downto 0);
491
      my_cin   : in  std_logic;
492
      my_cout  : out std_logic;
493
      -- q and x operand input (serial input)
494
      xin      : in  std_logic;
495
      qin      : in  std_logic;
496
      -- q and x operand output (serial output)
497
      xout     : out std_logic;
498
      qout     : out std_logic;
499
      -- msb input (lsb from next stage, for shift right operation)
500
      a_msb    : in  std_logic;
501
      a_0      : out std_logic;
502
      -- carry out(clocked) and in
503
      cin      : in  std_logic;
504
      cout     : out std_logic;
505
      -- reduction adder carry's
506
      red_cin  : in std_logic;
507
      red_cout : out std_logic;
508
      -- control singals
509
      start    : in  std_logic;
510
      reset    : in  std_logic;
511
      done     : out std_logic;
512
      -- result out
513
      r_sel    : in  std_logic; -- result selection: 0 -> pipeline result, 1 -> reducted result
514
      r        : out std_logic_vector((width-1) downto 0)
515
    );
516
  end component sys_stage;
517 30 JonasDC
 
518
  --------------------------------------------------------------------
519
  -- sys_last_cell_logic
520
  --------------------------------------------------------------------   
521
  --    logic needed as the last piece in the systolic array pipeline
522
  --    calculates the last 2 bits of the cell_result and finishes the reduction
523
  --    also generates the result selection signal
524
  -- 
525
  component sys_last_cell_logic is
526
    port  (
527
      core_clk : in std_logic;    -- clock input
528
      reset    : in std_logic;
529
      a_0      : out std_logic;   -- a_msb for last stage
530
      cin      : in std_logic;    -- cout from last stage
531
      red_cin  : in std_logic;    -- red_cout from last stage
532
      r_sel    : out std_logic;   -- result selection bit
533
      start    : in std_logic     -- done signal from last stage
534
    );
535
  end component sys_last_cell_logic;
536 25 JonasDC
 
537
  --------------------------------------------------------------------
538 31 JonasDC
  -- sys_first_cell_logic
539
  --------------------------------------------------------------------     
540
  --    logic needed as the first piece in the systolic array pipeline
541
  --    calculates the first my_cout and generates q signal
542
  -- 
543
  component sys_first_cell_logic is
544
    port  (
545
      m0       : in std_logic;    -- lsb from m operand
546
      y0       : in std_logic;    -- lsb from y operand
547
      my_cout  : out std_logic;   -- my_cin for first stage
548
      xi       : in std_logic;    -- xi operand input
549
      xout     : out std_logic;   -- xin for first stage
550
      qout     : out std_logic;   -- qin for first stage
551
      cout     : out std_logic;   -- cin for first stage
552
      a_0      : in std_logic;    -- a_0 from first stage
553
      red_cout : out std_logic    -- red_cin for first stage
554
    );
555
  end component sys_first_cell_logic;
556
 
557
  --------------------------------------------------------------------
558 25 JonasDC
  -- sys_pipeline
559
  -------------------------------------------------------------------- 
560
  --    the pipelined systolic array for a montgommery multiplier
561
  --    contains a structural description of the pipeline using the systolic stages
562
  -- 
563
  component sys_pipeline is
564
    generic(
565
      n  : integer := 1536; -- width of the operands (# bits)
566 37 JonasDC
      t  : integer := 192;  -- total number of stages (minimum 2)
567
      tl : integer := 64;   -- lower number of stages (minimum 1)
568
      split : boolean := true -- if true the pipeline wil be split in 2 parts,
569
                              -- if false there are no lower stages, only t counts
570 25 JonasDC
    );
571
    port(
572
      -- clock input
573
      core_clk : in  std_logic;
574
      -- modulus and y opperand input (n)-bit
575
      y        : in  std_logic_vector((n-1) downto 0);
576
      m        : in  std_logic_vector((n-1) downto 0);
577
      -- x operand input (serial)
578
      xi       : in  std_logic;
579
      next_x   : out std_logic; -- next x operand bit
580
      -- control signals
581
      start    : in  std_logic; -- start multiplier
582
      reset    : in  std_logic;
583
      p_sel    : in  std_logic_vector(1 downto 0); -- select which piece of the pipeline will be used
584
      -- result out
585
      r        : out std_logic_vector((n-1) downto 0)
586
    );
587
  end component sys_pipeline;
588
 
589
  component mont_multiplier is
590
  generic (
591 37 JonasDC
    n     : integer := 1536;  -- width of the operands
592
    t     : integer := 96;    -- total number of stages (minimum 2)
593
    tl    : integer := 32;    -- lower number of stages (minimum 1)
594
    split : boolean := true   -- if true the pipeline wil be split in 2 parts,
595
                              -- if false there are no lower stages, only t counts
596 25 JonasDC
  );
597
  port (
598
    -- clock input
599
    core_clk : in std_logic;
600
    -- operand inputs
601
    xy       : in std_logic_vector((n-1) downto 0); -- bus for x or y operand
602
    m        : in std_logic_vector((n-1) downto 0); -- modulus
603
    -- result output
604
    r        : out std_logic_vector((n-1) downto 0);  -- result
605
    -- control signals
606
    start    : in std_logic;
607
    reset    : in std_logic;
608
    p_sel    : in std_logic_vector(1 downto 0);
609
    load_x   : in std_logic;
610
    ready    : out std_logic
611
  );
612
  end component mont_multiplier;
613
 
614 3 JonasDC
end package mod_sim_exp_pkg;

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.