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----------------------------------------------------------------------  
----  mod_sim_exp_pkg                                             ---- 
----                                                              ---- 
----  This file is part of the                                    ----
----    Modular Simultaneous Exponentiation Core project          ---- 
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
----                                                              ---- 
----  Description                                                 ---- 
----    Package for the Modular Simultaneous Exponentiation Core  ----
----    Project. Contains the component declarations and used     ----
----    constants.                                                ----
----                                                              ---- 
----  Dependencies: none                                          ---- 
----                                                              ---- 
----  Authors:                                                    ----
----      - Geoffrey Ottoy, DraMCo research group                 ----
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
----                                                              ---- 
---------------------------------------------------------------------- 
----                                                              ---- 
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
----                                                              ---- 
---- This source file may be used and distributed without         ---- 
---- restriction provided that this copyright statement is not    ---- 
---- removed from the file and that any derivative work contains  ---- 
---- the original copyright notice and the associated disclaimer. ---- 
----                                                              ---- 
---- This source file is free software; you can redistribute it   ---- 
---- and/or modify it under the terms of the GNU Lesser General   ---- 
---- Public License as published by the Free Software Foundation; ---- 
---- either version 2.1 of the License, or (at your option) any   ---- 
---- later version.                                               ---- 
----                                                              ---- 
---- This source is distributed in the hope that it will be       ---- 
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
---- details.                                                     ---- 
----                                                              ---- 
---- You should have received a copy of the GNU Lesser General    ---- 
---- Public License along with this source; if not, download it   ---- 
---- from http://www.opencores.org/lgpl.shtml                     ---- 
----                                                              ---- 
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
 
package mod_sim_exp_pkg is
 
  -- 1-bit D flip-flop with asynchronous active high reset
  component d_flip_flop is
    port(
      core_clk : in  std_logic; -- clock signal
      reset    : in  std_logic; -- active high reset
      din      : in  std_logic; -- data in
      dout     : out std_logic  -- data out
    );
  end component d_flip_flop;
 
  -- 1-bit register with asynchronous reset and clock enable
  component register_1b is
    port(
      core_clk : in  std_logic; -- clock input
      ce       : in  std_logic; -- clock enable (active high)
      reset    : in  std_logic; -- reset (active high)
      din      : in  std_logic; -- data in
      dout     : out std_logic  -- data out
    );
  end component register_1b;
 
  -- n-bit register with asynchronous reset and clock enable
  component register_n is
    generic(
      n : integer := 4
    );
    port(
      core_clk : in  std_logic; -- clock input
      ce       : in  std_logic; -- clock enable (active high)
      reset    : in  std_logic; -- reset (active high)
      din      : in  std_logic_vector((n-1) downto 0);  -- data in (n-bit)
      dout     : out std_logic_vector((n-1) downto 0)   -- data out (n-bit)
    );
  end component register_n;
 
  -- 1-bit full adder cell
  component cell_1b_adder is
    port (
      -- input operands a, b
      a    : in  std_logic;
      b    : in  std_logic;
      -- carry in, out
      cin  : in  std_logic;
      cout : out  std_logic;
      -- result out
      r    : out  std_logic
    );
  end component cell_1b_adder;
 
  -- 1-bit mux for a standard cell in the montgommery multiplier systolic array
  component cell_1b_mux is
    port (
      -- input bits
      my     : in  std_logic;
      y      : in  std_logic;
      m      : in  std_logic;
      -- selection bits
      x      : in  std_logic;
      q      : in  std_logic;
      -- mux out
      result : out std_logic
    );
  end component cell_1b_mux;
 
  -- 1-bit cell for the systolic array
  component cell_1b is
    port (
      -- operand input bits (m+y, y and m)
      my   : in  std_logic;
      y    : in  std_logic;
      m    : in  std_logic;
      -- operand x input bit and q (serial)
      x    : in  std_logic;
      q    : in  std_logic;
      -- previous result input bit
      a    : in  std_logic;
      -- carry's
      cin  : in  std_logic;
      cout : out std_logic;
      -- cell result out
      r    : out std_logic
    );
  end component cell_1b;
 
  -- (width)-bit full adder block using cell_1b_adders
  -- with buffered carry out
  component adder_block is
    generic (
      width : integer := 32 --adder operand widths
    );
    port (
      -- clock input
      core_clk : in std_logic;
      -- adder input operands a, b (width)-bit
      a : in std_logic_vector((width-1) downto 0);
      b : in std_logic_vector((width-1) downto 0);
      -- carry in, out
      cin   : in std_logic;
      cout  : out std_logic;
      -- adder result out (width)-bit
      r : out std_logic_vector((width-1) downto 0)
    );
  end component adder_block;
 
  -- n-bit adder using adder blocks. works in stages, to prevent large 
  -- carry propagation
  component adder_n is
    generic (
      width       : integer := 1536; -- adder operands width
      block_width : integer := 8     -- adder blocks size
    );
    port (
      -- clock input
      core_clk : in std_logic;
      -- adder input operands (width)-bit
      a : in std_logic_vector((width-1) downto 0);
      b : in std_logic_vector((width-1) downto 0);
      -- carry in, out
      cin   : in std_logic;
      cout  : out std_logic;
      -- adder output result (width)-bit
      r : out std_logic_vector((width-1) downto 0)
    );
  end component adder_n;
 
  component autorun_cntrl is
    port (
      clk              : in  std_logic;
      reset            : in  std_logic;
      start            : in  std_logic;
      done             : out  std_logic;
      op_sel           : out  std_logic_vector (1 downto 0);
      start_multiplier : out  std_logic;
      multiplier_done  : in  std_logic;
      read_buffer      : out  std_logic;
      buffer_din       : in  std_logic_vector (31 downto 0);
      buffer_empty     : in  std_logic
    );
  end component autorun_cntrl;
 
  component counter_sync is
    generic(
      max_value : integer := 1024
    );
    port(
      reset_value : in integer;
      core_clk    : in std_logic;
      ce          : in std_logic;
      reset       : in std_logic;
      overflow    : out std_logic
    );
  end component counter_sync;
 
  component fifo_primitive is
    port (
      clk    : in  std_logic;
      din    : in  std_logic_vector (31 downto 0);
      dout   : out  std_logic_vector (31 downto 0);
      empty  : out  std_logic;
      full   : out  std_logic;
      push   : in  std_logic;
      pop    : in  std_logic;
      reset  : in std_logic;
      nopop  : out std_logic;
      nopush : out std_logic
    );
  end component fifo_primitive;
 
  component first_stage is
    generic(
      width : integer := 16 -- must be the same as width of the standard stage
    );
    port(
      core_clk : in  std_logic;
      my       : in  std_logic_vector((width) downto 0);
      y        : in  std_logic_vector((width) downto 0);
      m        : in  std_logic_vector((width) downto 0);
      xin      : in  std_logic;
      xout     : out std_logic;
      qout     : out std_logic;
      a_msb    : in  std_logic;
      cout     : out std_logic;
      start    : in  std_logic;
      reset    : in  std_logic;
      done     : out std_logic;
      r        : out std_logic_vector((width-1) downto 0)
    );
  end component first_stage;
 
  component last_stage is
    generic(
      width : integer := 16 -- must be the same as width of the standard stage
    );
    port(
      core_clk : in  std_logic;
      my       : in  std_logic_vector((width-1) downto 0);
      y        : in  std_logic_vector((width-2) downto 0);
      m        : in  std_logic_vector((width-2) downto 0);
      xin      : in  std_logic;
      qin      : in  std_logic;
      cin      : in  std_logic;
      start    : in  std_logic;
      reset    : in  std_logic;
      r        : out std_logic_vector((width+1) downto 0)
    );
  end component last_stage;
 
  component modulus_ram is
    port(
      clk           : in std_logic;
      modulus_addr  : in std_logic_vector(5 downto 0);
      write_modulus : in std_logic;
      modulus_in    : in std_logic_vector(31 downto 0);
      modulus_out   : out std_logic_vector(1535 downto 0)
    );
  end component modulus_ram;
 
  component mont_ctrl is
    port (
      clk   : in std_logic;
      reset : in std_logic;
        -- bus side
      start           : in std_logic;
      x_sel_single    : in std_logic_vector(1 downto 0);
      y_sel_single    : in std_logic_vector(1 downto 0);
      run_auto        : in std_logic;
      op_buffer_empty : in std_logic;
      op_sel_buffer   : in std_logic_vector(31 downto 0);
      read_buffer     : out std_logic;
      buffer_noread   : in std_logic;
      done            : out std_logic;
      calc_time       : out std_logic;
        -- multiplier side
      op_sel           : out std_logic_vector(1 downto 0);
      load_x           : out std_logic;
      load_result      : out std_logic;
      start_multiplier : out std_logic;
      multiplier_ready : in std_logic
    );
  end component mont_ctrl;
 
  component mont_mult_sys_pipeline is
    generic (
      n          : integer := 1536;
      nr_stages  : integer := 96; --(divides n, bits_low & (n-bits_low))
      stages_low : integer := 32
    );
    port (
      core_clk : in std_logic;
      xy       : in std_logic_vector((n-1) downto 0);
      m        : in std_logic_vector((n-1) downto 0);
      r        : out std_logic_vector((n-1) downto 0);
      start    : in std_logic;
      reset    : in std_logic;
      p_sel    : in std_logic_vector(1 downto 0);
      load_x   : in std_logic;
      ready    : out std_logic
    );
  end component mont_mult_sys_pipeline;
 
  component multiplier_core is
    port(
      clk   : in  std_logic;
      reset : in  std_logic;
        -- operand memory interface (plb shared memory)
      write_enable : in  std_logic;
      data_in      : in  std_logic_vector (31 downto 0);
      rw_address   : in  std_logic_vector (8 downto 0);
      data_out     : out std_logic_vector (31 downto 0);
      collision    : out std_logic;
        -- op_sel fifo interface
      fifo_din    : in  std_logic_vector (31 downto 0);
      fifo_push   : in  std_logic;
      fifo_full   : out std_logic;
      fifo_nopush : out std_logic;
        -- ctrl signals
      start          : in  std_logic;
      run_auto       : in  std_logic;
      ready          : out std_logic;
      x_sel_single   : in  std_logic_vector (1 downto 0);
      y_sel_single   : in  std_logic_vector (1 downto 0);
      dest_op_single : in  std_logic_vector (1 downto 0);
      p_sel          : in  std_logic_vector (1 downto 0);
      calc_time      : out std_logic
    );
  end component multiplier_core;
 
  component operand_dp is
    port (
      clka  : in std_logic;
      wea   : in std_logic_vector(0 downto 0);
      addra : in std_logic_vector(5 downto 0);
      dina  : in std_logic_vector(31 downto 0);
      douta : out std_logic_vector(511 downto 0);
      clkb  : in std_logic;
      web   : in std_logic_vector(0 downto 0);
      addrb : in std_logic_vector(5 downto 0);
      dinb  : in std_logic_vector(511 downto 0);
      doutb : out std_logic_vector(31 downto 0)
    );
  end component operand_dp;
 
  component operand_mem is
    generic(n : integer := 1536
    );
    port(
        -- data interface (plb side)
      data_in    : in  std_logic_vector(31 downto 0);
      data_out   : out  std_logic_vector(31 downto 0);
      rw_address : in  std_logic_vector(8 downto 0);
        -- address structure:
        -- bit:  8   -> '1': modulus
        --              '0': operands
        -- bits: 7-6 -> operand_in_sel in case of bit 8 = '0'
        --              don't care in case of modulus
        -- bits: 5-0 -> modulus_addr / operand_addr resp.
 
        -- operand interface (multiplier side)
      op_sel    : in  std_logic_vector(1 downto 0);
      xy_out    : out  std_logic_vector(1535 downto 0);
      m         : out  std_logic_vector(1535 downto 0);
      result_in : in std_logic_vector(1535 downto 0);
        -- control signals
      load_op        : in std_logic;
      load_m         : in std_logic;
      load_result    : in std_logic;
      result_dest_op : in std_logic_vector(1 downto 0);
      collision      : out std_logic;
        -- system clock
      clk : in  std_logic
    );
  end component operand_mem;
 
  component operand_ram is
    port( -- write_operand_ack voorzien?
      -- global ports
      clk       : in std_logic;
      collision : out std_logic;
      -- bus side connections (32-bit serial)
      operand_addr   : in std_logic_vector(5 downto 0);
      operand_in     : in std_logic_vector(31 downto 0);
      operand_in_sel : in std_logic_vector(1 downto 0);
      result_out     : out std_logic_vector(31 downto 0);
      write_operand  : in std_logic;
      -- multiplier side connections (1536 bit parallel)
      result_dest_op  : in std_logic_vector(1 downto 0);
      operand_out     : out std_logic_vector(1535 downto 0);
      operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side
      write_result    : in std_logic;
      result_in       : in std_logic_vector(1535 downto 0)
    );
  end component operand_ram;
 
  component operands_sp is
    port (
      clka  : in std_logic;
      wea   : in std_logic_vector(0 downto 0);
      addra : in std_logic_vector(4 downto 0);
      dina  : in std_logic_vector(31 downto 0);
      douta : out std_logic_vector(511 downto 0)
    );
  end component operands_sp;
 
  component standard_cell_block is
    generic (
      width : integer := 16
    );
    port (
      my   : in  std_logic_vector((width-1) downto 0);
      y    : in  std_logic_vector((width-1) downto 0);
      m    : in  std_logic_vector((width-1) downto 0);
      x    : in  std_logic;
      q    : in  std_logic;
      a    : in  std_logic_vector((width-1) downto 0);
      cin  : in std_logic;
      cout : out std_logic;
      r    : out  std_logic_vector((width-1) downto 0)
    );
  end component standard_cell_block;
 
  component standard_stage is
    generic(
      width : integer := 32
    );
    port(
      core_clk : in  std_logic;
      my       : in  std_logic_vector((width-1) downto 0);
      y        : in  std_logic_vector((width-1) downto 0);
      m        : in  std_logic_vector((width-1) downto 0);
      xin      : in  std_logic;
      qin      : in  std_logic;
      xout     : out std_logic;
      qout     : out std_logic;
      a_msb    : in  std_logic;
      cin      : in  std_logic;
      cout     : out std_logic;
      start    : in  std_logic;
      reset    : in  std_logic;
      done : out std_logic;
      r    : out std_logic_vector((width-1) downto 0)
    );
  end component standard_stage;
 
  component stepping_logic is
    generic(
      n : integer := 1536; -- max nr of steps required to complete a multiplication
      t : integer := 192 -- total nr of steps in the pipeline
    );
    port(
      core_clk          : in  std_logic;
      start             : in  std_logic;
      reset             : in  std_logic;
      t_sel             : in integer range 0 to t; -- nr of stages in the pipeline piece
      n_sel             : in integer range 0 to n; -- nr of steps required for a complete multiplication
      start_first_stage : out std_logic;
      stepping_done     : out std_logic
    );
  end component stepping_logic;
 
  component systolic_pipeline is
    generic(
      n  : integer := 1536; -- width of the operands (# bits)
      t  : integer := 192;  -- number of stages (divider of n) >= 2
      tl : integer := 64    -- best take t = sqrt(n)
    );
    port(
      core_clk : in  std_logic;
      my       : in  std_logic_vector((n) downto 0);
      y        : in  std_logic_vector((n-1) downto 0);
      m        : in  std_logic_vector((n-1) downto 0);
      xi       : in  std_logic;
      start    : in  std_logic;
      reset    : in  std_logic;
      p_sel    : in  std_logic_vector(1 downto 0); -- select which piece of the multiplier will be used
      ready    : out std_logic;
      next_x   : out std_logic;
      r        : out std_logic_vector((n+1) downto 0)
    );
  end component systolic_pipeline;
 
  component x_shift_reg is
    generic(
      n  : integer := 1536;
      t  : integer := 48;
      tl : integer := 16
    );
    port(
      clk    : in  std_logic;
      reset  : in  std_logic;
      x_in   : in  std_logic_vector((n-1) downto 0);
      load_x : in  std_logic;
      next_x : in  std_logic;
      p_sel  : in  std_logic_vector(1 downto 0);
      x_i    : out std_logic
    );
  end component x_shift_reg;
 
end package mod_sim_exp_pkg;

Line No.	Rev	Author	Line
1	9	JonasDC	`----------------------------------------------------------------------`
2			`---- mod_sim_exp_pkg ----`
3			`---- ----`
4			`---- This file is part of the ----`
5			`---- Modular Simultaneous Exponentiation Core project ----`
6			`---- http://www.opencores.org/cores/mod_sim_exp/ ----`
7			`---- ----`
8			`---- Description ----`
9			`---- Package for the Modular Simultaneous Exponentiation Core ----`
10			`---- Project. Contains the component declarations and used ----`
11			`---- constants. ----`
12			`---- ----`
13			`---- Dependencies: none ----`
14			`---- ----`
15			`---- Authors: ----`
16			`---- - Geoffrey Ottoy, DraMCo research group ----`
17			`---- - Jonas De Craene, JonasDC@opencores.org ----`
18			`---- ----`
19			`----------------------------------------------------------------------`
20			`---- ----`
21			`---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----`
22			`---- ----`
23			`---- This source file may be used and distributed without ----`
24			`---- restriction provided that this copyright statement is not ----`
25			`---- removed from the file and that any derivative work contains ----`
26			`---- the original copyright notice and the associated disclaimer. ----`
27			`---- ----`
28			`---- This source file is free software; you can redistribute it ----`
29			`---- and/or modify it under the terms of the GNU Lesser General ----`
30			`---- Public License as published by the Free Software Foundation; ----`
31			`---- either version 2.1 of the License, or (at your option) any ----`
32			`---- later version. ----`
33			`---- ----`
34			`---- This source is distributed in the hope that it will be ----`
35			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
36			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
37			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
38			`---- details. ----`
39			`---- ----`
40			`---- You should have received a copy of the GNU Lesser General ----`
41			`---- Public License along with this source; if not, download it ----`
42			`---- from http://www.opencores.org/lgpl.shtml ----`
43			`---- ----`
44			`----------------------------------------------------------------------`
45	3	JonasDC
46			`library ieee;`
47			`use ieee.std_logic_1164.all;`
48			`use ieee.std_logic_unsigned.all;`
49
50	9	JonasDC
51	3	JonasDC	`package mod_sim_exp_pkg is`
52
53	9	JonasDC	`-- 1-bit D flip-flop with asynchronous active high reset`
54			`component d_flip_flop is`
55			`port(`
56			`core_clk : in std_logic; -- clock signal`
57			`reset : in std_logic; -- active high reset`
58			`din : in std_logic; -- data in`
59			`dout : out std_logic -- data out`
60	3	JonasDC	`);`
61	9	JonasDC	`end component d_flip_flop;`
62
63			`-- 1-bit register with asynchronous reset and clock enable`
64			`component register_1b is`
65			`port(`
66			`core_clk : in std_logic; -- clock input`
67			`ce : in std_logic; -- clock enable (active high)`
68			`reset : in std_logic; -- reset (active high)`
69			`din : in std_logic; -- data in`
70			`dout : out std_logic -- data out`
71	3	JonasDC	`);`
72	9	JonasDC	`end component register_1b;`
73	3	JonasDC
74	9	JonasDC	`-- n-bit register with asynchronous reset and clock enable`
75			`component register_n is`
76			`generic(`
77			`n : integer := 4`
78	3	JonasDC	`);`
79	9	JonasDC	`port(`
80			`core_clk : in std_logic; -- clock input`
81			`ce : in std_logic; -- clock enable (active high)`
82			`reset : in std_logic; -- reset (active high)`
83			`din : in std_logic_vector((n-1) downto 0); -- data in (n-bit)`
84			`dout : out std_logic_vector((n-1) downto 0) -- data out (n-bit)`
85	3	JonasDC	`);`
86	9	JonasDC	`end component register_n;`
87	3	JonasDC
88	9	JonasDC	`-- 1-bit full adder cell`
89	3	JonasDC	`component cell_1b_adder is`
90			`port (`
91	9	JonasDC	`-- input operands a, b`
92			`a : in std_logic;`
93			`b : in std_logic;`
94			`-- carry in, out`
95			`cin : in std_logic;`
96			`cout : out std_logic;`
97			`-- result out`
98			`r : out std_logic`
99	3	JonasDC	`);`
100			`end component cell_1b_adder;`
101
102	9	JonasDC	`-- 1-bit mux for a standard cell in the montgommery multiplier systolic array`
103	3	JonasDC	`component cell_1b_mux is`
104			`port (`
105	9	JonasDC	`-- input bits`
106			`my : in std_logic;`
107	3	JonasDC	`y : in std_logic;`
108			`m : in std_logic;`
109	9	JonasDC	`-- selection bits`
110	3	JonasDC	`x : in std_logic;`
111			`q : in std_logic;`
112	9	JonasDC	`-- mux out`
113	3	JonasDC	`result : out std_logic`
114			`);`
115			`end component cell_1b_mux;`
116
117	9	JonasDC	`-- 1-bit cell for the systolic array`
118	3	JonasDC	`component cell_1b is`
119			`port (`
120	9	JonasDC	`-- operand input bits (m+y, y and m)`
121	3	JonasDC	`my : in std_logic;`
122			`y : in std_logic;`
123			`m : in std_logic;`
124	9	JonasDC	`-- operand x input bit and q (serial)`
125	3	JonasDC	`x : in std_logic;`
126			`q : in std_logic;`
127	9	JonasDC	`-- previous result input bit`
128	3	JonasDC	`a : in std_logic;`
129	9	JonasDC	`-- carry's`
130	3	JonasDC	`cin : in std_logic;`
131			`cout : out std_logic;`
132	9	JonasDC	`-- cell result out`
133	3	JonasDC	`r : out std_logic`
134			`);`
135			`end component cell_1b;`
136
137	9	JonasDC	`-- (width)-bit full adder block using cell_1b_adders`
138			`-- with buffered carry out`
139			`component adder_block is`
140			`generic (`
141			`width : integer := 32 --adder operand widths`
142			`);`
143			`port (`
144			`-- clock input`
145			`core_clk : in std_logic;`
146			`-- adder input operands a, b (width)-bit`
147			`a : in std_logic_vector((width-1) downto 0);`
148			`b : in std_logic_vector((width-1) downto 0);`
149			`-- carry in, out`
150			`cin : in std_logic;`
151			`cout : out std_logic;`
152			`-- adder result out (width)-bit`
153			`r : out std_logic_vector((width-1) downto 0)`
154			`);`
155			`end component adder_block;`
156
157			`-- n-bit adder using adder blocks. works in stages, to prevent large`
158			`-- carry propagation`
159			`component adder_n is`
160			`generic (`
161			`width : integer := 1536; -- adder operands width`
162			`block_width : integer := 8 -- adder blocks size`
163			`);`
164			`port (`
165			`-- clock input`
166			`core_clk : in std_logic;`
167			`-- adder input operands (width)-bit`
168			`a : in std_logic_vector((width-1) downto 0);`
169			`b : in std_logic_vector((width-1) downto 0);`
170			`-- carry in, out`
171			`cin : in std_logic;`
172			`cout : out std_logic;`
173			`-- adder output result (width)-bit`
174			`r : out std_logic_vector((width-1) downto 0)`
175			`);`
176			`end component adder_n;`
177
178			`component autorun_cntrl is`
179			`port (`
180			`clk : in std_logic;`
181			`reset : in std_logic;`
182			`start : in std_logic;`
183			`done : out std_logic;`
184			`op_sel : out std_logic_vector (1 downto 0);`
185			`start_multiplier : out std_logic;`
186			`multiplier_done : in std_logic;`
187			`read_buffer : out std_logic;`
188			`buffer_din : in std_logic_vector (31 downto 0);`
189			`buffer_empty : in std_logic`
190			`);`
191			`end component autorun_cntrl;`
192
193	3	JonasDC	`component counter_sync is`
194			`generic(`
195			`max_value : integer := 1024`
196			`);`
197			`port(`
198			`reset_value : in integer;`
199			`core_clk : in std_logic;`
200			`ce : in std_logic;`
201			`reset : in std_logic;`
202			`overflow : out std_logic`
203			`);`
204			`end component counter_sync;`
205
206			`component fifo_primitive is`
207			`port (`
208			`clk : in std_logic;`
209			`din : in std_logic_vector (31 downto 0);`
210			`dout : out std_logic_vector (31 downto 0);`
211			`empty : out std_logic;`
212			`full : out std_logic;`
213			`push : in std_logic;`
214			`pop : in std_logic;`
215			`reset : in std_logic;`
216			`nopop : out std_logic;`
217			`nopush : out std_logic`
218			`);`
219			`end component fifo_primitive;`
220
221			`component first_stage is`
222			`generic(`
223			`width : integer := 16 -- must be the same as width of the standard stage`
224			`);`
225			`port(`
226			`core_clk : in std_logic;`
227			`my : in std_logic_vector((width) downto 0);`
228			`y : in std_logic_vector((width) downto 0);`
229			`m : in std_logic_vector((width) downto 0);`
230			`xin : in std_logic;`
231			`xout : out std_logic;`
232			`qout : out std_logic;`
233			`a_msb : in std_logic;`
234			`cout : out std_logic;`
235			`start : in std_logic;`
236			`reset : in std_logic;`
237			`done : out std_logic;`
238			`r : out std_logic_vector((width-1) downto 0)`
239			`);`
240			`end component first_stage;`
241
242			`component last_stage is`
243			`generic(`
244			`width : integer := 16 -- must be the same as width of the standard stage`
245			`);`
246			`port(`
247			`core_clk : in std_logic;`
248			`my : in std_logic_vector((width-1) downto 0);`
249			`y : in std_logic_vector((width-2) downto 0);`
250			`m : in std_logic_vector((width-2) downto 0);`
251			`xin : in std_logic;`
252			`qin : in std_logic;`
253			`cin : in std_logic;`
254			`start : in std_logic;`
255			`reset : in std_logic;`
256			`r : out std_logic_vector((width+1) downto 0)`
257			`);`
258			`end component last_stage;`
259
260			`component modulus_ram is`
261			`port(`
262			`clk : in std_logic;`
263			`modulus_addr : in std_logic_vector(5 downto 0);`
264			`write_modulus : in std_logic;`
265			`modulus_in : in std_logic_vector(31 downto 0);`
266			`modulus_out : out std_logic_vector(1535 downto 0)`
267			`);`
268			`end component modulus_ram;`
269
270			`component mont_ctrl is`
271			`port (`
272			`clk : in std_logic;`
273			`reset : in std_logic;`
274			`-- bus side`
275			`start : in std_logic;`
276			`x_sel_single : in std_logic_vector(1 downto 0);`
277			`y_sel_single : in std_logic_vector(1 downto 0);`
278			`run_auto : in std_logic;`
279			`op_buffer_empty : in std_logic;`
280			`op_sel_buffer : in std_logic_vector(31 downto 0);`
281			`read_buffer : out std_logic;`
282			`buffer_noread : in std_logic;`
283			`done : out std_logic;`
284			`calc_time : out std_logic;`
285			`-- multiplier side`
286			`op_sel : out std_logic_vector(1 downto 0);`
287			`load_x : out std_logic;`
288			`load_result : out std_logic;`
289			`start_multiplier : out std_logic;`
290			`multiplier_ready : in std_logic`
291			`);`
292			`end component mont_ctrl;`
293
294			`component mont_mult_sys_pipeline is`
295			`generic (`
296			`n : integer := 1536;`
297			`nr_stages : integer := 96; --(divides n, bits_low & (n-bits_low))`
298			`stages_low : integer := 32`
299			`);`
300			`port (`
301			`core_clk : in std_logic;`
302			`xy : in std_logic_vector((n-1) downto 0);`
303			`m : in std_logic_vector((n-1) downto 0);`
304			`r : out std_logic_vector((n-1) downto 0);`
305			`start : in std_logic;`
306			`reset : in std_logic;`
307			`p_sel : in std_logic_vector(1 downto 0);`
308			`load_x : in std_logic;`
309			`ready : out std_logic`
310			`);`
311			`end component mont_mult_sys_pipeline;`
312
313			`component multiplier_core is`
314			`port(`
315			`clk : in std_logic;`
316			`reset : in std_logic;`
317			`-- operand memory interface (plb shared memory)`
318			`write_enable : in std_logic;`
319			`data_in : in std_logic_vector (31 downto 0);`
320			`rw_address : in std_logic_vector (8 downto 0);`
321			`data_out : out std_logic_vector (31 downto 0);`
322			`collision : out std_logic;`
323			`-- op_sel fifo interface`
324			`fifo_din : in std_logic_vector (31 downto 0);`
325			`fifo_push : in std_logic;`
326			`fifo_full : out std_logic;`
327			`fifo_nopush : out std_logic;`
328			`-- ctrl signals`
329			`start : in std_logic;`
330			`run_auto : in std_logic;`
331			`ready : out std_logic;`
332			`x_sel_single : in std_logic_vector (1 downto 0);`
333			`y_sel_single : in std_logic_vector (1 downto 0);`
334			`dest_op_single : in std_logic_vector (1 downto 0);`
335			`p_sel : in std_logic_vector (1 downto 0);`
336			`calc_time : out std_logic`
337			`);`
338			`end component multiplier_core;`
339
340			`component operand_dp is`
341			`port (`
342			`clka : in std_logic;`
343			`wea : in std_logic_vector(0 downto 0);`
344			`addra : in std_logic_vector(5 downto 0);`
345			`dina : in std_logic_vector(31 downto 0);`
346			`douta : out std_logic_vector(511 downto 0);`
347			`clkb : in std_logic;`
348			`web : in std_logic_vector(0 downto 0);`
349			`addrb : in std_logic_vector(5 downto 0);`
350			`dinb : in std_logic_vector(511 downto 0);`
351			`doutb : out std_logic_vector(31 downto 0)`
352			`);`
353			`end component operand_dp;`
354
355			`component operand_mem is`
356			`generic(n : integer := 1536`
357			`);`
358			`port(`
359			`-- data interface (plb side)`
360			`data_in : in std_logic_vector(31 downto 0);`
361			`data_out : out std_logic_vector(31 downto 0);`
362			`rw_address : in std_logic_vector(8 downto 0);`
363			`-- address structure:`
364			`-- bit: 8 -> '1': modulus`
365			`-- '0': operands`
366			`-- bits: 7-6 -> operand_in_sel in case of bit 8 = '0'`
367			`-- don't care in case of modulus`
368			`-- bits: 5-0 -> modulus_addr / operand_addr resp.`
369
370			`-- operand interface (multiplier side)`
371			`op_sel : in std_logic_vector(1 downto 0);`
372			`xy_out : out std_logic_vector(1535 downto 0);`
373			`m : out std_logic_vector(1535 downto 0);`
374			`result_in : in std_logic_vector(1535 downto 0);`
375			`-- control signals`
376			`load_op : in std_logic;`
377			`load_m : in std_logic;`
378			`load_result : in std_logic;`
379			`result_dest_op : in std_logic_vector(1 downto 0);`
380			`collision : out std_logic;`
381			`-- system clock`
382			`clk : in std_logic`
383			`);`
384			`end component operand_mem;`
385
386			`component operand_ram is`
387			`port( -- write_operand_ack voorzien?`
388			`-- global ports`
389			`clk : in std_logic;`
390			`collision : out std_logic;`
391			`-- bus side connections (32-bit serial)`
392			`operand_addr : in std_logic_vector(5 downto 0);`
393			`operand_in : in std_logic_vector(31 downto 0);`
394			`operand_in_sel : in std_logic_vector(1 downto 0);`
395			`result_out : out std_logic_vector(31 downto 0);`
396			`write_operand : in std_logic;`
397			`-- multiplier side connections (1536 bit parallel)`
398			`result_dest_op : in std_logic_vector(1 downto 0);`
399			`operand_out : out std_logic_vector(1535 downto 0);`
400			`operand_out_sel : in std_logic_vector(1 downto 0); -- controlled by bus side`
401			`write_result : in std_logic;`
402			`result_in : in std_logic_vector(1535 downto 0)`
403			`);`
404			`end component operand_ram;`
405
406			`component operands_sp is`
407			`port (`
408			`clka : in std_logic;`
409			`wea : in std_logic_vector(0 downto 0);`
410			`addra : in std_logic_vector(4 downto 0);`
411			`dina : in std_logic_vector(31 downto 0);`
412			`douta : out std_logic_vector(511 downto 0)`
413			`);`
414			`end component operands_sp;`
415
416			`component standard_cell_block is`
417			`generic (`
418			`width : integer := 16`
419			`);`
420			`port (`
421			`my : in std_logic_vector((width-1) downto 0);`
422			`y : in std_logic_vector((width-1) downto 0);`
423			`m : in std_logic_vector((width-1) downto 0);`
424			`x : in std_logic;`
425			`q : in std_logic;`
426			`a : in std_logic_vector((width-1) downto 0);`
427			`cin : in std_logic;`
428			`cout : out std_logic;`
429			`r : out std_logic_vector((width-1) downto 0)`
430			`);`
431			`end component standard_cell_block;`
432
433			`component standard_stage is`
434			`generic(`
435			`width : integer := 32`
436			`);`
437			`port(`
438			`core_clk : in std_logic;`
439			`my : in std_logic_vector((width-1) downto 0);`
440			`y : in std_logic_vector((width-1) downto 0);`
441			`m : in std_logic_vector((width-1) downto 0);`
442			`xin : in std_logic;`
443			`qin : in std_logic;`
444			`xout : out std_logic;`
445			`qout : out std_logic;`
446			`a_msb : in std_logic;`
447			`cin : in std_logic;`
448			`cout : out std_logic;`
449			`start : in std_logic;`
450			`reset : in std_logic;`
451			`done : out std_logic;`
452			`r : out std_logic_vector((width-1) downto 0)`
453			`);`
454			`end component standard_stage;`
455
456			`component stepping_logic is`
457			`generic(`
458			`n : integer := 1536; -- max nr of steps required to complete a multiplication`
459			`t : integer := 192 -- total nr of steps in the pipeline`
460			`);`
461			`port(`
462			`core_clk : in std_logic;`
463			`start : in std_logic;`
464			`reset : in std_logic;`
465			`t_sel : in integer range 0 to t; -- nr of stages in the pipeline piece`
466			`n_sel : in integer range 0 to n; -- nr of steps required for a complete multiplication`
467			`start_first_stage : out std_logic;`
468			`stepping_done : out std_logic`
469			`);`
470			`end component stepping_logic;`
471
472			`component systolic_pipeline is`
473			`generic(`
474			`n : integer := 1536; -- width of the operands (# bits)`
475			`t : integer := 192; -- number of stages (divider of n) >= 2`
476			`tl : integer := 64 -- best take t = sqrt(n)`
477			`);`
478			`port(`
479			`core_clk : in std_logic;`
480			`my : in std_logic_vector((n) downto 0);`
481			`y : in std_logic_vector((n-1) downto 0);`
482			`m : in std_logic_vector((n-1) downto 0);`
483			`xi : in std_logic;`
484			`start : in std_logic;`
485			`reset : in std_logic;`
486			`p_sel : in std_logic_vector(1 downto 0); -- select which piece of the multiplier will be used`
487			`ready : out std_logic;`
488			`next_x : out std_logic;`
489			`r : out std_logic_vector((n+1) downto 0)`
490			`);`
491			`end component systolic_pipeline;`
492
493			`component x_shift_reg is`
494			`generic(`
495			`n : integer := 1536;`
496			`t : integer := 48;`
497			`tl : integer := 16`
498			`);`
499			`port(`
500			`clk : in std_logic;`

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