OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [modulus_ram_asym.vhd] - Blame information for rev 81

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 67 JonasDC
----------------------------------------------------------------------  
2
----  modulus_ram_asym                                            ---- 
3
----                                                              ---- 
4
----  This file is part of the                                    ----
5
----    Modular Simultaneous Exponentiation Core project          ---- 
6
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
7
----                                                              ---- 
8
----  Description                                                 ---- 
9
----    BRAM memory and logic to store the modulus, due to the    ----
10
----    achitecture, a minimum depth of 2 is needed for this      ----
11
----    module to be inferred into blockram, this version is      ----
12
----    slightly more performant than modulus_ram_gen and uses    ----
13
----    less resources. but does not work on every fpga, only     ----
14
----    the ones that support asymmetric rams.                    ----
15
----                                                              ---- 
16
----  Dependencies:                                               ----
17
----    - dpramblock_asym                                         ----
18
----                                                              ----
19
----  Authors:                                                    ----
20
----      - Geoffrey Ottoy, DraMCo research group                 ----
21
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
22
----                                                              ---- 
23
---------------------------------------------------------------------- 
24
----                                                              ---- 
25
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
26
----                                                              ---- 
27
---- This source file may be used and distributed without         ---- 
28
---- restriction provided that this copyright statement is not    ---- 
29
---- removed from the file and that any derivative work contains  ---- 
30
---- the original copyright notice and the associated disclaimer. ---- 
31
----                                                              ---- 
32
---- This source file is free software; you can redistribute it   ---- 
33
---- and/or modify it under the terms of the GNU Lesser General   ---- 
34
---- Public License as published by the Free Software Foundation; ---- 
35
---- either version 2.1 of the License, or (at your option) any   ---- 
36
---- later version.                                               ---- 
37
----                                                              ---- 
38
---- This source is distributed in the hope that it will be       ---- 
39
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
40
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
41
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
42
---- details.                                                     ---- 
43
----                                                              ---- 
44
---- You should have received a copy of the GNU Lesser General    ---- 
45
---- Public License along with this source; if not, download it   ---- 
46
---- from http://www.opencores.org/lgpl.shtml                     ---- 
47
----                                                              ---- 
48
----------------------------------------------------------------------
49
 
50
library ieee;
51
use ieee.std_logic_1164.all;
52
use ieee.std_logic_arith.all;
53
use ieee.std_logic_unsigned.all;
54
 
55
library mod_sim_exp;
56
use mod_sim_exp.std_functions.all;
57 81 JonasDC
use mod_sim_exp.mod_sim_exp_pkg.all;
58 67 JonasDC
 
59
-- structural description of a RAM to hold the modulus, with 
60
-- adjustable width (64, 128, 256, 512, 576, 640,..) and depth(nr of moduluses)
61
--    formula for available widths: (i*512+(0 or 64 or 128 or 256)) (i=integer number) 
62
--
63
entity modulus_ram_asym is
64
  generic(
65
    width : integer := 1536;  -- must be a multiple of 32
66
    depth : integer := 2;     -- nr of moduluses
67
    device : string := "xilinx"
68
  );
69
  port(
70
    clk            : in std_logic;
71
      -- bus side
72
    write_modulus  : in std_logic; -- write enable
73
    modulus_in_sel : in std_logic_vector(log2(depth)-1 downto 0); -- modulus operand to write to
74
    modulus_addr   : in std_logic_vector(log2((width)/32)-1 downto 0); -- modulus word(32-bit) address
75
    modulus_in     : in std_logic_vector(31 downto 0); -- modulus word data in
76
    modulus_sel    : in std_logic_vector(log2(depth)-1 downto 0); -- selects the modulus to use for multiplications
77
      -- multiplier side
78
    modulus_out    : out std_logic_vector(width-1 downto 0)
79
  );
80
end modulus_ram_asym;
81
 
82
architecture structural of modulus_ram_asym is
83
  -- constants
84
  constant RAMblock_maxwidth   : integer := 512;
85
  constant nrRAMblocks_full    : integer := width/RAMblock_maxwidth;
86
  constant RAMblock_part       : integer := width rem RAMblock_maxwidth;
87
  constant RAMblock_part_width : integer := width-(nrRAMblocks_full*RAMblock_maxwidth);
88
  constant RAMselect_aw        : integer := log2(width/32)-log2(nrRAMblocks_full/32);
89
 
90
begin
91
 
92
  -- generate (width/512) ramblocks with a given depth
93
  -- these rams are tyed together to form the following structure
94
  --  dual port ram:
95
  --  - PORT A : 32-bit write
96
  --  - PORT B : (width)-bit read
97
  -- 
98
  single_block : if (width <= RAMblock_maxwidth) generate
99
    signal waddr : std_logic_vector(log2((width*depth)/32)-1 downto 0);
100
  begin
101
    waddr <= modulus_in_sel & modulus_addr;
102
 
103
    ramblock: entity mod_sim_exp.dpramblock_asym
104
    generic map(
105
      width => width,
106
      depth => depth,
107
      device  => device
108
    )
109
    port map(
110
      clk => clk,
111
      -- write port
112
      waddr => waddr,
113
      we    => write_modulus,
114
      din   => modulus_in,
115
      -- read port
116
      raddr => modulus_sel,
117
      dout  => modulus_out
118
    );
119
  end generate;
120
 
121
  multiple_full_blocks : if (width > RAMblock_maxwidth) generate
122
    -- signals for multiple blocks
123
    signal waddr  : std_logic_vector(log2(RAMblock_maxwidth*depth/32)-1 downto 0);
124
    signal we_RAM : std_logic_vector(nrRAMblocks_full-1 downto 0);
125
  begin
126
    ramblocks_full : for i in 0 to nrRAMblocks_full generate
127
      -- write port signal
128
      waddr <= modulus_in_sel & modulus_addr(log2(RAMblock_maxwidth/32)-1 downto 0);
129
 
130
      full_ones : if (i < nrRAMblocks_full) generate
131 81 JonasDC
        ramblock_full : dpramblock_asym
132 67 JonasDC
        generic map(
133
          width  => RAMblock_maxwidth,
134
          depth  => depth,
135
          device => device
136
        )
137
        port map(
138
          clk => clk,
139
          -- write port
140
          waddr => waddr,
141
          we    => we_RAM(i),
142
          din   => modulus_in,
143
          -- read port
144
          raddr => modulus_sel,
145
          dout  => modulus_out((i+1)*RAMblock_maxwidth-1 downto i*RAMblock_maxwidth)
146
        );
147
        -- we
148
        process (write_modulus, modulus_addr)
149
        begin
150
          if modulus_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32)) = conv_std_logic_vector(i,RAMselect_aw) then
151
            we_RAM(i) <= write_modulus;
152
          else
153
            we_RAM(i) <= '0';
154
          end if;
155
        end process;
156
      end generate; -- end of if generate for full blocks
157
 
158
      optional_part : if (i = nrRAMblocks_full) and (RAMblock_part /= 0) generate
159
        -- signals for optional part
160
        signal waddr_part : std_logic_vector(log2(RAMblock_part_width*depth/32)-1 downto 0);
161
        signal we_part    : std_logic;
162
      begin
163
        -- write port signal
164
        waddr_part <= modulus_in_sel & modulus_addr(log2(RAMblock_part_width/32)-1 downto 0);
165
        ramblock_part : entity mod_sim_exp.dpramblock_asym
166
        generic map(
167
          width  => RAMblock_part_width,
168
          depth  => depth,
169
          device => device
170
        )
171
        port map(
172
          clk => clk,
173
          -- write port
174
          waddr => waddr_part,
175
          we    => we_part,
176
          din   => modulus_in,
177
          -- read port
178
          raddr => modulus_sel,
179
          dout  => modulus_out(width-1 downto i*RAMblock_maxwidth)
180
        );
181
 
182
        -- we_part
183
        process (write_modulus, modulus_addr)
184
        begin
185
          if modulus_addr(log2(width/32)-1 downto log2(RAMblock_maxwidth/32)) = conv_std_logic_vector(i,RAMselect_aw) then
186
            we_part <= write_modulus;
187
          else
188
            we_part <= '0';
189
          end if;
190
        end process;
191
      end generate;-- end of if generate for part block
192
    end generate;-- end of for generate
193
  end generate;-- end of if generate for multiple blocks
194
 
195
end structural;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.