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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [operand_dp.vhd] - Blame information for rev 94

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1 94 JonasDC
--------------------------------------------------------------------------------
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--     (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved.            --
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--                                                                            --
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--     This file contains confidential and proprietary information            --
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--     of Xilinx, Inc. and is protected under U.S. and                        --
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--     international copyright and other intellectual property                --
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--     laws.                                                                  --
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--     rights to the materials distributed herewith. Except as                --
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--     otherwise provided in a valid license issued to you by                 --
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--     Xilinx, and to the maximum extent permitted by applicable              --
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--     THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS               --
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--     PART OF THIS FILE AT ALL TIMES.                                        --
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--------------------------------------------------------------------------------
48 2 JonasDC
-- You must compile the wrapper file operand_dp.vhd when simulating
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-- the core, operand_dp. When compiling the wrapper file, be sure to
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-- reference the XilinxCoreLib VHDL simulation library. For detailed
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-- instructions, please refer to the "CORE Generator Help".
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-- The synthesis directives "translate_off/translate_on" specified
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-- below are supported by Xilinx, Mentor Graphics and Synplicity
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-- synthesis tools. Ensure they are correct for your synthesis tool(s).
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- synthesis translate_off
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Library XilinxCoreLib;
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-- synthesis translate_on
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ENTITY operand_dp IS
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        port (
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        clka: in std_logic;
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        wea: in std_logic_vector(0 downto 0);
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        addra: in std_logic_vector(5 downto 0);
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        dina: in std_logic_vector(31 downto 0);
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        douta: out std_logic_vector(31 downto 0);
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        clkb: in std_logic;
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        web: in std_logic_vector(0 downto 0);
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        addrb: in std_logic_vector(1 downto 0);
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        dinb: in std_logic_vector(511 downto 0);
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        doutb: out std_logic_vector(511 downto 0));
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END operand_dp;
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76 94 JonasDC
ARCHITECTURE operand_dp_a OF operand_dp IS
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-- synthesis translate_off
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component wrapped_operand_dp
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        port (
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        clka: in std_logic;
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        wea: in std_logic_vector(0 downto 0);
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        addra: in std_logic_vector(5 downto 0);
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        dina: in std_logic_vector(31 downto 0);
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        douta: out std_logic_vector(31 downto 0);
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        clkb: in std_logic;
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        web: in std_logic_vector(0 downto 0);
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        addrb: in std_logic_vector(1 downto 0);
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        dinb: in std_logic_vector(511 downto 0);
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        doutb: out std_logic_vector(511 downto 0));
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end component;
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-- Configuration specification 
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        for all : wrapped_operand_dp use entity XilinxCoreLib.blk_mem_gen_v3_3(behavioral)
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                generic map(
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                        c_has_regceb => 0,
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                        c_has_regcea => 0,
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                        c_mem_type => 2,
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                        c_rstram_b => 0,
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                        c_rstram_a => 0,
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                        c_has_injecterr => 0,
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                        c_rst_type => "SYNC",
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                        c_prim_type => 1,
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                        c_read_width_b => 512,
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                        c_initb_val => "0",
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                        c_family => "virtex6",
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                        c_read_width_a => 32,
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                        c_disable_warn_bhv_coll => 0,
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                        c_write_mode_b => "WRITE_FIRST",
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                        c_init_file_name => "no_coe_file_loaded",
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                        c_write_mode_a => "WRITE_FIRST",
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                        c_mux_pipeline_stages => 0,
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                        c_has_mem_output_regs_b => 0,
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                        c_has_mem_output_regs_a => 0,
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                        c_load_init_file => 0,
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                        c_xdevicefamily => "virtex6",
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                        c_write_depth_b => 4,
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                        c_write_depth_a => 64,
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                        c_has_rstb => 0,
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                        c_has_rsta => 0,
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                        c_has_mux_output_regs_b => 0,
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                        c_inita_val => "0",
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                        c_has_mux_output_regs_a => 0,
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                        c_addra_width => 6,
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                        c_addrb_width => 2,
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                        c_default_data => "0",
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                        c_use_ecc => 0,
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                        c_algorithm => 1,
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                        c_disable_warn_bhv_range => 0,
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                        c_write_width_b => 512,
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                        c_write_width_a => 32,
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                        c_read_depth_b => 4,
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                        c_read_depth_a => 64,
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                        c_byte_size => 9,
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                        c_sim_collision_check => "ALL",
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                        c_common_clk => 0,
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                        c_wea_width => 1,
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                        c_has_enb => 0,
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                        c_web_width => 1,
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                        c_has_ena => 0,
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                        c_use_byte_web => 0,
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                        c_use_byte_wea => 0,
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                        c_rst_priority_b => "CE",
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                        c_rst_priority_a => "CE",
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                        c_use_default_data => 0);
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-- synthesis translate_on
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BEGIN
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-- synthesis translate_off
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U0 : wrapped_operand_dp
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                port map (
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                        clka => clka,
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                        wea => wea,
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                        addra => addra,
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                        dina => dina,
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                        douta => douta,
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                        clkb => clkb,
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                        web => web,
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                        addrb => addrb,
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                        dinb => dinb,
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                        doutb => doutb);
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-- synthesis translate_on
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162 94 JonasDC
END operand_dp_a;
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