OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [operand_mem.vhd] - Blame information for rev 94

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 63 JonasDC
----------------------------------------------------------------------  
2 69 JonasDC
----  operand_mem                                                 ---- 
3 63 JonasDC
----                                                              ---- 
4
----  This file is part of the                                    ----
5
----    Modular Simultaneous Exponentiation Core project          ---- 
6
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
7
----                                                              ---- 
8
----  Description                                                 ---- 
9 69 JonasDC
----    RAM memory and logic to the store operands and the        ----
10
----    modulus for the montgomery multiplier, the user has a     ----
11
----    choise between 3 memory styles, more detail in the        ----
12
----    documentation                                             ----
13
----                                                              ----            
14 63 JonasDC
----  Dependencies:                                               ----
15 69 JonasDC
----    - operand_ram                                             ----
16
----    - modulus_ram                                             ----
17 63 JonasDC
----    - operand_ram_gen                                         ----
18
----    - modulus_ram_gen                                         ----
19 69 JonasDC
----    - operand_ram_asym                                        ----
20
----    - modulus_ram_asym                                        ----
21 63 JonasDC
----                                                              ----
22
----  Authors:                                                    ----
23
----      - Geoffrey Ottoy, DraMCo research group                 ----
24
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
25
----                                                              ---- 
26
---------------------------------------------------------------------- 
27
----                                                              ---- 
28
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
29
----                                                              ---- 
30
---- This source file may be used and distributed without         ---- 
31
---- restriction provided that this copyright statement is not    ---- 
32
---- removed from the file and that any derivative work contains  ---- 
33
---- the original copyright notice and the associated disclaimer. ---- 
34
----                                                              ---- 
35
---- This source file is free software; you can redistribute it   ---- 
36
---- and/or modify it under the terms of the GNU Lesser General   ---- 
37
---- Public License as published by the Free Software Foundation; ---- 
38
---- either version 2.1 of the License, or (at your option) any   ---- 
39
---- later version.                                               ---- 
40
----                                                              ---- 
41
---- This source is distributed in the hope that it will be       ---- 
42
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
43
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
44
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
45
---- details.                                                     ---- 
46
----                                                              ---- 
47
---- You should have received a copy of the GNU Lesser General    ---- 
48
---- Public License along with this source; if not, download it   ---- 
49
---- from http://www.opencores.org/lgpl.shtml                     ---- 
50
----                                                              ---- 
51
----------------------------------------------------------------------
52
 
53
library ieee;
54
use ieee.std_logic_1164.all;
55
use ieee.std_logic_arith.all;
56
use ieee.std_logic_unsigned.all;
57
 
58
library mod_sim_exp;
59
use mod_sim_exp.mod_sim_exp_pkg.all;
60
use mod_sim_exp.std_functions.all;
61
 
62
-- address structure:
63 75 JonasDC
-- bit: 8   ->  '1': modulus
64
--              '0': operands
65
-- bits: 7-6 -> operand_in_sel in case of highest bit = '0'
66
--              modulus_in_sel in case of highest bit = '1'
67 63 JonasDC
-- bits: (log2(width/32)-1)-0 -> modulus_addr / operand_addr resp.
68
-- 
69 69 JonasDC
entity operand_mem is
70 63 JonasDC
  generic(
71 69 JonasDC
    width     : integer := 1536; -- width of the operands
72
    nr_op     : integer := 4; -- nr of operand storages, has to be greater than nr_m
73
    nr_m      : integer := 2; -- nr of modulus storages
74
    mem_style : string  := "asym"; -- xil_prim, generic, asym are valid options
75 94 JonasDC
    device    : string  := "xilinx"   -- xilinx, altera are valid options
76 63 JonasDC
  );
77
  port(
78
    -- data interface (plb side)
79 94 JonasDC
    bus_clk      : in std_logic;
80 63 JonasDC
    data_in      : in std_logic_vector(31 downto 0);
81
    data_out     : out std_logic_vector(31 downto 0);
82 75 JonasDC
    rw_address   : in std_logic_vector(8 downto 0);
83 63 JonasDC
    write_enable : in std_logic;
84
    -- operand interface (multiplier side)
85 94 JonasDC
    core_clk  : in std_logic;
86 63 JonasDC
    op_sel    : in std_logic_vector(log2(nr_op)-1 downto 0);
87
    xy_out    : out std_logic_vector((width-1) downto 0);
88
    m         : out std_logic_vector((width-1) downto 0);
89
    result_in : in std_logic_vector((width-1) downto 0);
90
    -- control signals
91
    load_result    : in std_logic;
92
    result_dest_op : in std_logic_vector(log2(nr_op)-1 downto 0);
93
    collision      : out std_logic;
94
    modulus_sel    : in std_logic_vector(log2(nr_m)-1 downto 0)
95
  );
96 69 JonasDC
end operand_mem;
97 63 JonasDC
 
98 69 JonasDC
architecture structural of operand_mem is
99
  -- constants
100 63 JonasDC
  constant wordaddr_aw : integer := log2(width/32);
101
  constant opaddr_aw   : integer := log2(nr_op);
102 69 JonasDC
  constant maddr_aw    : integer := log2(nr_m);
103 63 JonasDC
  constant total_aw    : integer := 1+opaddr_aw+wordaddr_aw;
104
 
105 69 JonasDC
  -- internal signals
106 63 JonasDC
  signal xy_data_i        : std_logic_vector(31 downto 0);
107
  signal xy_addr_i        : std_logic_vector(wordaddr_aw-1 downto 0);
108
  signal operand_in_sel_i : std_logic_vector(opaddr_aw-1 downto 0);
109
  signal modulus_in_sel_i : std_logic_vector(maddr_aw-1 downto 0);
110
 
111
  signal load_op : std_logic;
112
 
113 69 JonasDC
  signal m_addr_i : std_logic_vector(wordaddr_aw-1 downto 0);
114
  signal load_m   : std_logic;
115
  signal m_data_i : std_logic_vector(31 downto 0);
116 63 JonasDC
 
117
begin
118
 
119
        -- map inputs
120
        xy_addr_i <= rw_address(wordaddr_aw-1 downto 0);
121
        m_addr_i <= rw_address(wordaddr_aw-1 downto 0);
122 75 JonasDC
        operand_in_sel_i <= rw_address(7 downto 6);
123
        modulus_in_sel_i <= rw_address(6 downto 6);
124 63 JonasDC
        xy_data_i <= data_in;
125
        m_data_i <= data_in;
126
 
127 69 JonasDC
  -- select right memory with highest address bit
128 75 JonasDC
        load_op <= write_enable when (rw_address(8) = '0') else '0';
129
  load_m <= write_enable when (rw_address(8) = '1') else '0';
130 63 JonasDC
 
131 69 JonasDC
  xil_prim_RAM : if mem_style="xil_prim" generate
132
    -- xy operand storage
133
    xy_ram_xil : operand_ram
134
    port map(
135 94 JonasDC
      bus_clk         => bus_clk,
136
      core_clk        => core_clk,
137 69 JonasDC
      collision       => collision,
138
      operand_addr    => xy_addr_i,
139
      operand_in      => xy_data_i,
140
      operand_in_sel  => operand_in_sel_i,
141
      result_out      => data_out,
142
      write_operand   => load_op,
143
      operand_out     => xy_out,
144
      operand_out_sel => op_sel,
145
      result_dest_op  => result_dest_op,
146
      write_result    => load_result,
147
      result_in       => result_in
148
    );
149
 
150
    -- modulus storage
151
    m_ram_xil : modulus_ram
152
    port map(
153 94 JonasDC
      clk           => bus_clk,
154 69 JonasDC
      modulus_addr  => m_addr_i,
155
      write_modulus => load_m,
156
      modulus_in    => m_data_i,
157
      modulus_out   => m
158
    );
159
  end generate;
160 63 JonasDC
 
161 69 JonasDC
  gen_RAM : if mem_style="generic" generate
162
    -- xy operand storage
163
    xy_ram_gen : operand_ram_gen
164
    generic map(
165
      width => width,
166
      depth => nr_op
167
    )
168
    port map(
169
      collision       => collision,
170 94 JonasDC
      bus_clk         => bus_clk,
171 69 JonasDC
      operand_addr    => xy_addr_i,
172
      operand_in      => xy_data_i,
173
      operand_in_sel  => operand_in_sel_i,
174
      result_out      => data_out,
175
      write_operand   => load_op,
176
      operand_out     => xy_out,
177
      operand_out_sel => op_sel,
178
      result_dest_op  => result_dest_op,
179 94 JonasDC
      core_clk        => core_clk,
180 69 JonasDC
      write_result    => load_result,
181
      result_in       => result_in
182
    );
183 63 JonasDC
 
184 69 JonasDC
    -- modulus storage
185
    m_ram_gen : modulus_ram_gen
186
    generic map(
187
      width => width,
188
      depth => nr_m
189
    )
190
    port map(
191 94 JonasDC
      bus_clk         => bus_clk,
192 69 JonasDC
      modulus_in_sel => modulus_in_sel_i,
193
      modulus_addr   => m_addr_i,
194
      write_modulus  => load_m,
195
      modulus_in     => m_data_i,
196 94 JonasDC
      core_clk       => core_clk,
197 69 JonasDC
      modulus_out    => m,
198
      modulus_sel    => modulus_sel
199
    );
200
  end generate;
201
 
202
  asym_RAM : if mem_style="asym" generate
203
    -- xy operand storage
204
    xy_ram_asym : operand_ram_asym
205
    generic map(
206
      width => width,
207
      depth => nr_op,
208
      device => device
209
    )
210
    port map(
211
      collision       => collision,
212 94 JonasDC
      bus_clk         => bus_clk,
213 69 JonasDC
      operand_addr    => xy_addr_i,
214
      operand_in      => xy_data_i,
215
      operand_in_sel  => operand_in_sel_i,
216
      result_out      => data_out,
217
      write_operand   => load_op,
218
      operand_out     => xy_out,
219
      operand_out_sel => op_sel,
220
      result_dest_op  => result_dest_op,
221 94 JonasDC
      core_clk        => core_clk,
222 69 JonasDC
      write_result    => load_result,
223
      result_in       => result_in
224
    );
225
 
226
    -- modulus storage
227
    m_ram_asym : modulus_ram_asym
228
    generic map(
229
      width => width,
230
      depth => nr_m,
231
      device => device
232
    )
233
    port map(
234 94 JonasDC
      bus_clk        => bus_clk,
235 69 JonasDC
      modulus_in_sel => modulus_in_sel_i,
236
      modulus_addr   => m_addr_i,
237
      write_modulus  => load_m,
238
      modulus_in     => m_data_i,
239 94 JonasDC
      core_clk       => core_clk,
240 69 JonasDC
      modulus_out    => m,
241
      modulus_sel    => modulus_sel
242
    );
243
  end generate;
244
 
245
end structural;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.