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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [register_n.vhd] - Blame information for rev 2

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1 2 JonasDC
------------------------------------------------------------------------------------ 
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--                      
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-- Geoffrey Ottoy - DraMCo research group
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--
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-- Module Name: register_n.vhd / entity register_n
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-- 
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-- Last Modified:       24/11/2011 
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-- 
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-- Description:         n bit register
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--
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--
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-- Dependencies:        FDCE
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--
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-- Revision:
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-- Revision 3.00 - Replaced LDCE primitive with FDCE primitive
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-- Revision 2.00 - Replaced behavioral architecture with structural using FPGA
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--                 primitives.
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--      Revision 1.00 - Architecture
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--      Revision 0.01 - File Created
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--
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--
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------------------------------------------------------------------------------------
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--
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-- NOTICE:
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--
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-- Copyright DraMCo research group. 2011. This code may be contain portions patented
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-- by other third parties!
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--
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------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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library UNISIM;
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use UNISIM.VComponents.all;
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entity register_n is
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        generic( n : integer := 4
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        );
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   port(core_clk : in  STD_LOGIC;
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                             ce : in  STD_LOGIC;
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                          reset : in  STD_LOGIC;
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                            din : in  STD_LOGIC_VECTOR((n-1) downto 0);
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                      dout : out STD_LOGIC_VECTOR((n-1) downto 0)
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        );
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end register_n;
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architecture Structural of register_n is
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        signal dout_i : std_logic_vector((n-1) downto 0) := (others => '0');
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begin
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        dout <= dout_i;
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        N_REGS: for i in 0 to n-1 generate
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                FDCE_inst : FDCE
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                generic map (
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                        INIT => '0')     -- Initial value of latch ('0' or '1')  
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                port map (
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                        Q => dout_i(i),  -- Data output
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                        CLR => reset,    -- Asynchronous clear/reset input
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                        D => din(i),     -- Data input
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                        C => core_clk,   -- Gate input
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                        CE => ce         -- Gate enable input
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                );
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        end generate;
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end Structural;

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