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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [stepping_logic.vhd] - Blame information for rev 19

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1 3 JonasDC
----------------------------------------------------------------------  
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----  stepping_logic                                              ---- 
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----                                                              ---- 
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----  This file is part of the                                    ----
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----    Modular Simultaneous Exponentiation Core project          ---- 
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----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
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----                                                              ---- 
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----  Description                                                 ---- 
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----    stepping logic to control the pipeline for one            ----
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----    montgommery multiplication                                ----
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----                                                              ----
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----  Dependencies:                                               ----
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----    - d_flip_flop                                             ----
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----    - counter_sync                                            ----
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----                                                              ----
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----  Authors:                                                    ----
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----      - Geoffrey Ottoy, DraMCo research group                 ----
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----      - Jonas De Craene, JonasDC@opencores.org                ---- 
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----                                                              ---- 
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---------------------------------------------------------------------- 
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----                                                              ---- 
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
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----                                                              ---- 
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---- This source file may be used and distributed without         ---- 
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---- restriction provided that this copyright statement is not    ---- 
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---- removed from the file and that any derivative work contains  ---- 
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---- the original copyright notice and the associated disclaimer. ---- 
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----                                                              ---- 
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---- This source file is free software; you can redistribute it   ---- 
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---- and/or modify it under the terms of the GNU Lesser General   ---- 
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---- Public License as published by the Free Software Foundation; ---- 
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---- either version 2.1 of the License, or (at your option) any   ---- 
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---- later version.                                               ---- 
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----                                                              ---- 
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---- This source is distributed in the hope that it will be       ---- 
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---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
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---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
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---- details.                                                     ---- 
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----                                                              ---- 
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---- You should have received a copy of the GNU Lesser General    ---- 
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---- Public License along with this source; if not, download it   ---- 
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---- from http://www.opencores.org/lgpl.shtml                     ---- 
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----                                                              ---- 
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----------------------------------------------------------------------
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47 3 JonasDC
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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library mod_sim_exp;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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-- stepping logic for the pipeline, generates the start pulses for the
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-- first stage and keeps track of when the last stages are done
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entity stepping_logic is
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  generic(
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    n : integer := 1536;  -- max nr of steps required to complete a multiplication
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    t : integer := 192    -- total nr of steps in the pipeline
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  );
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  port(
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    core_clk          : in  std_logic;  -- clock input
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    start             : in  std_logic;  -- start signal for pipeline (one multiplication)
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    reset             : in  std_logic;  -- reset signal
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    t_sel             : in integer range 0 to t; -- nr of stages in the pipeline piece
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    n_sel             : in integer range 0 to n; -- nr of steps(bits in operands) required for a complete multiplication
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    start_first_stage : out std_logic;  -- start pulse output for first stage
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    stepping_done     : out std_logic   -- done signal
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  );
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end stepping_logic;
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architecture Behavioral of stepping_logic is
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  -- signals for the first stage control, pulses and counters
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  signal first_stage_done     : std_logic; -- indicates the first stage is done running for this multiplication
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  signal first_stage_active   : std_logic; -- indicates the first stage is active
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  signal first_stage_active_d : std_logic; -- delayed version of first_stage_active
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  signal start_first_stage_i  : std_logic; -- internal version of start_first_stage output
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  -- signals for the last stages control and counter
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  signal last_stages_done     : std_logic; -- indicates the last stages are done running for this multiplication
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  signal last_stages_active   : std_logic; -- indicates the last stages are active
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  signal last_stages_active_d : std_logic; -- delayed version of last_stages_active
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begin
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        -- map outputs
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        stepping_done <= last_stages_done;
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        -- internal signals
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        --------------------
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        -- first_stage_active signal gets active from a start pulse 
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        --                                inactive from first_stage_done pulse
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        first_stage_active <= start or (first_stage_active_d and not first_stage_done);
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        -- done signal gets active from a first_stage_done pulse
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        --                  inactive from last_stages_done pulse
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        last_stages_active <= first_stage_done or (last_stages_active_d and not last_stages_done);
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        -- map start_first_stage_i to output, but also use the initial start pulse
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        start_first_stage <= start or start_first_stage_i;
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  last_stages_active_delay : d_flip_flop
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  port map(
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    core_clk => core_clk,
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    reset    => reset,
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    din      => last_stages_active,
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    dout     => last_stages_active_d
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  );
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  first_stage_active_delay : d_flip_flop
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  port map(
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    core_clk => core_clk,
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    reset    => reset,
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    din      => first_stage_active,
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    dout     => first_stage_active_d
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  );
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  -- the counters
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  ----------------
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  -- for counting the last steps (waiting for the other stages to stop)
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  -- counter for keeping track of how many stages are done
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  laststeps_counter : counter_sync
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  generic map(
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    max_value => t
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  )
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  port map(
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    reset_value => t_sel,
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    core_clk    => core_clk,
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    ce          => last_stages_active,
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    reset       => reset,
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    overflow    => last_stages_done
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  );
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  -- counter for keeping track of how many times the first stage is started
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  -- counts bits in operand x till operand width then generates pulse on first_stage_done
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  steps_counter : counter_sync
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  generic map(
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    max_value => n
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  )
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  port map(
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    reset_value => (n_sel),
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    core_clk    => core_clk,
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    ce          => start_first_stage_i,
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    reset       => reset,
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    overflow    => first_stage_done
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  );
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  -- the output (overflow) of this counter starts the first stage every 2 clock cycles
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  substeps_counter : counter_sync
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  generic map(
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    max_value => 2
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  )
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  port map(
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    reset_value => 2,
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    core_clk    => core_clk,
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    ce          => first_stage_active,
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    reset       => reset,
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    overflow    => start_first_stage_i
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  );
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end Behavioral;

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