OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [axi/] [msec_ipcore_axilite.vhd] - Blame information for rev 94

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 84 JonasDC
----------------------------------------------------------------------  
2
----  msec_ipcore_axilite                                         ---- 
3
----                                                              ---- 
4
----  This file is part of the                                    ----
5
----    Modular Simultaneous Exponentiation Core project          ---- 
6
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
7
----                                                              ---- 
8
----  Description                                                 ---- 
9
----    AXI-Lite bus interface for the mod_sim_exp_core. Has a    ----
10
----    fixed address decoder, address offsets are:               ----
11
----                                                              ----
12
----      M       : 0xXXXX0000                                    ----
13
----      OP0     : 0xXXXX1000                                    ----
14
----      OP1     : 0xXXXX2000                                    ----
15
----      OP2     : 0xXXXX3000                                    ----
16
----      OP3     : 0xXXXX4000                                    ----
17
----      FIFO    : 0xXXXX5000                                    ----
18
----      Control : 0xXXXX6000                                    ----
19
----                                                              ----
20
----    only the XXXX part of the address can be chosen freely    ----
21
----                                                              ----
22
----  Dependencies:                                               ----
23
----    - mod_sim_exp_core                                        ----
24
----                                                              ----
25
----  Authors:                                                    ----
26
----      - Geoffrey Ottoy, DraMCo research group                 ----
27
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
28
----                                                              ---- 
29
---------------------------------------------------------------------- 
30
----                                                              ---- 
31
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG   ---- 
32
----                                                              ---- 
33
---- This source file may be used and distributed without         ---- 
34
---- restriction provided that this copyright statement is not    ---- 
35
---- removed from the file and that any derivative work contains  ---- 
36
---- the original copyright notice and the associated disclaimer. ---- 
37
----                                                              ---- 
38
---- This source file is free software; you can redistribute it   ---- 
39
---- and/or modify it under the terms of the GNU Lesser General   ---- 
40
---- Public License as published by the Free Software Foundation; ---- 
41
---- either version 2.1 of the License, or (at your option) any   ---- 
42
---- later version.                                               ---- 
43
----                                                              ---- 
44
---- This source is distributed in the hope that it will be       ---- 
45
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
46
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
47
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
48
---- details.                                                     ---- 
49
----                                                              ---- 
50
---- You should have received a copy of the GNU Lesser General    ---- 
51
---- Public License along with this source; if not, download it   ---- 
52
---- from http://www.opencores.org/lgpl.shtml                     ---- 
53
----                                                              ---- 
54
----------------------------------------------------------------------
55 82 JonasDC
 
56
library ieee;
57
use ieee.std_logic_1164.all;
58
use ieee.std_logic_arith.all;
59
use ieee.std_logic_unsigned.all;
60
 
61
library mod_sim_exp;
62
use mod_sim_exp.mod_sim_exp_pkg;
63
 
64
------------------------------------------------------------------------------
65
-- Entity section
66
------------------------------------------------------------------------------
67
-- Definition of Generics:
68
--   C_S_AXI_DATA_WIDTH           -- AXI4LITE slave: Data width
69
--   C_S_AXI_ADDR_WIDTH           -- AXI4LITE slave: Address Width
70
--   C_BASEADDR                   -- AXI4LITE slave: base address
71
--   C_HIGHADDR                   -- AXI4LITE slave: high address
72
--
73
-- Definition of Ports:
74
--   S_AXI_ACLK                   -- AXI4LITE slave: Clock 
75
--   S_AXI_ARESETN                -- AXI4LITE slave: Reset
76
--   S_AXI_AWADDR                 -- AXI4LITE slave: Write address
77
--   S_AXI_AWVALID                -- AXI4LITE slave: Write address valid
78
--   S_AXI_WDATA                  -- AXI4LITE slave: Write data
79
--   S_AXI_WSTRB                  -- AXI4LITE slave: Write strobe
80
--   S_AXI_WVALID                 -- AXI4LITE slave: Write data valid
81
--   S_AXI_BREADY                 -- AXI4LITE slave: Response ready
82
--   S_AXI_ARADDR                 -- AXI4LITE slave: Read address
83
--   S_AXI_ARVALID                -- AXI4LITE slave: Read address valid
84
--   S_AXI_RREADY                 -- AXI4LITE slave: Read data ready
85
--   S_AXI_ARREADY                -- AXI4LITE slave: read addres ready
86
--   S_AXI_RDATA                  -- AXI4LITE slave: Read data
87
--   S_AXI_RRESP                  -- AXI4LITE slave: Read data response
88
--   S_AXI_RVALID                 -- AXI4LITE slave: Read data valid
89
--   S_AXI_WREADY                 -- AXI4LITE slave: Write data ready
90
--   S_AXI_BRESP                  -- AXI4LITE slave: Response
91
--   S_AXI_BVALID                 -- AXI4LITE slave: Resonse valid
92
--   S_AXI_AWREADY                -- AXI4LITE slave: Wrte address ready
93
------------------------------------------------------------------------------
94
 
95 84 JonasDC
entity msec_ipcore_axilite is
96
  generic(
97
    -- Multiplier parameters
98 82 JonasDC
    C_NR_BITS_TOTAL   : integer := 1536;
99
    C_NR_STAGES_TOTAL : integer := 96;
100
    C_NR_STAGES_LOW   : integer := 32;
101
    C_SPLIT_PIPELINE  : boolean := true;
102 94 JonasDC
    C_FIFO_AW         : integer := 7;
103 85 JonasDC
    C_MEM_STYLE       : string  := "asym"; -- xil_prim, generic, asym are valid options
104 84 JonasDC
    C_FPGA_MAN        : string  := "xilinx";    -- xilinx, altera are valid options
105
    -- Bus protocol parameters
106 82 JonasDC
    C_S_AXI_DATA_WIDTH             : integer              := 32;
107
    C_S_AXI_ADDR_WIDTH             : integer              := 32;
108
    C_BASEADDR                     : std_logic_vector     := X"FFFFFFFF";
109
    C_HIGHADDR                     : std_logic_vector     := X"00000000"
110
  );
111 84 JonasDC
  port(
112 82 JonasDC
    --USER ports
113 94 JonasDC
    core_clk                      : in std_logic;
114 82 JonasDC
    calc_time                     : out std_logic;
115
    IntrEvent                     : out std_logic;
116
    -------------------------
117
    -- AXI4lite interface
118
    -------------------------
119
    --- Global signals
120
    S_AXI_ACLK                     : in  std_logic;
121
    S_AXI_ARESETN                  : in  std_logic;
122
    --- Write address channel
123
    S_AXI_AWADDR                   : in  std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
124
    S_AXI_AWVALID                  : in  std_logic;
125
    S_AXI_AWREADY                  : out std_logic;
126
    --- Write data channel
127
    S_AXI_WDATA                    : in  std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
128
    S_AXI_WVALID                   : in  std_logic;
129
    S_AXI_WREADY                   : out std_logic;
130
    S_AXI_WSTRB                    : in  std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
131
    --- Write response channel
132
    S_AXI_BVALID                   : out std_logic;
133
    S_AXI_BREADY                   : in  std_logic;
134
    S_AXI_BRESP                    : out std_logic_vector(1 downto 0);
135
    --- Read address channel
136
    S_AXI_ARADDR                   : in  std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
137
    S_AXI_ARVALID                  : in  std_logic;
138
    S_AXI_ARREADY                  : out std_logic;
139
    --- Read data channel
140
    S_AXI_RDATA                    : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
141
    S_AXI_RVALID                   : out std_logic;
142
    S_AXI_RREADY                   : in  std_logic;
143
    S_AXI_RRESP                    : out std_logic_vector(1 downto 0)
144
  );
145
 
146
  attribute MAX_FANOUT : string;
147
  attribute SIGIS      : string;
148
  attribute MAX_FANOUT of S_AXI_ACLK    : signal is "10000";
149
  attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
150
  attribute SIGIS of S_AXI_ACLK         : signal is "Clk";
151
  attribute SIGIS of S_AXI_ARESETN      : signal is "Rst";
152 84 JonasDC
end entity msec_ipcore_axilite;
153 82 JonasDC
 
154
------------------------------------------------------------------------------
155
-- Architecture section
156
------------------------------------------------------------------------------
157
 
158 84 JonasDC
architecture IMP of msec_ipcore_axilite is
159 82 JonasDC
  type axi_states is (addr_wait, read_state, write_state, response_state);
160
  signal state : axi_states;
161
 
162
  signal address : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
163
  signal reset : std_logic;
164
 
165 84 JonasDC
  signal S_AXI_BVALID_i : std_logic;
166 82 JonasDC
 
167
  -- selection signals
168
  signal cs_array           : std_logic_vector(6 downto 0);
169
  signal slv_reg_selected : std_logic;
170
  signal op_mem_selected    : std_logic;
171
  signal op_sel             : std_logic_vector(1 downto 0);
172
  signal MNO_sel            : std_logic;
173
 
174
  -- slave register signals
175
  signal slv_reg : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
176
  signal slv_reg_write_enable : std_logic;
177
  signal load_flags : std_logic;
178
 
179
  -- core interface signeals
180
  signal write_enable : std_logic;
181
  signal core_write_enable : std_logic;
182
  signal core_fifo_push : std_logic;
183
  signal core_data_out : std_logic_vector(31 downto 0);
184
  signal core_rw_address : std_logic_vector(8 downto 0);
185
 
186
  ------------------------------------------------------------------
187
  -- Signals for multiplier core interrupt
188
  ------------------------------------------------------------------
189
  signal core_interrupt                 : std_logic;
190
  signal core_fifo_full                 : std_logic;
191
  signal core_fifo_nopush               : std_logic;
192
  signal core_ready                     : std_logic;
193
  signal core_mem_collision             : std_logic;
194
 
195
  ------------------------------------------------------------------
196
  -- Signals for multiplier core control
197
  ------------------------------------------------------------------
198
  signal core_start                     : std_logic;
199 91 JonasDC
  signal core_start_bit                 : std_logic;
200
  signal core_start_bit_d               : std_logic;
201 82 JonasDC
  signal core_exp_m                     : std_logic;
202
  signal core_p_sel                     : std_logic_vector(1 downto 0);
203
  signal core_dest_op_single            : std_logic_vector(1 downto 0);
204
  signal core_x_sel_single              : std_logic_vector(1 downto 0);
205
  signal core_y_sel_single              : std_logic_vector(1 downto 0);
206
  signal core_flags                     : std_logic_vector(15 downto 0);
207
  signal core_modulus_sel               : std_logic;
208
 
209
begin
210
  -- unused signals
211
  S_AXI_BRESP <= "00";
212
  S_AXI_RRESP <= "00";
213
 
214
  -- axi-lite slave state machine
215
  axi_slave_states : process (S_AXI_ACLK)
216
  begin
217
    if rising_edge(S_AXI_ACLK) then
218
      if S_AXI_ARESETN='0' then -- slave reset state
219
        S_AXI_RVALID <= '0';
220 84 JonasDC
        S_AXI_BVALID_i <= '0';
221 82 JonasDC
        S_AXI_ARREADY <= '0';
222
        S_AXI_WREADY <= '0';
223
        S_AXI_AWREADY <= '0';
224
        state <= addr_wait;
225
        address <= (others=>'0');
226
        write_enable <= '0';
227
      else
228
        case state is
229
          when addr_wait =>
230
          -- wait for a read or write address and latch it in
231
            if S_AXI_ARVALID = '1' then -- read
232
              state <= read_state;
233
              address <= S_AXI_ARADDR;
234
              S_AXI_ARREADY <= '1';
235 84 JonasDC
            elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then -- write
236 82 JonasDC
              state <= write_state;
237
              address <= S_AXI_AWADDR;
238
            else
239
              state <= addr_wait;
240
            end if;
241
 
242
          when read_state =>
243
          -- place correct data on bus and generate valid pulse
244
            S_AXI_ARREADY <= '0';
245
            S_AXI_RVALID <= '1';
246
            state <= response_state;
247
 
248
          when write_state =>
249
          -- generate a write pulse
250 84 JonasDC
            S_AXI_AWREADY <= '1';
251
            write_enable <= '1';
252
            S_AXI_WREADY <= '1';
253
            state <= response_state;
254 82 JonasDC
 
255
          when response_state =>
256
            write_enable <= '0';
257 84 JonasDC
            S_AXI_AWREADY <= '0';
258 82 JonasDC
            S_AXI_WREADY <= '0';
259 84 JonasDC
            S_AXI_BVALID_i <= '1';
260 82 JonasDC
          -- wait for response from master
261 84 JonasDC
            if (S_AXI_RREADY = '1') or (S_AXI_BVALID_i = '1' and S_AXI_BREADY = '1') then
262 82 JonasDC
              S_AXI_RVALID <= '0';
263 84 JonasDC
              S_AXI_BVALID_i <= '0';
264 82 JonasDC
              state <= addr_wait;
265
            else
266
              state <= response_state;
267
            end if;
268
 
269
        end case;
270
      end if;
271
    end if;
272
  end process;
273 84 JonasDC
  S_AXI_BVALID <= S_AXI_BVALID_i;
274
 
275
  -- place correct data on the read bus
276
  S_AXI_RDATA <=  slv_reg when (slv_reg_selected='1') else
277
                  core_data_out;
278 82 JonasDC
 
279
  -- SLAVE REG MAPPING
280
  -- core control signals
281 84 JonasDC
  core_p_sel <= slv_reg(31 downto 30);
282
  core_dest_op_single <= slv_reg(29 downto 28);
283
  core_x_sel_single <= slv_reg(27 downto 26);
284
  core_y_sel_single <= slv_reg(25 downto 24);
285 91 JonasDC
  core_start_bit <= slv_reg(23);
286 84 JonasDC
  core_exp_m <= slv_reg(22);
287
  core_modulus_sel <= slv_reg(21);
288
  reset <= (not S_AXI_ARESETN) or slv_reg(20);
289 82 JonasDC
 
290
  -- implement slave register
291
  SLAVE_REG_WRITE_PROC : process( S_AXI_ACLK ) is
292
  begin
293
    if rising_edge(S_AXI_ACLK) then
294 85 JonasDC
      if reset = '1' then
295 82 JonasDC
        slv_reg <= (others => '0');
296
      elsif load_flags = '1' then
297 84 JonasDC
        slv_reg <= slv_reg(31 downto 16) & core_flags;
298 82 JonasDC
      else
299
        if (slv_reg_write_enable='1') then
300
          slv_reg <= S_AXI_WDATA(31 downto 0);
301
        end if;
302
      end if;
303
    end if;
304
  end process SLAVE_REG_WRITE_PROC;
305
 
306 91 JonasDC
  -- create start pulse of 1 clk wide
307
  START_PULSE : process(S_AXI_ACLK)
308
  begin
309
    if rising_edge(S_AXI_ACLK) then
310
      core_start_bit_d <= core_start_bit;
311
    end if;
312
  end process;
313
  core_start <= core_start_bit and not core_start_bit_d;
314
 
315 82 JonasDC
  -- interrupt and flags
316
  core_interrupt <= core_ready or core_mem_collision or core_fifo_full or core_fifo_nopush;
317
 
318 86 JonasDC
  FLAGS_CNTRL_PROC : process(S_AXI_ACLK, reset) is
319 82 JonasDC
  begin
320 85 JonasDC
    if reset = '1' then
321 82 JonasDC
      core_flags <= (others => '0');
322
      load_flags <= '0';
323
    elsif rising_edge(S_AXI_ACLK) then
324 91 JonasDC
      if core_start = '1' then  -- flags get resetted when core starts new operation
325 82 JonasDC
        core_flags <= (others => '0');
326
      else
327
        if core_ready = '1' then
328
          core_flags(15) <= '1';
329
        else
330
          core_flags(15) <= core_flags(15);
331
        end if;
332
        if core_mem_collision = '1' then
333
          core_flags(14) <= '1';
334
        else
335
          core_flags(14) <= core_flags(14);
336
        end if;
337
        if core_fifo_full = '1' then
338
          core_flags(13) <= '1';
339
        else
340
          core_flags(13) <= core_flags(13);
341
        end if;
342
        if core_fifo_nopush = '1' then
343
          core_flags(12) <= '1';
344
        else
345
          core_flags(12) <= core_flags(12);
346
        end if;
347
      end if;
348
      load_flags <= core_interrupt;
349
    end if;
350
  end process FLAGS_CNTRL_PROC;
351
 
352 91 JonasDC
  IntrEvent <= core_flags(15) or core_flags(14) or core_flags(13) or core_flags(12);
353
 
354 82 JonasDC
  -- adress decoder
355
  with address(14 downto 12) select
356
    cs_array <= "0000001" when "000", -- M
357
                "0000010" when "001", -- OP0
358
                "0000100" when "010", -- OP1
359
                "0001000" when "011", -- OP2
360
                "0010000" when "100", -- OP3
361
                "0100000" when "101", -- FIFO
362
                "1000000" when "110", -- user reg space
363
                "0000000" when others;
364 84 JonasDC
 
365 82 JonasDC
  slv_reg_selected <= cs_array(6);
366
  slv_reg_write_enable <= write_enable and slv_reg_selected;
367
 
368
  -- high if memory space is selected
369
  op_mem_selected <= cs_array(0) or cs_array(1) or cs_array(2) or cs_array(3) or cs_array(4);
370
 
371
  -- operand memory singals
372
  MNO_sel <= cs_array(0);
373
 
374
  with cs_array(4 downto 1) select
375
    op_sel <=   "00" when "0001",
376
                "01" when "0010",
377
                "10" when "0100",
378
                "11" when "1000",
379
                "00" when others;
380
 
381
  core_rw_address <= MNO_sel & op_sel & address(7 downto 2);
382
 
383
  core_write_enable <= write_enable and op_mem_selected;
384
 
385
 
386
  -- FIFO signals
387
  core_fifo_push <= write_enable and cs_array(5);
388
 
389
  ------------------------------------------
390
  -- Exponentiation core instance
391
  ------------------------------------------
392
  msec: entity mod_sim_exp.mod_sim_exp_core
393
  generic map(
394
    C_NR_BITS_TOTAL   => C_NR_BITS_TOTAL,
395
    C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
396
    C_NR_STAGES_LOW   => C_NR_STAGES_LOW,
397
    C_SPLIT_PIPELINE  => C_SPLIT_PIPELINE,
398 94 JonasDC
    C_FIFO_AW         => C_FIFO_AW,
399 82 JonasDC
    C_MEM_STYLE       => C_MEM_STYLE,
400 84 JonasDC
    C_FPGA_MAN        => C_FPGA_MAN
401 82 JonasDC
  )
402
  port map(
403 94 JonasDC
    bus_clk   => S_AXI_ACLK,
404
    core_clk  => core_clk,
405
    reset     => reset,
406 82 JonasDC
      -- operand memory interface (plb shared memory)
407
    write_enable => core_write_enable,
408
    data_in      => S_AXI_WDATA(31 downto 0),
409
    rw_address   => core_rw_address,
410
    data_out     => core_data_out,
411
    collision    => core_mem_collision,
412
      -- op_sel fifo interface
413
    fifo_din    => S_AXI_WDATA(31 downto 0),
414
    fifo_push   => core_fifo_push,
415
    fifo_full   => core_fifo_full,
416
    fifo_nopush => core_fifo_nopush,
417
      -- ctrl signals
418
    start          => core_start,
419
    exp_m          => core_exp_m,
420
    ready          => core_ready,
421
    x_sel_single   => core_x_sel_single,
422
    y_sel_single   => core_y_sel_single,
423
    dest_op_single => core_dest_op_single,
424
    p_sel          => core_p_sel,
425
    calc_time      => calc_time,
426
    modulus_sel    => core_modulus_sel
427
  );
428
 
429 84 JonasDC
end IMP;

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.