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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [plb/] [mod_sim_exp_IPcore.vhd] - Blame information for rev 65

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1 44 JonasDC
------------------------------------------------------------------------------
2
-- mont_mult1536.vhd - entity/architecture pair
3
------------------------------------------------------------------------------
4
-- IMPORTANT:
5
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
6
--
7
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
8
--
9
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
10
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
11
-- OF THE USER_LOGIC ENTITY.
12
------------------------------------------------------------------------------
13
--
14
-- ***************************************************************************
15
-- ** Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.            **
16
-- **                                                                       **
17
-- ** Xilinx, Inc.                                                          **
18
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"         **
19
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND       **
20
-- ** SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,        **
21
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,        **
22
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION           **
23
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,     **
24
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE      **
25
-- ** FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY              **
26
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE               **
27
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR        **
28
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF       **
29
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS       **
30
-- ** FOR A PARTICULAR PURPOSE.                                             **
31
-- **                                                                       **
32
-- ***************************************************************************
33
--
34
------------------------------------------------------------------------------
35
-- Filename:          mont_mult1536.vhd
36
-- Version:           2.00.a
37
-- Description:       Top level design, instantiates library components and user logic.
38
-- Date:              Thu May 03 09:53:36 2012 (by Create and Import Peripheral Wizard)
39
-- VHDL Standard:     VHDL'93
40
------------------------------------------------------------------------------
41
-- Naming Conventions:
42
--   active low signals:                    "*_n"
43
--   clock signals:                         "clk", "clk_div#", "clk_#x"
44
--   reset signals:                         "rst", "rst_n"
45
--   generics:                              "C_*"
46
--   user defined types:                    "*_TYPE"
47
--   state machine next state:              "*_ns"
48
--   state machine current state:           "*_cs"
49
--   combinatorial signals:                 "*_com"
50
--   pipelined or register delay signals:   "*_d#"
51
--   counter signals:                       "*cnt*"
52
--   clock enable signals:                  "*_ce"
53
--   internal version of output port:       "*_i"
54
--   device pins:                           "*_pin"
55
--   ports:                                 "- Names begin with Uppercase"
56
--   processes:                             "*_PROCESS"
57
--   component instantiations:              "<ENTITY_>I_<#|FUNC>"
58
------------------------------------------------------------------------------
59
 
60
library ieee;
61
use ieee.std_logic_1164.all;
62
use ieee.std_logic_arith.all;
63
use ieee.std_logic_unsigned.all;
64
 
65
library proc_common_v3_00_a;
66
use proc_common_v3_00_a.proc_common_pkg.all;
67
use proc_common_v3_00_a.ipif_pkg.all;
68
use proc_common_v3_00_a.soft_reset;
69
 
70
library interrupt_control_v2_01_a;
71
use interrupt_control_v2_01_a.interrupt_control;
72
 
73
library plbv46_slave_single_v1_01_a;
74
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
75
 
76
library mod_sim_exp;
77
use mod_sim_exp.user_logic;
78
 
79
------------------------------------------------------------------------------
80
-- Entity section
81
------------------------------------------------------------------------------
82
-- Definition of Generics:
83
--   C_BASEADDR                   -- PLBv46 slave: base address
84
--   C_HIGHADDR                   -- PLBv46 slave: high address
85
--   C_SPLB_AWIDTH                -- PLBv46 slave: address bus width
86
--   C_SPLB_DWIDTH                -- PLBv46 slave: data bus width
87
--   C_SPLB_NUM_MASTERS           -- PLBv46 slave: Number of masters
88
--   C_SPLB_MID_WIDTH             -- PLBv46 slave: master ID bus width
89
--   C_SPLB_NATIVE_DWIDTH         -- PLBv46 slave: internal native data bus width
90
--   C_SPLB_P2P                   -- PLBv46 slave: point to point interconnect scheme
91
--   C_SPLB_SUPPORT_BURSTS        -- PLBv46 slave: support bursts
92
--   C_SPLB_SMALLEST_MASTER       -- PLBv46 slave: width of the smallest master
93
--   C_SPLB_CLK_PERIOD_PS         -- PLBv46 slave: bus clock in picoseconds
94
--   C_INCLUDE_DPHASE_TIMER       -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
95
--   C_FAMILY                     -- Xilinx FPGA family
96
--   C_MEM0_BASEADDR              -- User memory space 0 base address
97
--   C_MEM0_HIGHADDR              -- User memory space 0 high address
98
--   C_MEM1_BASEADDR              -- User memory space 1 base address
99
--   C_MEM1_HIGHADDR              -- User memory space 1 high address
100
--   C_MEM2_BASEADDR              -- User memory space 2 base address
101
--   C_MEM2_HIGHADDR              -- User memory space 2 high address
102
--   C_MEM3_BASEADDR              -- User memory space 3 base address
103
--   C_MEM3_HIGHADDR              -- User memory space 3 high address
104
--   C_MEM4_BASEADDR              -- User memory space 4 base address
105
--   C_MEM4_HIGHADDR              -- User memory space 4 high address
106
--   C_MEM5_BASEADDR              -- User memory space 5 base address
107
--   C_MEM5_HIGHADDR              -- User memory space 5 high address
108
--
109
-- Definition of Ports:
110
--   SPLB_Clk                     -- PLB main bus clock
111
--   SPLB_Rst                     -- PLB main bus reset
112
--   PLB_ABus                     -- PLB address bus
113
--   PLB_UABus                    -- PLB upper address bus
114
--   PLB_PAValid                  -- PLB primary address valid indicator
115
--   PLB_SAValid                  -- PLB secondary address valid indicator
116
--   PLB_rdPrim                   -- PLB secondary to primary read request indicator
117
--   PLB_wrPrim                   -- PLB secondary to primary write request indicator
118
--   PLB_masterID                 -- PLB current master identifier
119
--   PLB_abort                    -- PLB abort request indicator
120
--   PLB_busLock                  -- PLB bus lock
121
--   PLB_RNW                      -- PLB read/not write
122
--   PLB_BE                       -- PLB byte enables
123
--   PLB_MSize                    -- PLB master data bus size
124
--   PLB_size                     -- PLB transfer size
125
--   PLB_type                     -- PLB transfer type
126
--   PLB_lockErr                  -- PLB lock error indicator
127
--   PLB_wrDBus                   -- PLB write data bus
128
--   PLB_wrBurst                  -- PLB burst write transfer indicator
129
--   PLB_rdBurst                  -- PLB burst read transfer indicator
130
--   PLB_wrPendReq                -- PLB write pending bus request indicator
131
--   PLB_rdPendReq                -- PLB read pending bus request indicator
132
--   PLB_wrPendPri                -- PLB write pending request priority
133
--   PLB_rdPendPri                -- PLB read pending request priority
134
--   PLB_reqPri                   -- PLB current request priority
135
--   PLB_TAttribute               -- PLB transfer attribute
136
--   Sl_addrAck                   -- Slave address acknowledge
137
--   Sl_SSize                     -- Slave data bus size
138
--   Sl_wait                      -- Slave wait indicator
139
--   Sl_rearbitrate               -- Slave re-arbitrate bus indicator
140
--   Sl_wrDAck                    -- Slave write data acknowledge
141
--   Sl_wrComp                    -- Slave write transfer complete indicator
142
--   Sl_wrBTerm                   -- Slave terminate write burst transfer
143
--   Sl_rdDBus                    -- Slave read data bus
144
--   Sl_rdWdAddr                  -- Slave read word address
145
--   Sl_rdDAck                    -- Slave read data acknowledge
146
--   Sl_rdComp                    -- Slave read transfer complete indicator
147
--   Sl_rdBTerm                   -- Slave terminate read burst transfer
148
--   Sl_MBusy                     -- Slave busy indicator
149
--   Sl_MWrErr                    -- Slave write error indicator
150
--   Sl_MRdErr                    -- Slave read error indicator
151
--   Sl_MIRQ                      -- Slave interrupt indicator
152
--   IP2INTC_Irpt                 -- Interrupt output to processor
153
------------------------------------------------------------------------------
154
 
155
entity mod_sim_exp_IPcore is
156
  generic
157
  (
158
    -- ADD USER GENERICS BELOW THIS LINE ---------------
159
    --USER generics added here
160
    -- Multiplier parameters
161
    C_NR_BITS_TOTAL   : integer := 1536;
162
    C_NR_STAGES_TOTAL : integer := 96;
163
    C_NR_STAGES_LOW   : integer := 32;
164
    C_SPLIT_PIPELINE  : boolean := true;
165 65 JonasDC
    C_FIFO_DEPTH      : integer := 32;
166 44 JonasDC
    -- ADD USER GENERICS ABOVE THIS LINE ---------------
167
 
168
    -- DO NOT EDIT BELOW THIS LINE ---------------------
169
    -- Bus protocol parameters, do not add to or delete
170
    C_BASEADDR                     : std_logic_vector     := X"FFFFFFFF";
171
    C_HIGHADDR                     : std_logic_vector     := X"00000000";
172
    C_SPLB_AWIDTH                  : integer              := 32;
173
    C_SPLB_DWIDTH                  : integer              := 128;
174
    C_SPLB_NUM_MASTERS             : integer              := 8;
175
    C_SPLB_MID_WIDTH               : integer              := 3;
176
    C_SPLB_NATIVE_DWIDTH           : integer              := 32;
177
    C_SPLB_P2P                     : integer              := 0;
178
    C_SPLB_SUPPORT_BURSTS          : integer              := 0;
179
    C_SPLB_SMALLEST_MASTER         : integer              := 32;
180
    C_SPLB_CLK_PERIOD_PS           : integer              := 10000;
181
    C_INCLUDE_DPHASE_TIMER         : integer              := 0;
182
    C_FAMILY                       : string               := "virtex5";
183
    C_M_BASEADDR                   : std_logic_vector     := X"FFFFFFFF";
184
    C_M_HIGHADDR                   : std_logic_vector     := X"00000000";
185
    C_OP0_BASEADDR                 : std_logic_vector     := X"FFFFFFFF";
186
    C_OP0_HIGHADDR                 : std_logic_vector     := X"00000000";
187
    C_OP1_BASEADDR                 : std_logic_vector     := X"FFFFFFFF";
188
    C_OP1_HIGHADDR                 : std_logic_vector     := X"00000000";
189
    C_OP2_BASEADDR                 : std_logic_vector     := X"FFFFFFFF";
190
    C_OP2_HIGHADDR                 : std_logic_vector     := X"00000000";
191
    C_OP3_BASEADDR                 : std_logic_vector     := X"FFFFFFFF";
192
    C_OP3_HIGHADDR                 : std_logic_vector     := X"00000000";
193
    C_FIFO_BASEADDR                : std_logic_vector     := X"FFFFFFFF";
194
    C_FIFO_HIGHADDR                : std_logic_vector     := X"00000000"
195
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
196
  );
197
  port
198
  (
199
    -- ADD USER PORTS BELOW THIS LINE ------------------
200
    --USER ports added here
201
   calc_time                      : out std_logic;
202
    -- ADD USER PORTS ABOVE THIS LINE ------------------
203
 
204
    -- DO NOT EDIT BELOW THIS LINE ---------------------
205
    -- Bus protocol ports, do not add to or delete
206
    SPLB_Clk                       : in  std_logic;
207
    SPLB_Rst                       : in  std_logic;
208
    PLB_ABus                       : in  std_logic_vector(0 to 31);
209
    PLB_UABus                      : in  std_logic_vector(0 to 31);
210
    PLB_PAValid                    : in  std_logic;
211
    PLB_SAValid                    : in  std_logic;
212
    PLB_rdPrim                     : in  std_logic;
213
    PLB_wrPrim                     : in  std_logic;
214
    PLB_masterID                   : in  std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
215
    PLB_abort                      : in  std_logic;
216
    PLB_busLock                    : in  std_logic;
217
    PLB_RNW                        : in  std_logic;
218
    PLB_BE                         : in  std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
219
    PLB_MSize                      : in  std_logic_vector(0 to 1);
220
    PLB_size                       : in  std_logic_vector(0 to 3);
221
    PLB_type                       : in  std_logic_vector(0 to 2);
222
    PLB_lockErr                    : in  std_logic;
223
    PLB_wrDBus                     : in  std_logic_vector(0 to C_SPLB_DWIDTH-1);
224
    PLB_wrBurst                    : in  std_logic;
225
    PLB_rdBurst                    : in  std_logic;
226
    PLB_wrPendReq                  : in  std_logic;
227
    PLB_rdPendReq                  : in  std_logic;
228
    PLB_wrPendPri                  : in  std_logic_vector(0 to 1);
229
    PLB_rdPendPri                  : in  std_logic_vector(0 to 1);
230
    PLB_reqPri                     : in  std_logic_vector(0 to 1);
231
    PLB_TAttribute                 : in  std_logic_vector(0 to 15);
232
    Sl_addrAck                     : out std_logic;
233
    Sl_SSize                       : out std_logic_vector(0 to 1);
234
    Sl_wait                        : out std_logic;
235
    Sl_rearbitrate                 : out std_logic;
236
    Sl_wrDAck                      : out std_logic;
237
    Sl_wrComp                      : out std_logic;
238
    Sl_wrBTerm                     : out std_logic;
239
    Sl_rdDBus                      : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
240
    Sl_rdWdAddr                    : out std_logic_vector(0 to 3);
241
    Sl_rdDAck                      : out std_logic;
242
    Sl_rdComp                      : out std_logic;
243
    Sl_rdBTerm                     : out std_logic;
244
    Sl_MBusy                       : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
245
    Sl_MWrErr                      : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
246
    Sl_MRdErr                      : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
247
    Sl_MIRQ                        : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
248
    IP2INTC_Irpt                   : out std_logic
249
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
250
  );
251
 
252
  attribute SIGIS : string;
253
  attribute SIGIS of SPLB_Clk      : signal is "CLK";
254
  attribute SIGIS of SPLB_Rst      : signal is "RST";
255
  attribute SIGIS of IP2INTC_Irpt  : signal is "INTR_LEVEL_HIGH";
256
 
257
end entity mod_sim_exp_IPcore;
258
 
259
------------------------------------------------------------------------------
260
-- Architecture section
261
------------------------------------------------------------------------------
262
 
263
architecture IMP of mod_sim_exp_IPcore is
264
 
265
  ------------------------------------------
266
  -- Array of base/high address pairs for each address range
267
  ------------------------------------------
268
  constant ZERO_ADDR_PAD                  : std_logic_vector(0 to 31) := (others => '0');
269
  constant USER_SLV_BASEADDR              : std_logic_vector     := C_BASEADDR or X"00000000";
270
  constant USER_SLV_HIGHADDR              : std_logic_vector     := C_BASEADDR or X"000000FF";
271
  constant RST_BASEADDR                   : std_logic_vector     := C_BASEADDR or X"00000100";
272
  constant RST_HIGHADDR                   : std_logic_vector     := C_BASEADDR or X"000001FF";
273
  constant INTR_BASEADDR                  : std_logic_vector     := C_BASEADDR or X"00000200";
274
  constant INTR_HIGHADDR                  : std_logic_vector     := C_BASEADDR or X"000002FF";
275
 
276
  constant IPIF_ARD_ADDR_RANGE_ARRAY      : SLV64_ARRAY_TYPE     :=
277
    (
278
      ZERO_ADDR_PAD & USER_SLV_BASEADDR,  -- user logic slave space base address
279
      ZERO_ADDR_PAD & USER_SLV_HIGHADDR,  -- user logic slave space high address
280
      ZERO_ADDR_PAD & RST_BASEADDR,       -- soft reset space base address
281
      ZERO_ADDR_PAD & RST_HIGHADDR,       -- soft reset space high address
282
      ZERO_ADDR_PAD & INTR_BASEADDR,      -- interrupt control space base address
283
      ZERO_ADDR_PAD & INTR_HIGHADDR,      -- interrupt control space high address
284
      ZERO_ADDR_PAD & C_M_BASEADDR,    -- user logic memory space 0 base address
285
      ZERO_ADDR_PAD & C_M_HIGHADDR,    -- user logic memory space 0 high address
286
      ZERO_ADDR_PAD & C_OP0_BASEADDR,    -- user logic memory space 1 base address
287
      ZERO_ADDR_PAD & C_OP0_HIGHADDR,    -- user logic memory space 1 high address
288
      ZERO_ADDR_PAD & C_OP1_BASEADDR,    -- user logic memory space 2 base address
289
      ZERO_ADDR_PAD & C_OP1_HIGHADDR,    -- user logic memory space 2 high address
290
      ZERO_ADDR_PAD & C_OP2_BASEADDR,    -- user logic memory space 3 base address
291
      ZERO_ADDR_PAD & C_OP2_HIGHADDR,    -- user logic memory space 3 high address
292
      ZERO_ADDR_PAD & C_OP3_BASEADDR,    -- user logic memory space 4 base address
293
      ZERO_ADDR_PAD & C_OP3_HIGHADDR,    -- user logic memory space 4 high address
294
      ZERO_ADDR_PAD & C_FIFO_BASEADDR,    -- user logic memory space 5 base address
295
      ZERO_ADDR_PAD & C_FIFO_HIGHADDR     -- user logic memory space 5 high address
296
    );
297
 
298
  ------------------------------------------
299
  -- Array of desired number of chip enables for each address range
300
  ------------------------------------------
301
  constant USER_SLV_NUM_REG               : integer              := 1;
302
  constant USER_NUM_REG                   : integer              := USER_SLV_NUM_REG;
303
  constant RST_NUM_CE                     : integer              := 1;
304
  constant INTR_NUM_CE                    : integer              := 16;
305
  constant USER_NUM_MEM                   : integer              := 6;
306
 
307
  constant IPIF_ARD_NUM_CE_ARRAY          : INTEGER_ARRAY_TYPE   :=
308
    (
309
 
310
      1  => RST_NUM_CE,                   -- number of ce for soft reset space
311
      2  => INTR_NUM_CE,                  -- number of ce for interrupt control space
312
      3  => 1,                            -- number of ce for user logic memory space 0 (always 1 chip enable)
313
      4  => 1,                            -- number of ce for user logic memory space 1 (always 1 chip enable)
314
      5  => 1,                            -- number of ce for user logic memory space 2 (always 1 chip enable)
315
      6  => 1,                            -- number of ce for user logic memory space 3 (always 1 chip enable)
316
      7  => 1,                            -- number of ce for user logic memory space 4 (always 1 chip enable)
317
      8  => 1                             -- number of ce for user logic memory space 5 (always 1 chip enable)
318
    );
319
 
320
  ------------------------------------------
321
  -- Ratio of bus clock to core clock (for use in dual clock systems)
322
  -- 1 = ratio is 1:1
323
  -- 2 = ratio is 2:1
324
  ------------------------------------------
325
  constant IPIF_BUS2CORE_CLK_RATIO        : integer              := 1;
326
 
327
  ------------------------------------------
328
  -- Width of the slave data bus (32 only)
329
  ------------------------------------------
330
  constant USER_SLV_DWIDTH                : integer              := C_SPLB_NATIVE_DWIDTH;
331
 
332
  constant IPIF_SLV_DWIDTH                : integer              := C_SPLB_NATIVE_DWIDTH;
333
 
334
  ------------------------------------------
335
  -- Width of triggered reset in bus clocks
336
  ------------------------------------------
337
  constant RESET_WIDTH                    : integer              := 4;
338
 
339
  ------------------------------------------
340
  -- Number of device level interrupts
341
  ------------------------------------------
342
  constant INTR_NUM_IPIF_IRPT_SRC         : integer              := 4;
343
 
344
  ------------------------------------------
345
  -- Capture mode for each IP interrupt (generated by user logic)
346
  -- 1 = pass through (non-inverting)
347
  -- 2 = pass through (inverting)
348
  -- 3 = registered level (non-inverting)
349
  -- 4 = registered level (inverting)
350
  -- 5 = positive edge detect
351
  -- 6 = negative edge detect
352
  ------------------------------------------
353
  constant USER_NUM_INTR                  : integer              := 1;
354
  constant USER_INTR_CAPTURE_MODE         : integer              := 1;
355
 
356
  constant INTR_IP_INTR_MODE_ARRAY        : INTEGER_ARRAY_TYPE   :=
357
    (
358
 
359
    );
360
 
361
  ------------------------------------------
362
  -- Device priority encoder feature inclusion/omission
363
  -- true  = include priority encoder
364
  -- false = omit priority encoder
365
  ------------------------------------------
366
  constant INTR_INCLUDE_DEV_PENCODER      : boolean              := false;
367
 
368
  ------------------------------------------
369
  -- Device ISC feature inclusion/omission
370
  -- true  = include device ISC
371
  -- false = omit device ISC
372
  ------------------------------------------
373
  constant INTR_INCLUDE_DEV_ISC           : boolean              := false;
374
 
375
  ------------------------------------------
376
  -- Width of the slave address bus (32 only)
377
  ------------------------------------------
378
  constant USER_SLV_AWIDTH                : integer              := C_SPLB_AWIDTH;
379
 
380
  ------------------------------------------
381
  -- Index for CS/CE
382
  ------------------------------------------
383
  constant USER_SLV_CS_INDEX              : integer              := 0;
384
  constant USER_SLV_CE_INDEX              : integer              := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
385
  constant RST_CS_INDEX                   : integer              := 1;
386
  constant RST_CE_INDEX                   : integer              := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, RST_CS_INDEX);
387
  constant INTR_CS_INDEX                  : integer              := 2;
388
  constant INTR_CE_INDEX                  : integer              := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, INTR_CS_INDEX);
389
  constant USER_MEM0_CS_INDEX             : integer              := 3;
390
  constant USER_CS_INDEX                  : integer              := USER_MEM0_CS_INDEX;
391
 
392
  constant USER_CE_INDEX                  : integer              := USER_SLV_CE_INDEX;
393
 
394
  ------------------------------------------
395
  -- IP Interconnect (IPIC) signal declarations
396
  ------------------------------------------
397
  signal ipif_Bus2IP_Clk                : std_logic;
398
  signal ipif_Bus2IP_Reset              : std_logic;
399
  signal ipif_IP2Bus_Data               : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
400
  signal ipif_IP2Bus_WrAck              : std_logic;
401
  signal ipif_IP2Bus_RdAck              : std_logic;
402
  signal ipif_IP2Bus_Error              : std_logic;
403
  signal ipif_Bus2IP_Addr               : std_logic_vector(0 to C_SPLB_AWIDTH-1);
404
  signal ipif_Bus2IP_Data               : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
405
  signal ipif_Bus2IP_RNW                : std_logic;
406
  signal ipif_Bus2IP_BE                 : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
407
  signal ipif_Bus2IP_CS                 : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
408
  signal ipif_Bus2IP_RdCE               : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
409
  signal ipif_Bus2IP_WrCE               : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
410
  signal rst_Bus2IP_Reset               : std_logic;
411
  signal rst_IP2Bus_WrAck               : std_logic;
412
  signal rst_IP2Bus_Error               : std_logic;
413
  signal intr_IPIF_Reg_Interrupts       : std_logic_vector(0 to 1);
414
  signal intr_IPIF_Lvl_Interrupts       : std_logic_vector(0 to INTR_NUM_IPIF_IRPT_SRC-1);
415
  signal intr_IP2Bus_Data               : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
416
  signal intr_IP2Bus_WrAck              : std_logic;
417
  signal intr_IP2Bus_RdAck              : std_logic;
418
  signal intr_IP2Bus_Error              : std_logic;
419
  signal user_Bus2IP_RdCE               : std_logic_vector(0 to USER_NUM_REG-1);
420
  signal user_Bus2IP_WrCE               : std_logic_vector(0 to USER_NUM_REG-1);
421
  signal user_IP2Bus_Data               : std_logic_vector(0 to USER_SLV_DWIDTH-1);
422
  signal user_IP2Bus_RdAck              : std_logic;
423
  signal user_IP2Bus_WrAck              : std_logic;
424
  signal user_IP2Bus_Error              : std_logic;
425
  signal user_IP2Bus_IntrEvent          : std_logic_vector(0 to USER_NUM_INTR-1);
426
 
427
begin
428
 
429
  ------------------------------------------
430
  -- instantiate plbv46_slave_single
431
  ------------------------------------------
432
  PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
433
    generic map
434
    (
435
      C_ARD_ADDR_RANGE_ARRAY         => IPIF_ARD_ADDR_RANGE_ARRAY,
436
      C_ARD_NUM_CE_ARRAY             => IPIF_ARD_NUM_CE_ARRAY,
437
      C_SPLB_P2P                     => C_SPLB_P2P,
438
      C_BUS2CORE_CLK_RATIO           => IPIF_BUS2CORE_CLK_RATIO,
439
      C_SPLB_MID_WIDTH               => C_SPLB_MID_WIDTH,
440
      C_SPLB_NUM_MASTERS             => C_SPLB_NUM_MASTERS,
441
      C_SPLB_AWIDTH                  => C_SPLB_AWIDTH,
442
      C_SPLB_DWIDTH                  => C_SPLB_DWIDTH,
443
      C_SIPIF_DWIDTH                 => IPIF_SLV_DWIDTH,
444
      C_INCLUDE_DPHASE_TIMER         => C_INCLUDE_DPHASE_TIMER,
445
      C_FAMILY                       => C_FAMILY
446
    )
447
    port map
448
    (
449
      SPLB_Clk                       => SPLB_Clk,
450
      SPLB_Rst                       => SPLB_Rst,
451
      PLB_ABus                       => PLB_ABus,
452
      PLB_UABus                      => PLB_UABus,
453
      PLB_PAValid                    => PLB_PAValid,
454
      PLB_SAValid                    => PLB_SAValid,
455
      PLB_rdPrim                     => PLB_rdPrim,
456
      PLB_wrPrim                     => PLB_wrPrim,
457
      PLB_masterID                   => PLB_masterID,
458
      PLB_abort                      => PLB_abort,
459
      PLB_busLock                    => PLB_busLock,
460
      PLB_RNW                        => PLB_RNW,
461
      PLB_BE                         => PLB_BE,
462
      PLB_MSize                      => PLB_MSize,
463
      PLB_size                       => PLB_size,
464
      PLB_type                       => PLB_type,
465
      PLB_lockErr                    => PLB_lockErr,
466
      PLB_wrDBus                     => PLB_wrDBus,
467
      PLB_wrBurst                    => PLB_wrBurst,
468
      PLB_rdBurst                    => PLB_rdBurst,
469
      PLB_wrPendReq                  => PLB_wrPendReq,
470
      PLB_rdPendReq                  => PLB_rdPendReq,
471
      PLB_wrPendPri                  => PLB_wrPendPri,
472
      PLB_rdPendPri                  => PLB_rdPendPri,
473
      PLB_reqPri                     => PLB_reqPri,
474
      PLB_TAttribute                 => PLB_TAttribute,
475
      Sl_addrAck                     => Sl_addrAck,
476
      Sl_SSize                       => Sl_SSize,
477
      Sl_wait                        => Sl_wait,
478
      Sl_rearbitrate                 => Sl_rearbitrate,
479
      Sl_wrDAck                      => Sl_wrDAck,
480
      Sl_wrComp                      => Sl_wrComp,
481
      Sl_wrBTerm                     => Sl_wrBTerm,
482
      Sl_rdDBus                      => Sl_rdDBus,
483
      Sl_rdWdAddr                    => Sl_rdWdAddr,
484
      Sl_rdDAck                      => Sl_rdDAck,
485
      Sl_rdComp                      => Sl_rdComp,
486
      Sl_rdBTerm                     => Sl_rdBTerm,
487
      Sl_MBusy                       => Sl_MBusy,
488
      Sl_MWrErr                      => Sl_MWrErr,
489
      Sl_MRdErr                      => Sl_MRdErr,
490
      Sl_MIRQ                        => Sl_MIRQ,
491
      Bus2IP_Clk                     => ipif_Bus2IP_Clk,
492
      Bus2IP_Reset                   => ipif_Bus2IP_Reset,
493
      IP2Bus_Data                    => ipif_IP2Bus_Data,
494
      IP2Bus_WrAck                   => ipif_IP2Bus_WrAck,
495
      IP2Bus_RdAck                   => ipif_IP2Bus_RdAck,
496
      IP2Bus_Error                   => ipif_IP2Bus_Error,
497
      Bus2IP_Addr                    => ipif_Bus2IP_Addr,
498
      Bus2IP_Data                    => ipif_Bus2IP_Data,
499
      Bus2IP_RNW                     => ipif_Bus2IP_RNW,
500
      Bus2IP_BE                      => ipif_Bus2IP_BE,
501
      Bus2IP_CS                      => ipif_Bus2IP_CS,
502
      Bus2IP_RdCE                    => ipif_Bus2IP_RdCE,
503
      Bus2IP_WrCE                    => ipif_Bus2IP_WrCE
504
    );
505
 
506
  ------------------------------------------
507
  -- instantiate soft_reset
508
  ------------------------------------------
509
  SOFT_RESET_I : entity proc_common_v3_00_a.soft_reset
510
    generic map
511
    (
512
      C_SIPIF_DWIDTH                 => IPIF_SLV_DWIDTH,
513
      C_RESET_WIDTH                  => RESET_WIDTH
514
    )
515
    port map
516
    (
517
      Bus2IP_Reset                   => ipif_Bus2IP_Reset,
518
      Bus2IP_Clk                     => ipif_Bus2IP_Clk,
519
      Bus2IP_WrCE                    => ipif_Bus2IP_WrCE(RST_CE_INDEX),
520
      Bus2IP_Data                    => ipif_Bus2IP_Data,
521
      Bus2IP_BE                      => ipif_Bus2IP_BE,
522
      Reset2IP_Reset                 => rst_Bus2IP_Reset,
523
      Reset2Bus_WrAck                => rst_IP2Bus_WrAck,
524
      Reset2Bus_Error                => rst_IP2Bus_Error,
525
      Reset2Bus_ToutSup              => open
526
    );
527
 
528
  ------------------------------------------
529
  -- instantiate interrupt_control
530
  ------------------------------------------
531
  INTERRUPT_CONTROL_I : entity interrupt_control_v2_01_a.interrupt_control
532
    generic map
533
    (
534
      C_NUM_CE                       => INTR_NUM_CE,
535
      C_NUM_IPIF_IRPT_SRC            => INTR_NUM_IPIF_IRPT_SRC,
536
      C_IP_INTR_MODE_ARRAY           => INTR_IP_INTR_MODE_ARRAY,
537
      C_INCLUDE_DEV_PENCODER         => INTR_INCLUDE_DEV_PENCODER,
538
      C_INCLUDE_DEV_ISC              => INTR_INCLUDE_DEV_ISC,
539
      C_IPIF_DWIDTH                  => IPIF_SLV_DWIDTH
540
    )
541
    port map
542
    (
543
      Bus2IP_Clk                     => ipif_Bus2IP_Clk,
544
      Bus2IP_Reset                   => rst_Bus2IP_Reset,
545
      Bus2IP_Data                    => ipif_Bus2IP_Data,
546
      Bus2IP_BE                      => ipif_Bus2IP_BE,
547
      Interrupt_RdCE                 => ipif_Bus2IP_RdCE(INTR_CE_INDEX to INTR_CE_INDEX+INTR_NUM_CE-1),
548
      Interrupt_WrCE                 => ipif_Bus2IP_WrCE(INTR_CE_INDEX to INTR_CE_INDEX+INTR_NUM_CE-1),
549
      IPIF_Reg_Interrupts            => intr_IPIF_Reg_Interrupts,
550
      IPIF_Lvl_Interrupts            => intr_IPIF_Lvl_Interrupts,
551
      IP2Bus_IntrEvent               => user_IP2Bus_IntrEvent,
552
      Intr2Bus_DevIntr               => IP2INTC_Irpt,
553
      Intr2Bus_DBus                  => intr_IP2Bus_Data,
554
      Intr2Bus_WrAck                 => intr_IP2Bus_WrAck,
555
      Intr2Bus_RdAck                 => intr_IP2Bus_RdAck,
556
      Intr2Bus_Error                 => intr_IP2Bus_Error,
557
      Intr2Bus_Retry                 => open,
558
      Intr2Bus_ToutSup               => open
559
    );
560
 
561
  -- feed registered and level-pass-through interrupts into Device ISC if exists, otherwise ignored
562
  intr_IPIF_Reg_Interrupts(0) <= '0';
563
  intr_IPIF_Reg_Interrupts(1) <= '0';
564
  intr_IPIF_Lvl_Interrupts(0) <= '0';
565
  intr_IPIF_Lvl_Interrupts(1) <= '0';
566
  intr_IPIF_Lvl_Interrupts(2) <= '0';
567
  intr_IPIF_Lvl_Interrupts(3) <= '0';
568
 
569
  ------------------------------------------
570
  -- instantiate User Logic
571
  ------------------------------------------
572
  USER_LOGIC_I : entity mod_sim_exp.user_logic
573
    generic map
574
    (
575
      -- MAP USER GENERICS BELOW THIS LINE ---------------
576
      -- Multiplier parameters
577
      C_NR_BITS_TOTAL   => C_NR_BITS_TOTAL,
578
      C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
579
      C_NR_STAGES_LOW   => C_NR_STAGES_LOW,
580
      C_SPLIT_PIPELINE  => C_SPLIT_PIPELINE,
581 65 JonasDC
      C_FIFO_DEPTH      => C_FIFO_DEPTH,
582 44 JonasDC
      -- MAP USER GENERICS ABOVE THIS LINE ---------------
583
 
584
      C_SLV_AWIDTH                   => USER_SLV_AWIDTH,
585
      C_SLV_DWIDTH                   => USER_SLV_DWIDTH,
586
      C_NUM_REG                      => USER_NUM_REG,
587
      C_NUM_MEM                      => USER_NUM_MEM,
588
      C_NUM_INTR                     => USER_NUM_INTR
589
    )
590
    port map
591
    (
592
      -- MAP USER PORTS BELOW THIS LINE ------------------
593
      --USER ports mapped here
594
    calc_time                      => calc_time,
595
      -- MAP USER PORTS ABOVE THIS LINE ------------------
596
 
597
      Bus2IP_Clk                     => ipif_Bus2IP_Clk,
598
      Bus2IP_Reset                   => rst_Bus2IP_Reset,
599
      Bus2IP_Addr                    => ipif_Bus2IP_Addr,
600
      Bus2IP_CS                      => ipif_Bus2IP_CS(USER_CS_INDEX to USER_CS_INDEX+USER_NUM_MEM-1),
601
      Bus2IP_RNW                     => ipif_Bus2IP_RNW,
602
      Bus2IP_Data                    => ipif_Bus2IP_Data,
603
      Bus2IP_BE                      => ipif_Bus2IP_BE,
604
      Bus2IP_RdCE                    => user_Bus2IP_RdCE,
605
      Bus2IP_WrCE                    => user_Bus2IP_WrCE,
606
      IP2Bus_Data                    => user_IP2Bus_Data,
607
      IP2Bus_RdAck                   => user_IP2Bus_RdAck,
608
      IP2Bus_WrAck                   => user_IP2Bus_WrAck,
609
      IP2Bus_Error                   => user_IP2Bus_Error,
610
      IP2Bus_IntrEvent               => user_IP2Bus_IntrEvent
611
    );
612
 
613
  ------------------------------------------
614
  -- connect internal signals
615
  ------------------------------------------
616
  IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data, intr_IP2Bus_Data ) is
617
  begin
618
 
619
    case ipif_Bus2IP_CS is
620
      when "100000000" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
621
      when "010000000" => ipif_IP2Bus_Data <= (others => '0');
622
      when "001000000" => ipif_IP2Bus_Data <= intr_IP2Bus_Data;
623
      when "000100000" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
624
      when "000010000" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
625
      when "000001000" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
626
      when "000000100" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
627
      when "000000010" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
628
      when "000000001" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
629
      when others => ipif_IP2Bus_Data <= (others => '0');
630
    end case;
631
 
632
  end process IP2BUS_DATA_MUX_PROC;
633
 
634
  ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or rst_IP2Bus_WrAck or intr_IP2Bus_WrAck;
635
  ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck or intr_IP2Bus_RdAck;
636
  ipif_IP2Bus_Error <= user_IP2Bus_Error or rst_IP2Bus_Error or intr_IP2Bus_Error;
637
 
638
  user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
639
  user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
640
 
641
end IMP;

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