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1 2 JonasDC
------------------------------------------------------------------------------
2
-- user_logic.vhd - entity/architecture pair
3
------------------------------------------------------------------------------
4
--
5
-- ***************************************************************************
6
-- ** Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.            **
7
-- **                                                                       **
8
-- ** Xilinx, Inc.                                                          **
9
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"         **
10
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND       **
11
-- ** SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,        **
12
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,        **
13
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION           **
14
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,     **
15
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE      **
16
-- ** FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY              **
17
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE               **
18
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR        **
19
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF       **
20
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS       **
21
-- ** FOR A PARTICULAR PURPOSE.                                             **
22
-- **                                                                       **
23
-- ***************************************************************************
24
--
25
------------------------------------------------------------------------------
26
-- Filename:          user_logic.vhd
27
-- Version:           2.00.a
28
-- Description:       User logic.
29
-- Date:              Thu May 03 09:53:36 2012 (by Create and Import Peripheral Wizard)
30
-- VHDL Standard:     VHDL'93
31
------------------------------------------------------------------------------
32
-- Naming Conventions:
33
--   active low signals:                    "*_n"
34
--   clock signals:                         "clk", "clk_div#", "clk_#x"
35
--   reset signals:                         "rst", "rst_n"
36
--   generics:                              "C_*"
37
--   user defined types:                    "*_TYPE"
38
--   state machine next state:              "*_ns"
39
--   state machine current state:           "*_cs"
40
--   combinatorial signals:                 "*_com"
41
--   pipelined or register delay signals:   "*_d#"
42
--   counter signals:                       "*cnt*"
43
--   clock enable signals:                  "*_ce"
44
--   internal version of output port:       "*_i"
45
--   device pins:                           "*_pin"
46
--   ports:                                 "- Names begin with Uppercase"
47
--   processes:                             "*_PROCESS"
48
--   component instantiations:              "<ENTITY_>I_<#|FUNC>"
49
------------------------------------------------------------------------------
50
 
51
-- DO NOT EDIT BELOW THIS LINE --------------------
52
library ieee;
53
use ieee.std_logic_1164.all;
54
use ieee.std_logic_arith.all;
55
use ieee.std_logic_unsigned.all;
56
 
57
library proc_common_v3_00_a;
58
use proc_common_v3_00_a.proc_common_pkg.all;
59
 
60
-- DO NOT EDIT ABOVE THIS LINE --------------------
61
 
62
--USER libraries added here
63 40 JonasDC
library mod_sim_exp;
64 42 JonasDC
use mod_sim_exp.mod_sim_exp_pkg.all;
65 2 JonasDC
 
66
------------------------------------------------------------------------------
67
-- Entity section
68
------------------------------------------------------------------------------
69
-- Definition of Generics:
70
--   C_SLV_AWIDTH                 -- Slave interface address bus width
71
--   C_SLV_DWIDTH                 -- Slave interface data bus width
72
--   C_NUM_REG                    -- Number of software accessible registers
73
--   C_NUM_MEM                    -- Number of memory spaces
74
--   C_NUM_INTR                   -- Number of interrupt event
75
--
76
-- Definition of Ports:
77
--   Bus2IP_Clk                   -- Bus to IP clock
78
--   Bus2IP_Reset                 -- Bus to IP reset
79
--   Bus2IP_Addr                  -- Bus to IP address bus
80
--   Bus2IP_CS                    -- Bus to IP chip select for user logic memory selection
81
--   Bus2IP_RNW                   -- Bus to IP read/not write
82
--   Bus2IP_Data                  -- Bus to IP data bus
83
--   Bus2IP_BE                    -- Bus to IP byte enables
84
--   Bus2IP_RdCE                  -- Bus to IP read chip enable
85
--   Bus2IP_WrCE                  -- Bus to IP write chip enable
86
--   IP2Bus_Data                  -- IP to Bus data bus
87
--   IP2Bus_RdAck                 -- IP to Bus read transfer acknowledgement
88
--   IP2Bus_WrAck                 -- IP to Bus write transfer acknowledgement
89
--   IP2Bus_Error                 -- IP to Bus error response
90
--   IP2Bus_IntrEvent             -- IP to Bus interrupt event
91
------------------------------------------------------------------------------
92
 
93
entity user_logic is
94
  generic
95
  (
96
    -- ADD USER GENERICS BELOW THIS LINE ---------------
97
    --USER generics added here
98 43 JonasDC
    -- Multiplier parameters
99
    C_NR_BITS_TOTAL   : integer := 1536;
100
    C_NR_STAGES_TOTAL : integer := 96;
101
    C_NR_STAGES_LOW   : integer := 32;
102
    C_SPLIT_PIPELINE  : boolean := true;
103 2 JonasDC
    -- ADD USER GENERICS ABOVE THIS LINE ---------------
104
 
105
    -- DO NOT EDIT BELOW THIS LINE ---------------------
106
    -- Bus protocol parameters, do not add to or delete
107
    C_SLV_AWIDTH                   : integer              := 32;
108
    C_SLV_DWIDTH                   : integer              := 32;
109
    C_NUM_REG                      : integer              := 1;
110
    C_NUM_MEM                      : integer              := 6;
111
    C_NUM_INTR                     : integer              := 1
112
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
113
  );
114
  port
115
  (
116
    -- ADD USER PORTS BELOW THIS LINE ------------------
117
    --USER ports added here
118
         calc_time                      : out std_logic;
119
        -- ctrl_sigs                      : out std_logic_vector( downto );
120
    -- ADD USER PORTS ABOVE THIS LINE ------------------
121
 
122
    -- DO NOT EDIT BELOW THIS LINE ---------------------
123
    -- Bus protocol ports, do not add to or delete
124
    Bus2IP_Clk                     : in  std_logic;
125
    Bus2IP_Reset                   : in  std_logic;
126
    Bus2IP_Addr                    : in  std_logic_vector(0 to C_SLV_AWIDTH-1);
127
    Bus2IP_CS                      : in  std_logic_vector(0 to C_NUM_MEM-1);
128
    Bus2IP_RNW                     : in  std_logic;
129
    Bus2IP_Data                    : in  std_logic_vector(0 to C_SLV_DWIDTH-1);
130
    Bus2IP_BE                      : in  std_logic_vector(0 to C_SLV_DWIDTH/8-1);
131
    Bus2IP_RdCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
132
    Bus2IP_WrCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
133
    IP2Bus_Data                    : out std_logic_vector(0 to C_SLV_DWIDTH-1);
134
    IP2Bus_RdAck                   : out std_logic;
135
    IP2Bus_WrAck                   : out std_logic;
136
    IP2Bus_Error                   : out std_logic;
137
    IP2Bus_IntrEvent               : out std_logic_vector(0 to C_NUM_INTR-1)
138
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
139
  );
140
 
141
  attribute SIGIS : string;
142
  attribute SIGIS of Bus2IP_Clk    : signal is "CLK";
143
  attribute SIGIS of Bus2IP_Reset  : signal is "RST";
144
 
145
end entity user_logic;
146
 
147
------------------------------------------------------------------------------
148
-- Architecture section
149
------------------------------------------------------------------------------
150
 
151
architecture IMP of user_logic is
152
 
153
  --USER signal declarations added here, as needed for user logic
154
 
155
  ------------------------------------------------------------------
156
  -- Signals for multiplier core slave model s/w accessible register
157
  ------------------------------------------------------------------
158
  signal slv_reg0                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
159
  signal slv_reg_write_sel              : std_logic_vector(0 to 0);
160
  signal slv_reg_read_sel               : std_logic_vector(0 to 0);
161
  signal slv_ip2bus_data                : std_logic_vector(0 to C_SLV_DWIDTH-1);
162
  signal slv_read_ack                   : std_logic;
163
  signal slv_write_ack                  : std_logic;
164
 
165
  signal load_flags                     : std_logic;
166
 
167
  ------------------------------------------------------------------
168
  -- Signals for multiplier core interrupt
169
  ------------------------------------------------------------------
170
  signal core_interrupt                 : std_logic_vector(0 to 0);
171 45 JonasDC
  signal core_fifo_full                 : std_logic;
172 2 JonasDC
  signal core_fifo_nopush               : std_logic;
173
  signal core_ready                     : std_logic;
174
  signal core_mem_collision             : std_logic;
175
 
176
  ------------------------------------------------------------------
177
  -- Signals for multiplier core control
178
  ------------------------------------------------------------------
179
  signal core_start                     : std_logic;
180 45 JonasDC
  signal core_exp_m                     : std_logic;
181 2 JonasDC
  signal core_p_sel                     : std_logic_vector(1 downto 0);
182
  signal core_dest_op_single            : std_logic_vector(1 downto 0);
183
  signal core_x_sel_single              : std_logic_vector(1 downto 0);
184
  signal core_y_sel_single              : std_logic_vector(1 downto 0);
185
  signal core_flags                     : std_logic_vector(15 downto 0);
186
 
187
  ------------------------------------------------------------------
188
  -- Signals for multiplier core memory space
189
  ------------------------------------------------------------------
190
  signal mem_address                    : std_logic_vector(0 to 5);
191
  signal mem_select                     : std_logic_vector(0 to 5);
192
  signal mem_read_enable                : std_logic;
193
  signal mem_read_enable_dly1           : std_logic;
194
  signal mem_read_req                   : std_logic;
195
  signal mem_ip2bus_data                : std_logic_vector(0 to C_SLV_DWIDTH-1);
196
  signal mem_read_ack_dly1              : std_logic;
197
  signal mem_read_ack                   : std_logic;
198
  signal mem_write_ack                  : std_logic;
199
 
200
  signal core_rw_address                : std_logic_vector (8 downto 0);
201
  signal core_data_in                   : std_logic_vector(31 downto 0);
202
  signal core_fifo_din                  : std_logic_vector(31 downto 0);
203
  signal sel_mno                        : std_logic;
204
  signal sel_op                         : std_logic_vector(1 downto 0);
205
  signal core_data_out                  : std_logic_vector(31 downto 0);
206
  signal core_write_enable              : std_logic;
207
  signal core_fifo_push                 : std_logic;
208
begin
209
 
210
  --USER logic implementation added here
211
  --ctrl_sigs <= 
212
 
213
  ------------------------------------------
214
  -- Example code to read/write user logic slave model s/w accessible registers
215
  -- 
216
  -- Note:
217
  -- The example code presented here is to show you one way of reading/writing
218
  -- software accessible registers implemented in the user logic slave model.
219
  -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
220
  -- to one software accessible register by the top level template. For example,
221
  -- if you have four 32 bit software accessible registers in the user logic,
222
  -- you are basically operating on the following memory mapped registers:
223
  -- 
224
  --    Bus2IP_WrCE/Bus2IP_RdCE   Memory Mapped Register
225
  --                     "1000"   C_BASEADDR + 0x0
226
  --                     "0100"   C_BASEADDR + 0x4
227
  --                     "0010"   C_BASEADDR + 0x8
228
  --                     "0001"   C_BASEADDR + 0xC
229
  -- 
230
  ------------------------------------------
231
  slv_reg_write_sel <= Bus2IP_WrCE(0 to 0);
232
  slv_reg_read_sel  <= Bus2IP_RdCE(0 to 0);
233
  slv_write_ack     <= Bus2IP_WrCE(0);
234
  slv_read_ack      <= Bus2IP_RdCE(0);
235
 
236
  -- implement slave model software accessible register(s)
237
  SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
238
  begin
239
    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
240
      if Bus2IP_Reset = '1' then
241
        slv_reg0 <= (others => '0');
242
      elsif load_flags = '1' then
243
                  slv_reg0 <= slv_reg0(0 to 15) & core_flags;
244
                else
245
        case slv_reg_write_sel is
246
          when "1" =>
247
            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
248
              if ( Bus2IP_BE(byte_index) = '1' ) then
249
                slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
250
              end if;
251
            end loop;
252
          when others => null;
253
        end case;
254
      end if;
255
    end if;
256
 
257
  end process SLAVE_REG_WRITE_PROC;
258
 
259
  -- implement slave model software accessible register(s) read mux
260
  SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0 ) is
261
  begin
262
 
263
    case slv_reg_read_sel is
264
      when "1" => slv_ip2bus_data <= slv_reg0;
265
      when others => slv_ip2bus_data <= (others => '0');
266
    end case;
267
 
268
  end process SLAVE_REG_READ_PROC;
269
 
270
  ------------------------------------------
271
  -- Multiplier core interrupts form IP core interrupt
272
  ------------------------------------------
273
 
274
  core_interrupt(0) <= core_ready or core_mem_collision or core_fifo_full or core_fifo_nopush;
275
  IP2Bus_IntrEvent <= core_interrupt;
276
 
277
  FLAGS_CNTRL_PROC: process(Bus2IP_Clk, Bus2IP_Reset) is
278
  begin
279
    if Bus2IP_Reset = '1' then
280
           core_flags <= (others => '0');
281
                load_flags <= '0';
282
    elsif rising_edge(Bus2IP_Clk) then
283
           if core_start = '1' then
284
                  core_flags <= (others => '0');
285
                else
286
                  if core_ready = '1' then
287
                    core_flags(15) <= '1';
288
                  else
289
                    core_flags(15) <= core_flags(15);
290
                  end if;
291
                  if core_mem_collision = '1' then
292
                    core_flags(14) <= '1';
293
                  else
294
                    core_flags(14) <= core_flags(14);
295
                  end if;
296
                  if core_fifo_full = '1' then
297
                         core_flags(13) <= '1';
298
                  else
299
                    core_flags(13) <= core_flags(13);
300
                  end if;
301
                  if core_fifo_nopush = '1' then
302
                         core_flags(12) <= '1';
303
                  else
304
                    core_flags(12) <= core_flags(12);
305
                  end if;
306
                end if;
307
                --
308
                load_flags <= core_interrupt(0);
309
         end if;
310
  end process FLAGS_CNTRL_PROC;
311
 
312
  ------------------------------------------
313
  -- Example code to access user logic memory region
314
  -- 
315
  -- Note:
316
  -- The example code presented here is to show you one way of using
317
  -- the user logic memory space features. The Bus2IP_Addr, Bus2IP_CS,
318
  -- and Bus2IP_RNW IPIC signals are dedicated to these user logic
319
  -- memory spaces. Each user logic memory space has its own address
320
  -- range and is allocated one bit on the Bus2IP_CS signal to indicated
321
  -- selection of that memory space. Typically these user logic memory
322
  -- spaces are used to implement memory controller type cores, but it
323
  -- can also be used in cores that need to access additional address space
324
  -- (non C_BASEADDR based), s.t. bridges. This code snippet infers
325
  -- 6 256x32-bit (byte accessible) single-port Block RAM by XST.
326
  ------------------------------------------
327
  mem_select      <= Bus2IP_CS;
328
  mem_read_enable <= ( Bus2IP_CS(0) or Bus2IP_CS(1) or Bus2IP_CS(2) or Bus2IP_CS(3) or Bus2IP_CS(4) or Bus2IP_CS(5) ) and Bus2IP_RNW;
329
  mem_read_ack    <= mem_read_ack_dly1;
330
  mem_write_ack   <= ( Bus2IP_CS(0) or Bus2IP_CS(1) or Bus2IP_CS(2) or Bus2IP_CS(3) or Bus2IP_CS(4) or Bus2IP_CS(5) ) and not(Bus2IP_RNW);
331
  mem_address     <= Bus2IP_Addr(C_SLV_AWIDTH-8 to C_SLV_AWIDTH-3);
332
 
333
  -- implement single clock wide read request
334
  mem_read_req    <= mem_read_enable and not(mem_read_enable_dly1);
335
  BRAM_RD_REQ_PROC : process( Bus2IP_Clk ) is
336
  begin
337
 
338
    if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
339
      if ( Bus2IP_Reset = '1' ) then
340
        mem_read_enable_dly1 <= '0';
341 42 JonasDC
 
342 2 JonasDC
      else
343
        mem_read_enable_dly1 <= mem_read_enable;
344
      end if;
345
    end if;
346
 
347
  end process BRAM_RD_REQ_PROC;
348
 
349
  -- this process generates the read acknowledge 1 clock after read enable
350
  -- is presented to the BRAM block. The BRAM block has a 1 clock delay
351
  -- from read enable to data out.
352
  BRAM_RD_ACK_PROC : process( Bus2IP_Clk ) is
353
  begin
354
 
355
    if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
356
      if ( Bus2IP_Reset = '1' ) then
357
        mem_read_ack_dly1 <= '0';
358
      else
359
        mem_read_ack_dly1 <= mem_read_req;
360
      end if;
361
    end if;
362
 
363
  end process BRAM_RD_ACK_PROC;
364
 
365
    -- address logic
366
  Sel_MNO <= mem_select(0);
367
  with mem_select(1 to 4) select
368
    Sel_Op <= "00" when "1000",
369
                   "01" when "0100",
370
                                  "10" when "0010",
371
                                  "11" when others;
372
 
373
 
374
  core_rw_address <= Sel_MNO & Sel_Op & mem_address;
375
 
376
  -- data-in
377
  core_data_in <= Bus2IP_Data;
378
  core_fifo_din <= Bus2IP_Data;
379
  core_write_enable <= (Bus2IP_CS(0) or Bus2IP_CS(1) or Bus2IP_CS(2) or Bus2IP_CS(3) or Bus2IP_CS(4)) and (not Bus2IP_RNW);
380
  core_fifo_push <= Bus2IP_CS(5) and (not Bus2IP_RNW);
381
  -- no read mux required, we can only read from core_data_out
382
  mem_ip2bus_data <= core_data_out;
383
 
384
  ------------------------------------------
385
  -- Map slv_reg0 bits to core control signals 
386
  ------------------------------------------
387
  core_start <= slv_reg0(8);
388 45 JonasDC
  core_exp_m <= slv_reg0(9);
389 2 JonasDC
  core_p_sel <= slv_reg0(0 to 1);
390
  core_dest_op_single <= slv_reg0(2 to 3);
391
  core_x_sel_single <= slv_reg0(4 to 5);
392
  core_y_sel_single <= slv_reg0(6 to 7);
393
 
394
  ------------------------------------------
395
  -- Multiplier core instance
396
  ------------------------------------------
397 40 JonasDC
  the_multiplier: mod_sim_exp_core
398 43 JonasDC
  generic map(
399
    C_NR_BITS_TOTAL   => C_NR_BITS_TOTAL,
400
    C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
401
    C_NR_STAGES_LOW   => C_NR_STAGES_LOW,
402
    C_SPLIT_PIPELINE  => C_SPLIT_PIPELINE
403
  )
404
  port map(
405
    clk   => Bus2IP_Clk,
406
    reset => Bus2IP_Reset,
407
      -- operand memory interface (plb shared memory)
408
    write_enable => core_write_enable,
409
    data_in      => core_data_in,
410
    rw_address   => core_rw_address,
411
    data_out     => core_data_out,
412
    collision    => core_mem_collision,
413
      -- op_sel fifo interface
414
    fifo_din    => core_fifo_din,
415
    fifo_push   => core_fifo_push,
416
    fifo_full   => core_fifo_full,
417
    fifo_nopush => core_fifo_nopush,
418
      -- ctrl signals
419
    start          => core_start,
420 45 JonasDC
    exp_m          => core_exp_m,
421 43 JonasDC
    ready          => core_ready,
422
    x_sel_single   => core_x_sel_single,
423
    y_sel_single   => core_y_sel_single,
424
    dest_op_single => core_dest_op_single,
425
    p_sel          => core_p_sel,
426
    calc_time      => calc_time
427 2 JonasDC
  );
428
 
429 43 JonasDC
 
430 2 JonasDC
  ------------------------------------------
431
  -- Drive IP to Bus signals
432
  ------------------------------------------
433
  IP2Bus_Data  <= slv_ip2bus_data when slv_read_ack = '1' else
434
                  mem_ip2bus_data when mem_read_ack = '1' else
435
                  (others => '0');
436
 
437
  IP2Bus_WrAck <= slv_write_ack or mem_write_ack;
438
  IP2Bus_RdAck <= slv_read_ack or mem_read_ack;
439
  IP2Bus_Error <= '0';
440
 
441
end IMP;

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