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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [syn/] [xilinx/] [log/] [fifo/] [generic_fifo_dc_gray_aw5_summary.html] - Blame information for rev 94

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<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>mod_sim_exp_core Project Status (07/03/2013 - 16:29:30)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>msec.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>generic_fifo_dc_gray</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>Synthesized</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6vlx240t-1ff1156</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>
No Errors</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.4</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/_xmsgs/*.xmsgs?&DataKey=Warning'>12 Warnings (12 new)</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>
<A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/generic_fifo_dc_gray_envsettings.html'>
System Settings</A>
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
</TR>
</TABLE>
 
 
 
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Device Utilization Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></a></TD></TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD COLSPAN='2'><B>Utilization</B></TD></TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
<TD ALIGN=RIGHT>62</TD>
<TD ALIGN=RIGHT>301440</TD>
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
<TD ALIGN=RIGHT>66</TD>
<TD ALIGN=RIGHT>150720</TD>
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of fully used LUT-FF pairs</TD>
<TD ALIGN=RIGHT>54</TD>
<TD ALIGN=RIGHT>74</TD>
<TD ALIGN=RIGHT COLSPAN='2'>72%</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded IOBs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>600</TD>
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Block RAM/FIFO</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>416</TD>
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
</TR>
</TABLE>
 
 
 
 
 
 
 
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/generic_fifo_dc_gray.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Jul 3 16:29:29 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/_xmsgs/xst.xmsgs?&DataKey=Warning'>12 Warnings (12 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/_xmsgs/xst.xmsgs?&DataKey=Info'>4 Infos (4 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
</TABLE>
 
 
<br><center><b>Date Generated:</b> 07/03/2013 - 16:29:30</center>
</BODY></HTML>

Line No.	Rev	Author	Line
1	94	JonasDC	`<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>`
2			`<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>`
3			`<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>`
4			`<TR ALIGN=CENTER BGCOLOR='#99CCFF'>`
5			`<TD ALIGN=CENTER COLSPAN='4'><B>mod_sim_exp_core Project Status (07/03/2013 - 16:29:30)</B></TD></TR>`
6			`<TR ALIGN=LEFT>`
7			`<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>`
8			`<TD>msec.xise</TD>`
9			`<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>`
10			`<TD> No Errors </TD>`
11			`</TR>`
12			`<TR ALIGN=LEFT>`
13			`<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>`
14			`<TD>generic_fifo_dc_gray</TD>`
15			`<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>`
16			`<TD>Synthesized</TD>`
17			`</TR>`
18			`<TR ALIGN=LEFT>`
19			`<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>`
20			`<TD>xc6vlx240t-1ff1156</TD>`
21			`<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>`
22			`<TD>`
23			`No Errors</TD>`
24			`</TR>`
25			`<TR ALIGN=LEFT>`
26			`<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.4</TD>`
27			`<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>`
28			`<TD ALIGN=LEFT><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/_xmsgs/*.xmsgs?&DataKey=Warning'>12 Warnings (12 new)</A></TD>`
29			`</TR>`
30			`<TR ALIGN=LEFT>`
31			`<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>`
32			`<TD>Balanced</TD>`
33			`<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>`
34			`<TD>`
35			` </TD>`
36			`</TR>`
37			`<TR ALIGN=LEFT>`
38			`<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>`
39			`<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>`
40			`<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>`
41			`<TD> </TD>`
42			`</TR>`
43			`<TR ALIGN=LEFT>`
44			`<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>`
45			`<TD>`
46			`<A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/generic_fifo_dc_gray_envsettings.html'>`
47			`System Settings</A>`
48			`</TD>`
49			`<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>`
50			`<TD>  </TD>`
51			`</TR>`
52			`</TABLE>`
53
54
55
56			` <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>`
57			`<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Device Utilization Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></a></TD></TR>`
58			`<TR ALIGN=CENTER BGCOLOR='#FFFF99'>`
59			`<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD COLSPAN='2'><B>Utilization</B></TD></TR>`
60			`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>`
61			`<TD ALIGN=RIGHT>62</TD>`
62			`<TD ALIGN=RIGHT>301440</TD>`
63			`<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>`
64			`</TR>`
65			`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>`
66			`<TD ALIGN=RIGHT>66</TD>`
67			`<TD ALIGN=RIGHT>150720</TD>`
68			`<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>`
69			`</TR>`
70			`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of fully used LUT-FF pairs</TD>`
71			`<TD ALIGN=RIGHT>54</TD>`
72			`<TD ALIGN=RIGHT>74</TD>`
73			`<TD ALIGN=RIGHT COLSPAN='2'>72%</TD>`
74			`</TR>`
75			`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded IOBs</TD>`
76			`<TD ALIGN=RIGHT>0</TD>`
77			`<TD ALIGN=RIGHT>600</TD>`
78			`<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>`
79			`</TR>`
80			`<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Block RAM/FIFO</TD>`
81			`<TD ALIGN=RIGHT>1</TD>`
82			`<TD ALIGN=RIGHT>416</TD>`
83			`<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>`
84			`</TR>`
85			`</TABLE>`
86
87
88
89
90
91
92
93			` <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>`
94			`<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>`
95			`<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>`
96			`<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>`
97			<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/generic_fifo_dc_gray.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Jul 3 16:29:29 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/_xmsgs/xst.xmsgs?&DataKey=Warning'>12 Warnings (12 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/dinghe/Thesis/mod_sim_exp/trunk/iseproj/msec/_xmsgs/xst.xmsgs?&DataKey=Info'>4 Infos (4 new)</A></TD></TR>
98			`<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>`
99			`<TR ALIGN=LEFT><TD>Map Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>`
100			`<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>`
101			`<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>`
102			`<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>`
103			`<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>`
104			`</TABLE>`
105			` <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>`
106			`<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>`
107			`<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>`
108			`</TABLE>`
109
110
111			`<br><center><b>Date Generated:</b> 07/03/2013 - 16:29:30</center>`
112			`</BODY></HTML>`

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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [syn/] [xilinx/] [log/] [fifo/] [generic_fifo_dc_gray_aw5_summary.html] - Blame information for rev 94