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<BODY><PRE><FONT&NBSP;FACE="COURIER&NBSP;NEW",&NBSP;MONOTYPE><P&NBSP;ALIGN=LEFT><B>Synthesis Report</B><P></P><B><CENTER>di 26. feb 15:21:57 2013</CENTER></B><BR><HR><BR>Release 12.4 - xst M.81d (nt)<BR>Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.<BR>--> Parameter TMPDIR set to xst/projnav.tmp<BR><BR><BR>Total REAL time to Xst completion: 0.00 secs<BR>Total CPU time to Xst completion: 0.11 secs<BR> <BR>--> Parameter xsthdpdir set to xst<BR><BR><BR>Total REAL time to Xst completion: 0.00 secs<BR>Total CPU time to Xst completion: 0.11 secs<BR> <BR>--> Reading design: mod_sim_exp_core.prj<BR><BR>TABLE OF CONTENTS<BR> 1) Synthesis Options Summary<BR> 2) HDL Parsing<BR> 3) HDL Elaboration<BR> 4) HDL Synthesis<BR> 4.1) HDL Synthesis Report<BR> 5) Advanced HDL Synthesis<BR> 5.1) Advanced HDL Synthesis Report<BR> 6) Low Level Synthesis<BR> 7) Partition Report<BR> 8) Design Summary<BR> 8.1) Primitive and Black Box Usage<BR> 8.2) Device utilization summary<BR> 8.3) Partition Resource Summary<BR> 8.4) Timing Report<BR> 8.4.1) Clock Information<BR> 8.4.2) Asynchronous Control Signals Information<BR> 8.4.3) Timing Summary<BR> 8.4.4) Timing Details<BR> 8.4.5) Cross Clock Domains Report<BR><BR><BR>=========================================================================<BR>* Synthesis Options Summary *<BR>=========================================================================<BR>---- Source Parameters<BR>Input File Name : "mod_sim_exp_core.prj"<BR>Input Format : mixed<BR>Ignore Synthesis Constraint File : NO<BR><BR>---- Target Parameters<BR>Output File Name : "mod_sim_exp_core"<BR>Output Format : NGC<BR>Target Device : xc6vlx240t-1-ff1156<BR><BR>---- Source Options<BR>Top Module Name : mod_sim_exp_core<BR>Automatic FSM Extraction : YES<BR>FSM Encoding Algorithm : Auto<BR>Safe Implementation : No<BR>FSM Style : LUT<BR>RAM Extraction : Yes<BR>RAM Style : Auto<BR>ROM Extraction : Yes<BR>Shift Register Extraction : YES<BR>ROM Style : Auto<BR>Resource Sharing : YES<BR>Asynchronous To Synchronous : NO<BR>Shift Register Minimum Size : 2<BR>Use DSP Block : Auto<BR>Automatic Register Balancing : No<BR><BR>---- Target Options<BR>LUT Combining : Auto<BR>Reduce Control Sets : Auto<BR>Add IO Buffers : NO<BR>Global Maximum Fanout : 100000<BR>Add Generic Clock Buffer(BUFG) : 32<BR>Register Duplication : YES<BR>Optimize Instantiated Primitives : NO<BR>Use Clock Enable : Auto<BR>Use Synchronous Set : Auto<BR>Use Synchronous Reset : Auto<BR>Pack IO Registers into IOBs : Auto<BR>Equivalent register Removal : YES<BR><BR>---- General Options<BR>Optimization Goal : Area<BR>Optimization Effort : 2<BR>Power Reduction : NO<BR>Keep Hierarchy : No<BR>Netlist Hierarchy : As_Optimized<BR>RTL Output : Yes<BR>Global Optimization : AllClockNets<BR>Read Cores : YES<BR>Write Timing Constraints : NO<BR>Cross Clock Analysis : NO<BR>Hierarchy Separator : /<BR>Bus Delimiter : <><BR>Case Specifier : Maintain<BR>Slice Utilization Ratio : 100<BR>BRAM Utilization Ratio : 100<BR>DSP48 Utilization Ratio : 100<BR>Auto BRAM Packing : NO<BR>Slice Utilization Ratio Delta : 5<BR><BR>---- Other Options<BR>Cores Search Directories : {"../../SVN/mod_sim_exp/rtl/vhdl/core" }<BR><BR>=========================================================================<BR><BR><BR>=========================================================================<BR>* HDL Parsing *<BR>=========================================================================<BR>Analyzing Verilog file \"\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_dp.v\" into library work<BR>Parsing module <OPERAND_DP>.<BR>Analyzing Verilog file \"\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operands_sp.v\" into library work<BR>Parsing module <OPERANDS_SP>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/std_functions.vhd" into library mod_sim_exp<BR>Parsing package <STD_FUNCTIONS>.<BR>Parsing package body <STD_FUNCTIONS>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_pkg.vhd" into library mod_sim_exp<BR>Parsing package <MOD_SIM_EXP_PKG>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/cell_1b_mux.vhd" into library mod_sim_exp<BR>Parsing entity <CELL_1B_MUX>.<BR>Parsing architecture <BEHAVIORAL> of entity <CELL_1B_MUX>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/cell_1b_adder.vhd" into library mod_sim_exp<BR>Parsing entity <CELL_1B_ADDER>.<BR>Parsing architecture <BEHAVIORAL> of entity <CELL_1B_ADDER>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/d_flip_flop.vhd" into library mod_sim_exp<BR>Parsing entity <D_FLIP_FLOP>.<BR>Parsing architecture <BEHAVORIAL> of entity <D_FLIP_FLOP>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/cell_1b.vhd" into library mod_sim_exp<BR>Parsing entity <CELL_1B>.<BR>Parsing architecture <STRUCTURAL> of entity <CELL_1B>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/standard_cell_block.vhd" into library mod_sim_exp<BR>Parsing entity <STANDARD_CELL_BLOCK>.<BR>Parsing architecture <STRUCTURAL> of entity <STANDARD_CELL_BLOCK>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/register_n.vhd" into library mod_sim_exp<BR>Parsing entity <REGISTER_N>.<BR>Parsing architecture <BEHAVORIAL> of entity <REGISTER_N>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/register_1b.vhd" into library mod_sim_exp<BR>Parsing entity <REGISTER_1B>.<BR>Parsing architecture <BEHAVORIAL> of entity <REGISTER_1B>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/adder_block.vhd" into library mod_sim_exp<BR>Parsing entity <ADDER_BLOCK>.<BR>Parsing architecture <STRUCTURAL> of entity <ADDER_BLOCK>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/sys_stage.vhd" into library mod_sim_exp<BR>Parsing entity <SYS_STAGE>.<BR>Parsing architecture <STRUCTURAL> of entity <SYS_STAGE>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/sys_last_cell_logic.vhd" into library mod_sim_exp<BR>Parsing entity <SYS_LAST_CELL_LOGIC>.<BR>Parsing architecture <BEHAVORIAL> of entity <SYS_LAST_CELL_LOGIC>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/sys_first_cell_logic.vhd" into library mod_sim_exp<BR>Parsing entity <SYS_FIRST_CELL_LOGIC>.<BR>Parsing architecture <BEHAVORIAL> of entity <SYS_FIRST_CELL_LOGIC>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/counter_sync.vhd" into library mod_sim_exp<BR>Parsing entity <COUNTER_SYNC>.<BR>Parsing architecture <BEHAVIORAL> of entity <COUNTER_SYNC>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/x_shift_reg.vhd" into library mod_sim_exp<BR>Parsing entity <X_SHIFT_REG>.<BR>Parsing architecture <BEHAVIORAL> of entity <X_SHIFT_REG>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/sys_pipeline.vhd" into library mod_sim_exp<BR>Parsing entity <SYS_PIPELINE>.<BR>Parsing architecture <STRUCTURAL> of entity <SYS_PIPELINE>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/stepping_logic.vhd" into library mod_sim_exp<BR>Parsing entity <STEPPING_LOGIC>.<BR>Parsing architecture <BEHAVIORAL> of entity <STEPPING_LOGIC>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_ram.vhd" into library mod_sim_exp<BR>Parsing entity <OPERAND_RAM>.<BR>Parsing architecture <BEHAVIORAL> of entity <OPERAND_RAM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/modulus_ram.vhd" into library mod_sim_exp<BR>Parsing entity <MODULUS_RAM>.<BR>Parsing architecture <BEHAVIORAL> of entity <MODULUS_RAM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/autorun_cntrl.vhd" into library mod_sim_exp<BR>Parsing entity <AUTORUN_CNTRL>.<BR>Parsing architecture <BEHAVIORAL> of entity <AUTORUN_CNTRL>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/operand_mem.vhd" into library mod_sim_exp<BR>Parsing entity <OPERAND_MEM>.<BR>Parsing architecture <BEHAVIORAL> of entity <OPERAND_MEM>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mont_multiplier.vhd" into library mod_sim_exp<BR>Parsing entity <MONT_MULTIPLIER>.<BR>Parsing architecture <STRUCTURAL> of entity <MONT_MULTIPLIER>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mont_ctrl.vhd" into library mod_sim_exp<BR>Parsing entity <MONT_CTRL>.<BR>Parsing architecture <BEHAVIORAL> of entity <MONT_CTRL>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/fifo_primitive.vhd" into library mod_sim_exp<BR>Parsing entity <FIFO_PRIMITIVE>.<BR>Parsing architecture <BEHAVIORAL> of entity <FIFO_PRIMITIVE>.<BR>Parsing VHDL file "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_core.vhd" into library mod_sim_exp<BR>Parsing entity <MOD_SIM_EXP_CORE>.<BR>Parsing architecture <STRUCTURAL> of entity <MOD_SIM_EXP_CORE>.<BR><BR>=========================================================================<BR>* HDL Elaboration *<BR>=========================================================================<BR><BR>Elaborating entity <MOD_SIM_EXP_CORE> (architecture <STRUCTURAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <MONT_MULTIPLIER> (architecture <STRUCTURAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <D_FLIP_FLOP> (architecture <BEHAVORIAL>) from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <X_SHIFT_REG> (architecture <BEHAVIORAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <STEPPING_LOGIC> (architecture <BEHAVIORAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <COUNTER_SYNC> (architecture <BEHAVIORAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <COUNTER_SYNC> (architecture <BEHAVIORAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <COUNTER_SYNC> (architecture <BEHAVIORAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <SYS_PIPELINE> (architecture <STRUCTURAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <SYS_STAGE> (architecture <STRUCTURAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <ADDER_BLOCK> (architecture <STRUCTURAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <CELL_1B_ADDER> (architecture <BEHAVIORAL>) from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <STANDARD_CELL_BLOCK> (architecture <STRUCTURAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <CELL_1B> (architecture <STRUCTURAL>) from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <CELL_1B_MUX> (architecture <BEHAVIORAL>) from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <REGISTER_N> (architecture <BEHAVORIAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <REGISTER_1B> (architecture <BEHAVORIAL>) from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <SYS_FIRST_CELL_LOGIC> (architecture <BEHAVORIAL>) from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <SYS_LAST_CELL_LOGIC> (architecture <BEHAVORIAL>) from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <OPERAND_MEM> (architecture <BEHAVIORAL>) with generics from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <OPERAND_RAM> (architecture <BEHAVIORAL>) from library <MOD_SIM_EXP>.<BR>WARNING:HDLCompiler:89 - "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_pkg.vhd" Line 475: <OPERAND_DP> remains a black-box since it has no binding entity.<BR><BR>Elaborating entity <MODULUS_RAM> (architecture <BEHAVIORAL>) from library <MOD_SIM_EXP>.<BR>WARNING:HDLCompiler:89 - "\Dropbox\ISE\mod_exp_core\../../SVN/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_pkg.vhd" Line 495: <OPERANDS_SP> remains a black-box since it has no binding entity.<BR><BR>Elaborating entity <FIFO_PRIMITIVE> (architecture <BEHAVIORAL>) from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <MONT_CTRL> (architecture <BEHAVIORAL>) from library <MOD_SIM_EXP>.<BR><BR>Elaborating entity <AUTORUN_CNTRL> (architecture <BEHAVIORAL>) from library <MOD_SIM_EXP>.<BR><BR>=========================================================================<BR>* HDL Synthesis *<BR>=========================================================================<BR><BR>Synthesizing Unit <MOD_SIM_EXP_CORE>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_core.vhd".<BR> C_NR_BITS_TOTAL = 1536<BR> C_NR_STAGES_TOTAL = 96<BR> C_NR_STAGES_LOW = 32<BR> C_SPLIT_PIPELINE = true<BR> C_NR_OP = 4<BR> C_NR_M = 2<BR> C_FIFO_DEPTH = 32<BR>INFO:Xst:3010 - "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/mod_sim_exp_core.vhd" line 167: Output port <NOPOP> of the instance <THE_EXPONENT_FIFO> is unconnected or connected to loadless signal.<BR> Summary:<BR> inferred 1 Multiplexer(s).<BR>Unit <MOD_SIM_EXP_CORE> synthesized.<BR><BR>Synthesizing Unit <MONT_MULTIPLIER>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/mont_multiplier.vhd".<BR> n = 1536<BR> t = 96<BR> tl = 32<BR> split = true<BR> Found 4x18-bit Read Only RAM for signal <_n0015><BR> Summary:<BR> inferred 1 RAM(s).<BR>Unit <MONT_MULTIPLIER> synthesized.<BR><BR>Synthesizing Unit <D_FLIP_FLOP>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/d_flip_flop.vhd".<BR> Found 1-bit register for signal <DOUT>.<BR> Summary:<BR> inferred 1 D-type flip-flop(s).<BR>Unit <D_FLIP_FLOP> synthesized.<BR><BR>Synthesizing Unit <X_SHIFT_REG>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/x_shift_reg.vhd".<BR> n = 1536<BR> t = 96<BR> tl = 32<BR> Found 1536-bit register for signal <X_REG>.<BR> Summary:<BR> inferred 1536 D-type flip-flop(s).<BR> inferred 1536 Multiplexer(s).<BR>Unit <X_SHIFT_REG> synthesized.<BR><BR>Synthesizing Unit <STEPPING_LOGIC>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/stepping_logic.vhd".<BR> n = 1536<BR> t = 96<BR> Summary:<BR> no macro.<BR>Unit <STEPPING_LOGIC> synthesized.<BR><BR>Synthesizing Unit <COUNTER_SYNC_1>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/counter_sync.vhd".<BR> max_value = 96<BR> Found 7-bit register for signal <COUNT_PROC.STEPS_COUNTER>.<BR> Found 1-bit register for signal <OVERFLOW>.<BR> Found 7-bit adder for signal <COUNT_PROC.STEPS_COUNTER[6]_GND_12_O_ADD_2_OUT> created at line 83.<BR> Found 32-bit subtractor for signal <RESET_VALUE[31]_GND_12_O_SUB_1_OUT<31:0>> created at line 79.<BR> Found 32-bit comparator equal for signal <RESET_VALUE[31]_GND_12_O_EQUAL_2_O> created at line 79<BR> Summary:<BR> inferred 2 Adder/Subtractor(s).<BR> inferred 8 D-type flip-flop(s).<BR> inferred 1 Comparator(s).<BR> inferred 2 Multiplexer(s).<BR>Unit <COUNTER_SYNC_1> synthesized.<BR><BR>Synthesizing Unit <COUNTER_SYNC_2>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/counter_sync.vhd".<BR> max_value = 1536<BR> Found 11-bit register for signal <COUNT_PROC.STEPS_COUNTER>.<BR> Found 1-bit register for signal <OVERFLOW>.<BR> Found 11-bit adder for signal <COUNT_PROC.STEPS_COUNTER[10]_GND_38_O_ADD_2_OUT> created at line 83.<BR> Found 32-bit subtractor for signal <RESET_VALUE[31]_GND_38_O_SUB_1_OUT<31:0>> created at line 79.<BR> Found 32-bit comparator equal for signal <RESET_VALUE[31]_GND_38_O_EQUAL_2_O> created at line 79<BR> Summary:<BR> inferred 2 Adder/Subtractor(s).<BR> inferred 12 D-type flip-flop(s).<BR> inferred 1 Comparator(s).<BR> inferred 2 Multiplexer(s).<BR>Unit <COUNTER_SYNC_2> synthesized.<BR><BR>Synthesizing Unit <COUNTER_SYNC_3>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/counter_sync.vhd".<BR> max_value = 2<BR> Found 1-bit register for signal <OVERFLOW>.<BR> Found 1-bit register for signal <COUNT_PROC.STEPS_COUNTER>.<BR> Found 1-bit adder for signal <COUNT_PROC.STEPS_COUNTER[0]_PWR_15_O_ADD_2_OUT<0>> created at line 83.<BR> Summary:<BR> inferred 1 Adder/Subtractor(s).<BR> inferred 2 D-type flip-flop(s).<BR> inferred 2 Multiplexer(s).<BR>Unit <COUNTER_SYNC_3> synthesized.<BR><BR>Synthesizing Unit <SYS_PIPELINE>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_pipeline.vhd".<BR> n = 1536<BR> t = 96<BR> tl = 32<BR> split = true<BR>INFO:Xst:3010 - "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_pipeline.vhd" line 133: Output port <MY_COUT> of the instance <PIPELINE_STAGES[95].STAGE> is unconnected or connected to loadless signal.<BR>INFO:Xst:3010 - "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_pipeline.vhd" line 133: Output port <XOUT> of the instance <PIPELINE_STAGES[95].STAGE> is unconnected or connected to loadless signal.<BR>INFO:Xst:3010 - "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_pipeline.vhd" line 133: Output port <QOUT> of the instance <PIPELINE_STAGES[95].STAGE> is unconnected or connected to loadless signal.<BR> Found 1-bit 3-to-1 multiplexer for signal <START_STAGE<32>> created at line 270.<BR> Found 1-bit 4-to-1 multiplexer for signal <R_SEL_L> created at line 304.<BR> Summary:<BR> inferred 11 Multiplexer(s).<BR>Unit <SYS_PIPELINE> synthesized.<BR><BR>Synthesizing Unit <SYS_STAGE>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_stage.vhd".<BR> width = 16<BR> Summary:<BR> inferred 1 Multiplexer(s).<BR>Unit <SYS_STAGE> synthesized.<BR><BR>Synthesizing Unit <ADDER_BLOCK>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/adder_block.vhd".<BR> width = 16<BR> Summary:<BR> no macro.<BR>Unit <ADDER_BLOCK> synthesized.<BR><BR>Synthesizing Unit <CELL_1B_ADDER>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/cell_1b_adder.vhd".<BR> Summary:<BR>Unit <CELL_1B_ADDER> synthesized.<BR><BR>Synthesizing Unit <STANDARD_CELL_BLOCK>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/standard_cell_block.vhd".<BR> width = 16<BR> Summary:<BR> no macro.<BR>Unit <STANDARD_CELL_BLOCK> synthesized.<BR><BR>Synthesizing Unit <CELL_1B>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/cell_1b.vhd".<BR> Summary:<BR> no macro.<BR>Unit <CELL_1B> synthesized.<BR><BR>Synthesizing Unit <CELL_1B_MUX>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/cell_1b_mux.vhd".<BR> Found 1-bit 4-to-1 multiplexer for signal <RESULT> created at line 72.<BR> Summary:<BR> inferred 1 Multiplexer(s).<BR>Unit <CELL_1B_MUX> synthesized.<BR><BR>Synthesizing Unit <REGISTER_N>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/register_n.vhd".<BR> width = 16<BR> Found 16-bit register for signal <DOUT>.<BR> Summary:<BR> inferred 16 D-type flip-flop(s).<BR>Unit <REGISTER_N> synthesized.<BR><BR>Synthesizing Unit <REGISTER_1B>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/register_1b.vhd".<BR> Found 1-bit register for signal <DOUT>.<BR> Summary:<BR> inferred 1 D-type flip-flop(s).<BR>Unit <REGISTER_1B> synthesized.<BR><BR>Synthesizing Unit <SYS_FIRST_CELL_LOGIC>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_first_cell_logic.vhd".<BR> Summary:<BR>Unit <SYS_FIRST_CELL_LOGIC> synthesized.<BR><BR>Synthesizing Unit <SYS_LAST_CELL_LOGIC>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_last_cell_logic.vhd".<BR>INFO:Xst:3010 - "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/sys_last_cell_logic.vhd" line 86: Output port <R> of the instance <REDUCTION_ADDER> is unconnected or connected to loadless signal.<BR> Summary:<BR> no macro.<BR>Unit <SYS_LAST_CELL_LOGIC> synthesized.<BR><BR>Synthesizing Unit <OPERAND_MEM>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/operand_mem.vhd".<BR> n = 1536<BR> Summary:<BR> inferred 2 Multiplexer(s).<BR>Unit <OPERAND_MEM> synthesized.<BR><BR>Synthesizing Unit <OPERAND_RAM>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/operand_ram.vhd".<BR> Found 32-bit 3-to-1 multiplexer for signal <RESULT_OUT> created at line 120.<BR> Summary:<BR> inferred 3 Multiplexer(s).<BR>Unit <OPERAND_RAM> synthesized.<BR><BR>Synthesizing Unit <MODULUS_RAM>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/modulus_ram.vhd".<BR> Summary:<BR> inferred 1 Multiplexer(s).<BR>Unit <MODULUS_RAM> synthesized.<BR><BR>Synthesizing Unit <FIFO_PRIMITIVE>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/fifo_primitive.vhd".<BR> Found 1-bit register for signal <RESET_I>.<BR> Found 2-bit register for signal <RESET_PROC.CLK_COUNTER>.<BR> Found 2-bit subtractor for signal <GND_108_O_GND_108_O_SUB_2_OUT<1:0>> created at line 100.<BR> Summary:<BR> inferred 1 Adder/Subtractor(s).<BR> inferred 3 D-type flip-flop(s).<BR> inferred 1 Multiplexer(s).<BR>Unit <FIFO_PRIMITIVE> synthesized.<BR><BR>Synthesizing Unit <MONT_CTRL>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/mont_ctrl.vhd".<BR> Found 3-bit register for signal <START_UP_COUNTER>.<BR> Found 1-bit register for signal <CALC_TIME_I>.<BR> Found 1-bit register for signal <START_D>.<BR> Found 3-bit adder for signal <START_UP_COUNTER[2]_GND_114_O_ADD_0_OUT> created at line 128.<BR> Summary:<BR> inferred 1 Adder/Subtractor(s).<BR> inferred 5 D-type flip-flop(s).<BR> inferred 5 Multiplexer(s).<BR>Unit <MONT_CTRL> synthesized.<BR><BR>Synthesizing Unit <AUTORUN_CNTRL>.<BR> Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/autorun_cntrl.vhd".<BR> Found 4-bit register for signal <BIT_COUNTER_I>.<BR> Found 1-bit register for signal <RUNNING_I>.<BR> Found 1-bit register for signal <START_MULTIPLIER_DEL_I>.<BR> Found 1-bit register for signal <START_CYCLE_DEL_I>.<BR> Found 1-bit register for signal <MULT_DONE_DEL_I>.<BR> Found 1-bit register for signal <CYCLE_COUNTER_I>.<BR> Found 4-bit subtractor for signal <GND_115_O_GND_115_O_SUB_4_OUT<3:0>> created at line 113.<BR> Found 1-bit 16-to-1 multiplexer for signal <E0_BIT_I> created at line 122.<BR> Found 1-bit 16-to-1 multiplexer for signal <E1_BIT_I> created at line 123.<BR> Summary:<BR> inferred 1 Adder/Subtractor(s).<BR> inferred 9 D-type flip-flop(s).<BR> inferred 7 Multiplexer(s).<BR>Unit <AUTORUN_CNTRL> synthesized.<BR><BR>=========================================================================<BR>HDL Synthesis Report<BR><BR>Macro Statistics<BR># RAMs : 1<BR> 4x18-bit single-port Read Only RAM : 1<BR># Adders/Subtractors : 8<BR> 1-bit adder : 1<BR> 11-bit adder : 1<BR> 2-bit subtractor : 1<BR> 3-bit adder : 1<BR> 32-bit subtractor : 2<BR> 4-bit subtractor : 1<BR> 7-bit adder : 1<BR># Registers : 695<BR> 1-bit register : 593<BR> 11-bit register : 1<BR> 1536-bit register : 1<BR> 16-bit register : 96<BR> 2-bit register : 1<BR> 3-bit register : 1<BR> 4-bit register : 1<BR> 7-bit register : 1<BR># Comparators : 2<BR> 32-bit comparator equal : 2<BR># Multiplexers : 3207<BR> 1-bit 16-to-1 multiplexer : 2<BR> 1-bit 2-to-1 multiplexer : 1553<BR> 1-bit 3-to-1 multiplexer : 1<BR> 1-bit 4-to-1 multiplexer : 1539<BR> 11-bit 2-to-1 multiplexer : 1<BR> 16-bit 2-to-1 multiplexer : 96<BR> 2-bit 2-to-1 multiplexer : 6<BR> 3-bit 2-to-1 multiplexer : 2<BR> 32-bit 3-to-1 multiplexer : 1<BR> 4-bit 2-to-1 multiplexer : 4<BR> 6-bit 2-to-1 multiplexer : 1<BR> 7-bit 2-to-1 multiplexer : 1<BR># Xors : 9224<BR> 1-bit xor2 : 9224<BR><BR>=========================================================================<BR><BR>=========================================================================<BR>* Advanced HDL Synthesis *<BR>=========================================================================<BR><BR>Reading core <../../SVN/mod_sim_exp/rtl/vhdl/core/operand_dp.ngc>.<BR>Reading core <../../SVN/mod_sim_exp/rtl/vhdl/core/operands_sp.ngc>.<BR>Loading core <OPERAND_DP> for timing and area information for instance <OP_0>.<BR>Loading core <OPERAND_DP> for timing and area information for instance <OP_1>.<BR>Loading core <OPERAND_DP> for timing and area information for instance <OP_2>.<BR>Loading core <OPERANDS_SP> for timing and area information for instance <MODULUS_0>.<BR>Loading core <OPERANDS_SP> for timing and area information for instance <MODULUS_1>.<BR>Loading core <OPERANDS_SP> for timing and area information for instance <MODULUS_2>.<BR>WARNING:Xst:1290 - Hierarchical block <CARRY_REG> is unconnected in block <MY_ADDER>.<BR> It will be removed from the design.<BR>WARNING:Xst:1290 - Hierarchical block <XOUT_REG> is unconnected in block <PIPELINE_STAGES[95].STAGE>.<BR> It will be removed from the design.<BR>WARNING:Xst:1290 - Hierarchical block <QOUT_REG> is unconnected in block <PIPELINE_STAGES[95].STAGE>.<BR> It will be removed from the design.<BR><BR>Synthesizing (advanced) Unit <COUNTER_SYNC_1>.<BR>The following registers are absorbed into counter <COUNT_PROC.STEPS_COUNTER>: 1 register on signal <COUNT_PROC.STEPS_COUNTER>.<BR>Unit <COUNTER_SYNC_1> synthesized (advanced).<BR><BR>Synthesizing (advanced) Unit <COUNTER_SYNC_2>.<BR>The following registers are absorbed into counter <COUNT_PROC.STEPS_COUNTER>: 1 register on signal <COUNT_PROC.STEPS_COUNTER>.<BR>Unit <COUNTER_SYNC_2> synthesized (advanced).<BR><BR>Synthesizing (advanced) Unit <COUNTER_SYNC_3>.<BR>The following registers are absorbed into counter <COUNT_PROC.STEPS_COUNTER_0>: 1 register on signal <COUNT_PROC.STEPS_COUNTER_0>.<BR>Unit <COUNTER_SYNC_3> synthesized (advanced).<BR><BR>Synthesizing (advanced) Unit <MONT_MULTIPLIER>.<BR>INFO:Xst:3031 - HDL ADVISOR - The RAM <MRAM__N0015> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.<BR> -----------------------------------------------------------------------<BR> | ram_type | Distributed | |<BR> -----------------------------------------------------------------------<BR> | Port A |<BR> | aspect ratio | 4-word x 18-bit | |<BR> | weA | connected to signal <GND> | high |<BR> | addrA | connected to signal <P_SEL> | |<BR> | diA | connected to signal <GND> | |<BR> | doA | connected to signal <T_SEL> | |<BR> -----------------------------------------------------------------------<BR>Unit <MONT_MULTIPLIER> synthesized (advanced).<BR><BR>=========================================================================<BR>Advanced HDL Synthesis Report<BR><BR>Macro Statistics<BR># RAMs : 1<BR> 4x18-bit single-port distributed Read Only RAM : 1<BR># Adders/Subtractors : 5<BR> 2-bit subtractor : 1<BR> 3-bit adder : 1<BR> 32-bit subtractor : 2<BR> 4-bit subtractor : 1<BR># Counters : 3<BR> 1-bit up counter : 1<BR> 11-bit up counter : 1<BR> 7-bit up counter : 1<BR># Registers : 3673<BR> Flip-Flops : 3673<BR># Comparators : 2<BR> 32-bit comparator equal : 2<BR># Multiplexers : 3202<BR> 1-bit 16-to-1 multiplexer : 2<BR> 1-bit 2-to-1 multiplexer : 1552<BR> 1-bit 3-to-1 multiplexer : 1<BR> 1-bit 4-to-1 multiplexer : 1539<BR> 16-bit 2-to-1 multiplexer : 96<BR> 2-bit 2-to-1 multiplexer : 4<BR> 3-bit 2-to-1 multiplexer : 2<BR> 32-bit 3-to-1 multiplexer : 1<BR> 4-bit 2-to-1 multiplexer : 4<BR> 6-bit 2-to-1 multiplexer : 1<BR># Xors : 9224<BR> 1-bit xor2 : 9224<BR><BR>=========================================================================<BR><BR>=========================================================================<BR>* Low Level Synthesis *<BR>=========================================================================<BR><BR>Optimizing unit <MOD_SIM_EXP_CORE> ...<BR><BR>Optimizing unit <OPERAND_RAM> ...<BR><BR>Optimizing unit <MODULUS_RAM> ...<BR><BR>Optimizing unit <FIFO_PRIMITIVE> ...<BR><BR>Optimizing unit <MONT_CTRL> ...<BR><BR>Optimizing unit <AUTORUN_CNTRL> ...<BR><BR>Optimizing unit <X_SHIFT_REG> ...<BR><BR>Optimizing unit <SYS_PIPELINE> ...<BR><BR>Optimizing unit <SYS_STAGE> ...<BR><BR>Optimizing unit <ADDER_BLOCK> ...<BR><BR>Optimizing unit <STANDARD_CELL_BLOCK> ...<BR><BR>Optimizing unit <REGISTER_N> ...<BR><BR>Optimizing unit <STEPPING_LOGIC> ...<BR>WARNING:Xst:2677 - Node <THE_MULTIPLIER dout xout_reg pipeline_stages[95].stage systolic_array> of sequential type is unconnected in block <MOD_SIM_EXP_CORE>.<BR>WARNING:Xst:2677 - Node <THE_MULTIPLIER dout pipeline_stages[95].stage systolic_array qout_reg> of sequential type is unconnected in block <MOD_SIM_EXP_CORE>.<BR>WARNING:Xst:2677 - Node <THE_MULTIPLIER dout pipeline_stages[95].stage systolic_array carry_reg my_adder> of sequential type is unconnected in block <MOD_SIM_EXP_CORE>.<BR><BR>Mapping all equations...<BR>Building and optimizing final netlist ...<BR>Found area constraint ratio of 100 (+ 5) on block mod_sim_exp_core, actual ratio is 7.<BR><BR>Final Macro Processing ...<BR><BR>=========================================================================<BR>Final Register Report<BR><BR>Macro Statistics<BR># Registers : 3689<BR> Flip-Flops : 3689<BR><BR>=========================================================================<BR><BR>=========================================================================<BR>* Partition Report *<BR>=========================================================================<BR><BR>Partition Implementation Status<BR>-------------------------------<BR><BR> No Partitions were found in this design.<BR><BR>-------------------------------<BR><BR>=========================================================================<BR>* Design Summary *<BR>=========================================================================<BR><BR>Top Level Output File Name : mod_sim_exp_core.ngc<BR><BR>Primitive and Black Box Usage:<BR>------------------------------<BR># BELS : 10150<BR># GND : 7<BR># INV : 1<BR># LUT2 : 14<BR># LUT3 : 788<BR># LUT4 : 799<BR># LUT5 : 3883<BR># LUT6 : 3864<BR># MUXCY : 10<BR># MUXF7 : 762<BR># MUXF8 : 2<BR># VCC : 7<BR># XORCY : 13<BR># FlipFlops/Latches : 3689<BR># FD : 4<BR># FDC : 1832<BR># FDCE : 1845<BR># FDP : 4<BR># FDPE : 4<BR># RAMS : 97<BR># FIFO18E1 : 1<BR># RAMB36E1 : 96<BR><BR>Device utilization summary:<BR>---------------------------<BR><BR>Selected Device : 6vlx240tff1156-1 <BR><BR><BR>Slice Logic Utilization: <BR> Number of Slice Registers: 3689 out of 301440 1% <BR> Number of Slice LUTs: 9349 out of 150720 6% <BR> Number used as Logic: 9349 out of 150720 6% <BR><BR>Slice Logic Distribution: <BR> Number of LUT Flip Flop pairs used: 9490<BR> Number with an unused Flip Flop: 5801 out of 9490 61% <BR> Number with an unused LUT: 141 out of 9490 1% <BR> Number of fully used LUT-FF pairs: 3548 out of 9490 37% <BR> Number of unique control sets: 108<BR><BR>IO Utilization: <BR> Number of IOs: 124<BR> Number of bonded IOBs: 0 out of 600 0% <BR><BR>Specific Feature Utilization:<BR> Number of Block RAM/FIFO: 97 out of 416 23% <BR> Number using Block RAM only: 96<BR> Number using FIFO only: 1<BR><BR>---------------------------<BR>Partition Resource Summary:<BR>---------------------------<BR><BR> No Partitions were found in this design.<BR><BR>---------------------------<BR><BR><BR>=========================================================================<BR>Timing Report<BR><BR>NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.<BR> FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT<BR> GENERATED AFTER PLACE-and-ROUTE.<BR><BR>Clock Information:<BR>------------------<BR>-----------------------------------+----------------------------------------+-------+<BR>Clock Signal | Clock buffer(FF name) | Load |<BR>-----------------------------------+----------------------------------------+-------+<BR>clk | NONE(the_multiplier/delay_1_cycle/dout)| 3786 |<BR>-----------------------------------+----------------------------------------+-------+<BR>INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.<BR><BR>Asynchronous Control Signals Information:<BR>----------------------------------------<BR>---------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------+<BR>Control Signal | Buffer(FF name) | Load |<BR>---------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------+<BR>the_memory/m_ram/modulus_0/BU2/doutb(0)(the_memory/m_ram/modulus_0/BU2/XST_GND:G)| NONE(the_memory/m_ram/modulus_0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SP.SIMPLE_PRIM36.ram) | 32 |<BR>the_memory/m_ram/modulus_1/BU2/doutb(0)(the_memory/m_ram/modulus_1/BU2/XST_GND:G)| NONE(the_memory/m_ram/modulus_1/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SP.SIMPLE_PRIM36.ram) | 32 |<BR>the_memory/m_ram/modulus_2/BU2/doutb(0)(the_memory/m_ram/modulus_2/BU2/XST_GND:G)| NONE(the_memory/m_ram/modulus_2/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SP.SIMPLE_PRIM36.ram) | 32 |<BR>the_memory/xy_ram/op_0/BU2/rdaddrecc(0)(the_memory/xy_ram/op_0/BU2/XST_GND:G) | NONE(the_memory/xy_ram/op_0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram)| 32 |<BR>the_memory/xy_ram/op_1/BU2/rdaddrecc(0)(the_memory/xy_ram/op_1/BU2/XST_GND:G) | NONE(the_memory/xy_ram/op_1/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram)| 32 |<BR>the_memory/xy_ram/op_2/BU2/rdaddrecc(0)(the_memory/xy_ram/op_2/BU2/XST_GND:G) | NONE(the_memory/xy_ram/op_2/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram)| 32 |<BR>---------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------+<BR><BR>Timing Summary:<BR>---------------<BR>Speed Grade: -1<BR><BR> Minimum period: 5.964ns (Maximum Frequency: 167.673MHz)<BR> Minimum input arrival time before clock: 5.340ns<BR> Maximum output required time after clock: 3.208ns<BR> Maximum combinational path delay: 1.410ns<BR><BR>Timing Details:<BR>---------------<BR>All values displayed in nanoseconds (ns)<BR><BR>=========================================================================<BR>Timing constraint: Default period analysis for Clock 'clk'<BR> Clock period: 5.964ns (frequency: 167.673MHz)<BR> Total number of paths / destination ports: 123290 / 9692<BR>-------------------------------------------------------------------------<BR>Delay: 5.964ns (Levels of Logic = 10)<BR> Source: the_multiplier/systolic_array/pipeline_stages[31].stage/reduction_adder/carry_reg/dout (FF)<BR> Destination: the_memory/xy_ram/op_1/BU2/U0/blk_mem_generator/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram (RAM)<BR> Source Clock: clk rising<BR> Destination Clock: clk rising<BR><BR> Data Path: the_multiplier/systolic_array/pipeline_stages[31].stage/reduction_adder/carry_reg/dout to the_memory/xy_ram/op_1/BU2/U0/blk_mem_generator/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram<BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> FDC:C->Q 3 0.375 0.431 the_multiplier/systolic_array/pipeline_stages[31].stage/reduction_adder/carry_reg/dout (the_multiplier/systolic_array/pipeline_stages[31].stage/reduction_adder/carry_reg/dout)<BR> LUT3:I2->O 2 0.068 0.423 the_multiplier/systolic_array/Mmux_red_cin_stage<32>11 (the_multiplier/systolic_array/red_cin_stage<32>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[1].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<2>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[3].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<4>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[5].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<6>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[7].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<8>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[9].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<10>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[11].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<12>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[13].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<14>)<BR> LUT4:I3->O 1 0.068 0.399 the_multiplier/systolic_array/pipeline_stages[32].stage/Mmux_r61 (r<526>)<BR> begin scope: 'the_memory/xy_ram/op_1'<BR> begin scope: 'BU2'<BR> RAMB36E1:DIBDI0 0.707 U0/blk_mem_generator/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram<BR> ----------------------------------------<BR> Total 5.964ns (1.694ns logic, 4.270ns route)<BR> (28.4% logic, 71.6% route)<BR><BR>=========================================================================<BR>Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'<BR> Total number of paths / destination ports: 15286 / 8029<BR>-------------------------------------------------------------------------<BR>Offset: 5.340ns (Levels of Logic = 10)<BR> Source: p_sel<1> (PAD)<BR> Destination: the_memory/xy_ram/op_1/BU2/U0/blk_mem_generator/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram (RAM)<BR> Destination Clock: clk rising<BR><BR> Data Path: p_sel<1> to the_memory/xy_ram/op_1/BU2/U0/blk_mem_generator/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram<BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> LUT3:I0->O 2 0.068 0.423 the_multiplier/systolic_array/Mmux_red_cin_stage<32>11 (the_multiplier/systolic_array/red_cin_stage<32>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[1].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<2>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[3].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<4>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[5].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<6>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[7].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<8>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[9].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<10>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[11].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<12>)<BR> LUT5:I4->O 3 0.068 0.431 the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/adder_chain[13].adders/cout1 (the_multiplier/systolic_array/pipeline_stages[32].stage/reduction_adder/carry<14>)<BR> LUT4:I3->O 1 0.068 0.399 the_multiplier/systolic_array/pipeline_stages[32].stage/Mmux_r61 (r<526>)<BR> begin scope: 'the_memory/xy_ram/op_1'<BR> begin scope: 'BU2'<BR> RAMB36E1:DIBDI0 0.707 U0/blk_mem_generator/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram<BR> ----------------------------------------<BR> Total 5.340ns (1.501ns logic, 3.839ns route)<BR> (28.1% logic, 71.9% route)<BR><BR>=========================================================================<BR>Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'<BR> Total number of paths / destination ports: 167 / 37<BR>-------------------------------------------------------------------------<BR>Offset: 3.208ns (Levels of Logic = 5)<BR> Source: the_exponent_fifo/FIFO18E1_inst (UNKNOWN)<BR> Destination: ready (PAD)<BR> Source Clock: clk rising<BR><BR> Data Path: the_exponent_fifo/FIFO18E1_inst to ready<BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> FIFO18E1:RDCLK->DO22 1 0.742 0.638 the_exponent_fifo/FIFO18E1_inst (fifo_dout<22>)<BR> LUT6:I2->O 1 0.068 0.000 the_control_unit/autorun_control_logic/Mmux_e1_bit_i_51 (the_control_unit/autorun_control_logic/Mmux_e1_bit_i_51)<BR> MUXF7:I1->O 1 0.248 0.000 the_control_unit/autorun_control_logic/Mmux_e1_bit_i_4_f7 (the_control_unit/autorun_control_logic/Mmux_e1_bit_i_4_f7)<BR> MUXF8:I0->O 6 0.175 0.614 the_control_unit/autorun_control_logic/Mmux_e1_bit_i_2_f8 (the_control_unit/autorun_control_logic/e1_bit_i)<BR> LUT6:I3->O 2 0.068 0.587 the_control_unit/autorun_control_logic/done_i (the_control_unit/auto_done)<BR> LUT3:I0->O 0 0.068 0.000 the_control_unit/done1 (ready)<BR> ----------------------------------------<BR> Total 3.208ns (1.369ns logic, 1.839ns route)<BR> (42.7% logic, 57.3% route)<BR><BR>=========================================================================<BR>Timing constraint: Default path analysis<BR> Total number of paths / destination ports: 70 / 35<BR>-------------------------------------------------------------------------<BR>Delay: 1.410ns (Levels of Logic = 3)<BR> Source: exp_m (PAD)<BR> Destination: ready (PAD)<BR><BR> Data Path: exp_m to ready<BR> Gate Net<BR> Cell:in->out fanout Delay Delay Logical Name (Net Name)<BR> ---------------------------------------- ------------<BR> LUT3:I0->O 4 0.068 0.437 the_control_unit/start_auto1 (the_control_unit/start_auto)<BR> LUT6:I5->O 2 0.068 0.587 the_control_unit/autorun_control_logic/done_i (the_control_unit/auto_done)<BR> LUT3:I0->O 0 0.068 0.000 the_control_unit/done1 (ready)<BR> ----------------------------------------<BR> Total 1.410ns (0.386ns logic, 1.024ns route)<BR> (27.4% logic, 72.6% route)<BR><BR>=========================================================================<BR><BR>Cross Clock Domains Report:<BR>--------------------------<BR><BR>Clock to Setup on destination clock clk<BR>---------------+---------+---------+---------+---------+<BR> | Src:Rise| Src:Fall| Src:Rise| Src:Fall|<BR>Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|<BR>---------------+---------+---------+---------+---------+<BR>clk | 5.964| | | |<BR>---------------+---------+---------+---------+---------+<BR><BR>=========================================================================<BR><BR><BR>Total REAL time to Xst completion: 169.00 secs<BR>Total CPU time to Xst completion: 169.37 secs<BR> <BR>--> <BR><BR>Total memory usage is 382080 kilobytes<BR><BR>Number of errors : 0 ( 0 filtered)<BR>Number of warnings : 8 ( 0 filtered)<BR>Number of infos : 7 ( 0 filtered)<BR><BR></PRE></FONT></BODY></HTML>
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