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/*
 * wrappers.v
 *
 * Copyright (c) 2007 Koen De Vleeschauwer.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */
 
/*
 * Wrappers for dpram and fifos.
 * For each component, two versions are provided: one where read and write port share a common clock;
 * and one where read and write port have independent clocks.
 */
 
`undef DEBUG
//`define DEBUG 1
 
/* check prog_thresh is less than fifo size */
`undef CHECK_FIFO_PARAMS
`ifdef __IVERILOG__
`define CHECK_FIFO_PARAMS 1
`endif
 
/*
 dual-port ram with same clock for read and write port.
 */
 
`include "timescale.v"
 
module dpram_sc (
        rst,
        din,
        clk,
        wr_addr,
        wr_en,
        dout,
        rd_addr,
        rd_en
        );
 
  parameter dta_width=8;           /* Data bus width */
  parameter addr_width=8;          /* Address bus width, determines dpram size by evaluating 2^addr_width */
 
  input                 rst;       /* low active sync master reset */
  input                 clk;       /* clock */
                                   /* read port */
  output reg [dta_width-1:0]dout;      /* data output */
  input                 rd_en;     /* read enable */
  input [addr_width-1:0]rd_addr;   /* read address */
                                   /* write port */
  input  [dta_width-1:0]din;       /* data input */
  input                 wr_en;     /* write enable */
  input [addr_width-1:0]wr_addr;   /* read address */
 
  /*
   * More or less in the style given in XST User Guide v9.1, "RAMs and ROMs Coding Examples",
   * "Verilog Coding Example for Dual Port RAM With Enable On Each Port"
   */
 
  reg    [dta_width-1:0]ram[(1 << addr_width)-1:0];
 
  always @(posedge clk)
    if (rd_en) dout <= ram[rd_addr];
    else dout <= dout;
 
  always @(posedge clk)
    if (wr_en) ram[wr_addr] <= din;
 
endmodule
 
 
/*
 dual-port ram with different clocks for read and write port
 */
 
module dpram_dc (
        din,
        wr_rst,
        wr_clk,
        wr_addr,
        wr_en,
        dout,
        rd_rst,
        rd_clk,
        rd_addr,
        rd_en
        );
 
  parameter dta_width=8;           /* Data bus width */
  parameter addr_width=8;          /* Address bus width, determines dpram size by evaluating 2^addr_width */
 
                                   /* read port */
  output reg [dta_width-1:0]dout;      /* data output */
  input                 rd_rst;    /* low active master reset, sync with read clock */
  input                 rd_clk;    /* read clock */
  input                 rd_en;     /* read enable */
  input [addr_width-1:0]rd_addr;   /* read address */
                                   /* write port */
  input  [dta_width-1:0]din;       /* data input */
  input                 wr_rst;    /* low active master reset, sync with write clock */
  input                 wr_clk;    /* write clock */
  input                 wr_en;     /* write enable */
  input [addr_width-1:0]wr_addr;   /* read address */
 
  reg    [dta_width-1:0]ram[(1 << addr_width)-1:0];
 
  always @(posedge rd_clk)
    if (rd_en) dout <= ram[rd_addr];
    else dout <= dout;
 
  always @(posedge wr_clk)
    if (wr_en) ram[wr_addr] <= din;
 
endmodule
 
/*
 fifo with common clock for read and write port.
 */
 
module fifo_sc (
        clk,
        rst,
        din,
        wr_en,
        full,
        wr_ack,
        overflow,
        prog_full,
        dout,
        rd_en,
        empty,
        valid,
        underflow,
        prog_empty
        );
 
  parameter [8:0]dta_width=9'd8;      /* Data bus width */
  parameter [8:0]addr_width=9'd8;     /* Address bus width, determines fifo size by evaluating 2^addr_width */
  parameter [8:0]prog_thresh=9'd1;    /* Programmable threshold constant for prog_empty and prog_full */
 
  parameter FIFO_XILINX=0;    /* use Xilinx FIFO primitives */
  parameter check_valid=1;    /* assign x's to fifo output when valid is not asserted */
 
  input          clk;
  input          rst;         /* low active sync master reset */
  /* read port */
  output [dta_width-1:0]dout; /* data output */
  input          rd_en;       /* read enable */
  output         empty;       /* asserted if fifo is empty; no additional reads can be performed */
  output         valid;       /* valid (read acknowledge): indicates rd_en was asserted during previous clock cycle and data was succesfully read from fifo and placed on dout */
  output         underflow;   /* underflow (read error): indicates rd_en was asserted during previous clock cycle but no data was read from fifo because fifo was empty */
  output         prog_empty;  /* indicates the fifo has prog_thresh entries, or less. threshold for asserting prog_empty is prog_thresh */
  /* write port */
  input  [dta_width-1:0]din;  /* data input */
  input          wr_en;       /* write enable */
  output         full;        /* asserted if fifo is full; no additional writes can be performed */
  output         overflow;    /* overflow (write error): indicates wr_en was asserted during previous clock cycle but no data was written to fifo because fifo was full */
  output         wr_ack;      /* write acknowledge: indicates wr_en was asserted during previous clock cycle and data was succesfully written to fifo */
  output         prog_full;   /* indicates the fifo has prog_thresh free entries, or less, left. threshold for asserting prog_full is 2^addr_width - prog_thresh */
 
  /* Writing when the fifo is full, or reading while the fifo is empty, does not destroy the contents of the fifo. */
 
  /* Implementation using "soft" fifo */
  xfifo_sc #(
    .dta_width(dta_width),
    .addr_width(addr_width),
    .prog_thresh(prog_thresh)
    )
  xfifo_sc (
    .clk(clk),
    .rst(rst),
    .din(din),
    .wr_en(wr_en),
    .full(full),
    .wr_ack(wr_ack),
    .overflow(overflow),
    .prog_full(prog_full),
    .dout(dout),
    .rd_en(rd_en),
    .empty(empty),
    .valid(valid),
    .underflow(underflow),
    .prog_empty(prog_empty)
    );
 
`ifdef DEBUG
  always @(posedge clk)
    $strobe("%m\tread: %h dout: %h", fifo_valid, dout);
`endif
 
`ifdef CHECK_FIFO_PARAMS
  initial #0
      begin
        if (prog_thresh > (1<<addr_width))
          begin
            #0 $display ("%m\t*** error: inconsistent fifo parameters. addr_width: %d prog_thresh: %d. ***", addr_width, prog_thresh);
            $finish;
          end
      end
 
  always @(posedge clk)
    if (overflow)
      begin
        #0 $display ("%m\t*** error: fifo overflow. ***");
      end
/*
  always @(posedge clk)
    if (underflow)
      begin
        #0 $display ("%m\t*** warning: fifo underflow. ***");
      end
*/
`endif
 
endmodule
 
/*
 fifo with independent clock for read and write port.
 */
 
module fifo_dc (
        rst,
        wr_clk,
        din,
        wr_en,
        full,
        wr_ack,
        overflow,
        prog_full,
        rd_clk,
        dout,
        rd_en,
        empty,
        valid,
        underflow,
        prog_empty
        );
 
  parameter [8:0]dta_width=9'd8;      /* Data bus width */
  parameter [8:0]addr_width=9'd8;     /* Address bus width, determines fifo size by evaluating 2^addr_width */
  parameter [8:0]prog_thresh=9'd1;    /* Programmable threshold constant for prog_empty and prog_full */
 
  parameter FIFO_XILINX=0;    /* use Xilinx FIFO primitives */
  parameter check_valid=1;    /* assign x's to fifo output when valid is not asserted */
 
  input          rst;         /* low active sync master reset */
  /* read port */
  input          rd_clk;      /* read clock. positive edge active */
  output [dta_width-1:0]dout; /* data output */
  input          rd_en;       /* read enable */
  output         empty;       /* asserted if fifo is empty; no additional reads can be performed */
  output         valid;       /* valid (read acknowledge): indicates rd_en was asserted during previous clock cycle and data was succesfully read from fifo and placed on dout */
  output         underflow;   /* underflow (read error): indicates rd_en was asserted during previous clock cycle but no data was read from fifo because fifo was empty */
  output         prog_empty;  /* indicates the fifo has prog_thresh entries, or less. threshold for asserting prog_empty is prog_thresh */
  /* write port */
  input          wr_clk;      /* write clock. positive edge active */
  input  [dta_width-1:0]din;  /* data input */
  input          wr_en;       /* write enable */
  output         full;        /* asserted if fifo is full; no additional writes can be performed */
  output         overflow;    /* overflow (write error): indicates wr_en was asserted during previous clock cycle but no data was written to fifo because fifo was full */
  output         wr_ack;      /* write acknowledge: indicates wr_en was asserted during previous clock cycle and data was succesfully written to fifo */
  output         prog_full;   /* indicates the fifo has prog_thresh free entries, or less, left. threshold for asserting prog_full is 2^addr_width - prog_thresh  */
 
  /* Writing when the fifo is full, or reading while the fifo is empty, does not destroy the contents of the fifo. */
 
  /* Implementation using opencores generic_fifo */
  wire           fifo_full;
  wire           fifo_empty;
  wire           fifo_full_n;
  wire           fifo_empty_n;
 
  reg            fifo_valid;
  reg            fifo_underflow;
  reg            fifo_wr_ack;
  reg            fifo_overflow;
 
  assign empty = fifo_empty;
  assign full = fifo_full;
  assign prog_empty = fifo_empty_n;
  assign prog_full = fifo_full_n;
  assign valid = fifo_valid;
  assign underflow = fifo_underflow;
  assign wr_ack = fifo_wr_ack;
  assign overflow = fifo_overflow;
 
  always @(posedge rd_clk)
    if (~rst) fifo_valid <= 1'b0;
    else fifo_valid <= rd_en && ~fifo_empty;
 
  always @(posedge rd_clk)
    if (~rst) fifo_underflow <= 1'b0;
    else fifo_underflow <= rd_en && fifo_empty;
 
  always @(posedge wr_clk)
    if (~rst) fifo_wr_ack <= 1'b0;
    else fifo_wr_ack <= wr_en && ~fifo_full;
 
  always @(posedge wr_clk)
    if (~rst) fifo_overflow <= 1'b0;
    else fifo_overflow <= wr_en && fifo_full;
 
  generic_fifo_dc
    #(.aw(addr_width),
    .dw(dta_width),
    .n(prog_thresh))
    gfifo_dc (
    .rd_clk(rd_clk),
    .wr_clk(wr_clk),
    .rst(rst),
    .clr(1'b0),
    .din(din),
    .we(wr_en && ~fifo_full),
    .dout(dout),
    .re(rd_en && ~fifo_empty),
    .full(fifo_full),
    .empty(fifo_empty),
    .full_n(fifo_full_n),
    .empty_n(fifo_empty_n),
    .level()
    );
 
`ifdef DEBUG
  always @(posedge rd_clk)
    $strobe("%m\tread: %h dout: %h", fifo_valid, dout);
`endif
 
`ifdef CHECK_FIFO_PARAMS
  initial #0
      begin
        if (prog_thresh > (1<<addr_width))
          begin
            #0 $display ("%m\t*** error: inconsistent fifo parameters. addr_width: %d prog_thresh: %d. ***", addr_width, prog_thresh);
            $finish;
          end
      end
 
  always @(posedge wr_clk)
    if (fifo_overflow)
      begin
        #0 $display ("%m\t*** error: fifo overflow. ***");
      end
/*
  always @(posedge rd_clk)
    if (fifo_underflow)
      begin
        #0 $display ("%m\t*** warning: fifo underflow. ***");
      end
*/
`endif
endmodule
/* not truncated */

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Subversion Repositories mpeg2fpga

[/] [mpeg2fpga/] [trunk/] [bench/] [iverilog/] [wrappers.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	kdv	`/*`
2			`* wrappers.v`
3			`*`
4			`* Copyright (c) 2007 Koen De Vleeschauwer.`
5			`*`
6			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
7			`* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE`
8			`* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE`
9			`* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE`
10			`* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL`
11			`* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS`
12			`* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)`
13			`* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT`
14			`* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY`
15			`* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF`
16			`* SUCH DAMAGE.`
17			`*/`
18
19			`/*`
20			`* Wrappers for dpram and fifos.`
21			`* For each component, two versions are provided: one where read and write port share a common clock;`
22			`* and one where read and write port have independent clocks.`
23			`*/`
24
25			`undef DEBUG
26			//`define DEBUG 1
27
28			`/* check prog_thresh is less than fifo size */`
29			`undef CHECK_FIFO_PARAMS
30			`ifdef __IVERILOG__
31			`define CHECK_FIFO_PARAMS 1
32			`endif
33
34			`/*`
35			`dual-port ram with same clock for read and write port.`
36			`*/`
37
38			`include "timescale.v"
39
40			`module dpram_sc (`
41			`rst,`
42			`din,`
43			`clk,`
44			`wr_addr,`
45			`wr_en,`
46			`dout,`
47			`rd_addr,`
48			`rd_en`
49			`);`
50
51			`parameter dta_width=8; /* Data bus width */`
52			`parameter addr_width=8; /* Address bus width, determines dpram size by evaluating 2^addr_width */`
53
54			`input rst; /* low active sync master reset */`
55			`input clk; /* clock */`
56			`/* read port */`
57			`output reg [dta_width-1:0]dout; /* data output */`
58			`input rd_en; /* read enable */`
59			`input [addr_width-1:0]rd_addr; /* read address */`
60			`/* write port */`
61			`input [dta_width-1:0]din; /* data input */`
62			`input wr_en; /* write enable */`
63			`input [addr_width-1:0]wr_addr; /* read address */`
64
65			`/*`
66			`* More or less in the style given in XST User Guide v9.1, "RAMs and ROMs Coding Examples",`
67			`* "Verilog Coding Example for Dual Port RAM With Enable On Each Port"`
68			`*/`
69
70			`reg [dta_width-1:0]ram[(1 << addr_width)-1:0];`
71
72			`always @(posedge clk)`
73			`if (rd_en) dout <= ram[rd_addr];`
74			`else dout <= dout;`
75
76			`always @(posedge clk)`
77			`if (wr_en) ram[wr_addr] <= din;`
78
79			`endmodule`
80
81
82			`/*`
83			`dual-port ram with different clocks for read and write port`
84			`*/`
85
86			`module dpram_dc (`
87			`din,`
88			`wr_rst,`
89			`wr_clk,`
90			`wr_addr,`
91			`wr_en,`
92			`dout,`
93			`rd_rst,`
94			`rd_clk,`
95			`rd_addr,`
96			`rd_en`
97			`);`
98
99			`parameter dta_width=8; /* Data bus width */`
100			`parameter addr_width=8; /* Address bus width, determines dpram size by evaluating 2^addr_width */`
101
102			`/* read port */`
103			`output reg [dta_width-1:0]dout; /* data output */`
104			`input rd_rst; /* low active master reset, sync with read clock */`
105			`input rd_clk; /* read clock */`
106			`input rd_en; /* read enable */`
107			`input [addr_width-1:0]rd_addr; /* read address */`
108			`/* write port */`
109			`input [dta_width-1:0]din; /* data input */`
110			`input wr_rst; /* low active master reset, sync with write clock */`
111			`input wr_clk; /* write clock */`
112			`input wr_en; /* write enable */`
113			`input [addr_width-1:0]wr_addr; /* read address */`
114
115			`reg [dta_width-1:0]ram[(1 << addr_width)-1:0];`
116
117			`always @(posedge rd_clk)`
118			`if (rd_en) dout <= ram[rd_addr];`
119			`else dout <= dout;`
120
121			`always @(posedge wr_clk)`
122			`if (wr_en) ram[wr_addr] <= din;`
123
124			`endmodule`
125
126			`/*`
127			`fifo with common clock for read and write port.`
128			`*/`
129
130			`module fifo_sc (`
131			`clk,`
132			`rst,`
133			`din,`
134			`wr_en,`
135			`full,`
136			`wr_ack,`
137			`overflow,`
138			`prog_full,`
139			`dout,`
140			`rd_en,`
141			`empty,`
142			`valid,`
143			`underflow,`
144			`prog_empty`
145			`);`
146
147			`parameter [8:0]dta_width=9'd8; /* Data bus width */`
148			`parameter [8:0]addr_width=9'd8; /* Address bus width, determines fifo size by evaluating 2^addr_width */`
149			`parameter [8:0]prog_thresh=9'd1; /* Programmable threshold constant for prog_empty and prog_full */`
150
151			`parameter FIFO_XILINX=0; /* use Xilinx FIFO primitives */`
152			`parameter check_valid=1; /* assign x's to fifo output when valid is not asserted */`
153
154			`input clk;`
155			`input rst; /* low active sync master reset */`
156			`/* read port */`
157			`output [dta_width-1:0]dout; /* data output */`
158			`input rd_en; /* read enable */`
159			`output empty; /* asserted if fifo is empty; no additional reads can be performed */`
160			`output valid; /* valid (read acknowledge): indicates rd_en was asserted during previous clock cycle and data was succesfully read from fifo and placed on dout */`
161			`output underflow; /* underflow (read error): indicates rd_en was asserted during previous clock cycle but no data was read from fifo because fifo was empty */`
162			`output prog_empty; /* indicates the fifo has prog_thresh entries, or less. threshold for asserting prog_empty is prog_thresh */`
163			`/* write port */`
164			`input [dta_width-1:0]din; /* data input */`
165			`input wr_en; /* write enable */`
166			`output full; /* asserted if fifo is full; no additional writes can be performed */`
167			`output overflow; /* overflow (write error): indicates wr_en was asserted during previous clock cycle but no data was written to fifo because fifo was full */`
168			`output wr_ack; /* write acknowledge: indicates wr_en was asserted during previous clock cycle and data was succesfully written to fifo */`
169			`output prog_full; /* indicates the fifo has prog_thresh free entries, or less, left. threshold for asserting prog_full is 2^addr_width - prog_thresh */`
170
171			`/* Writing when the fifo is full, or reading while the fifo is empty, does not destroy the contents of the fifo. */`
172
173			`/* Implementation using "soft" fifo */`
174			`xfifo_sc #(`
175			`.dta_width(dta_width),`
176			`.addr_width(addr_width),`
177			`.prog_thresh(prog_thresh)`
178			`)`
179			`xfifo_sc (`
180			`.clk(clk),`
181			`.rst(rst),`
182			`.din(din),`
183			`.wr_en(wr_en),`
184			`.full(full),`
185			`.wr_ack(wr_ack),`
186			`.overflow(overflow),`
187			`.prog_full(prog_full),`
188			`.dout(dout),`
189			`.rd_en(rd_en),`
190			`.empty(empty),`
191			`.valid(valid),`
192			`.underflow(underflow),`
193			`.prog_empty(prog_empty)`
194			`);`
195
196			`ifdef DEBUG
197			`always @(posedge clk)`
198			`$strobe("%m\tread: %h dout: %h", fifo_valid, dout);`
199			`endif
200
201			`ifdef CHECK_FIFO_PARAMS
202			`initial #0`
203			`begin`
204			`if (prog_thresh > (1<<addr_width))`
205			`begin`
206			`#0 $display ("%m\t* error: inconsistent fifo parameters. addr_width: %d prog_thresh: %d. *", addr_width, prog_thresh);`
207			`$finish;`
208			`end`
209			`end`
210
211			`always @(posedge clk)`
212			`if (overflow)`
213			`begin`
214			`#0 $display ("%m\t* error: fifo overflow. *");`
215			`end`
216			`/*`
217			`always @(posedge clk)`
218			`if (underflow)`
219			`begin`
220			`#0 $display ("%m\t* warning: fifo underflow. *");`
221			`end`
222			`*/`
223			`endif
224
225			`endmodule`
226
227			`/*`
228			`fifo with independent clock for read and write port.`
229			`*/`
230
231			`module fifo_dc (`
232			`rst,`
233			`wr_clk,`
234			`din,`
235			`wr_en,`
236			`full,`
237			`wr_ack,`
238			`overflow,`
239			`prog_full,`
240			`rd_clk,`
241			`dout,`
242			`rd_en,`
243			`empty,`
244			`valid,`
245			`underflow,`
246			`prog_empty`
247			`);`
248
249			`parameter [8:0]dta_width=9'd8; /* Data bus width */`
250			`parameter [8:0]addr_width=9'd8; /* Address bus width, determines fifo size by evaluating 2^addr_width */`
251			`parameter [8:0]prog_thresh=9'd1; /* Programmable threshold constant for prog_empty and prog_full */`
252
253			`parameter FIFO_XILINX=0; /* use Xilinx FIFO primitives */`
254			`parameter check_valid=1; /* assign x's to fifo output when valid is not asserted */`
255
256			`input rst; /* low active sync master reset */`
257			`/* read port */`
258			`input rd_clk; /* read clock. positive edge active */`
259			`output [dta_width-1:0]dout; /* data output */`
260			`input rd_en; /* read enable */`
261			`output empty; /* asserted if fifo is empty; no additional reads can be performed */`
262			`output valid; /* valid (read acknowledge): indicates rd_en was asserted during previous clock cycle and data was succesfully read from fifo and placed on dout */`
263			`output underflow; /* underflow (read error): indicates rd_en was asserted during previous clock cycle but no data was read from fifo because fifo was empty */`
264			`output prog_empty; /* indicates the fifo has prog_thresh entries, or less. threshold for asserting prog_empty is prog_thresh */`
265			`/* write port */`
266			`input wr_clk; /* write clock. positive edge active */`
267			`input [dta_width-1:0]din; /* data input */`
268			`input wr_en; /* write enable */`
269			`output full; /* asserted if fifo is full; no additional writes can be performed */`
270			`output overflow; /* overflow (write error): indicates wr_en was asserted during previous clock cycle but no data was written to fifo because fifo was full */`
271			`output wr_ack; /* write acknowledge: indicates wr_en was asserted during previous clock cycle and data was succesfully written to fifo */`
272			`output prog_full; /* indicates the fifo has prog_thresh free entries, or less, left. threshold for asserting prog_full is 2^addr_width - prog_thresh */`
273
274			`/* Writing when the fifo is full, or reading while the fifo is empty, does not destroy the contents of the fifo. */`
275
276			`/* Implementation using opencores generic_fifo */`
277			`wire fifo_full;`
278			`wire fifo_empty;`
279			`wire fifo_full_n;`
280			`wire fifo_empty_n;`
281
282			`reg fifo_valid;`
283			`reg fifo_underflow;`
284			`reg fifo_wr_ack;`
285			`reg fifo_overflow;`
286
287			`assign empty = fifo_empty;`
288			`assign full = fifo_full;`
289			`assign prog_empty = fifo_empty_n;`
290			`assign prog_full = fifo_full_n;`
291			`assign valid = fifo_valid;`
292			`assign underflow = fifo_underflow;`
293			`assign wr_ack = fifo_wr_ack;`
294			`assign overflow = fifo_overflow;`
295
296			`always @(posedge rd_clk)`
297			`if (~rst) fifo_valid <= 1'b0;`
298			`else fifo_valid <= rd_en && ~fifo_empty;`
299
300			`always @(posedge rd_clk)`
301			`if (~rst) fifo_underflow <= 1'b0;`
302			`else fifo_underflow <= rd_en && fifo_empty;`
303
304			`always @(posedge wr_clk)`
305			`if (~rst) fifo_wr_ack <= 1'b0;`
306			`else fifo_wr_ack <= wr_en && ~fifo_full;`
307
308			`always @(posedge wr_clk)`
309			`if (~rst) fifo_overflow <= 1'b0;`
310			`else fifo_overflow <= wr_en && fifo_full;`
311
312			`generic_fifo_dc`
313			`#(.aw(addr_width),`
314			`.dw(dta_width),`
315			`.n(prog_thresh))`
316			`gfifo_dc (`
317			`.rd_clk(rd_clk),`
318			`.wr_clk(wr_clk),`
319			`.rst(rst),`
320			`.clr(1'b0),`
321			`.din(din),`
322			`.we(wr_en && ~fifo_full),`
323			`.dout(dout),`
324			`.re(rd_en && ~fifo_empty),`
325			`.full(fifo_full),`
326			`.empty(fifo_empty),`
327			`.full_n(fifo_full_n),`
328			`.empty_n(fifo_empty_n),`
329			`.level()`
330			`);`
331
332			`ifdef DEBUG
333			`always @(posedge rd_clk)`
334			`$strobe("%m\tread: %h dout: %h", fifo_valid, dout);`
335			`endif
336
337			`ifdef CHECK_FIFO_PARAMS
338			`initial #0`
339			`begin`
340			`if (prog_thresh > (1<<addr_width))`
341			`begin`
342			`#0 $display ("%m\t* error: inconsistent fifo parameters. addr_width: %d prog_thresh: %d. *", addr_width, prog_thresh);`
343			`$finish;`
344			`end`
345			`end`
346
347			`always @(posedge wr_clk)`
348			`if (fifo_overflow)`
349			`begin`
350			`#0 $display ("%m\t* error: fifo overflow. *");`
351			`end`
352			`/*`
353			`always @(posedge rd_clk)`
354			`if (fifo_underflow)`
355			`begin`
356			`#0 $display ("%m\t* warning: fifo underflow. *");`
357			`end`
358			`*/`
359			`endif
360			`endmodule`
361			`/* not truncated */`