OpenCores
URL https://opencores.org/ocsvn/mpeg2fpga/mpeg2fpga/trunk

Subversion Repositories mpeg2fpga

[/] [mpeg2fpga/] [trunk/] [rtl/] [mpeg2/] [fwft.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 kdv
/*
2
 * fwft.v
3
 *
4
 * Copyright (c) 2007 Koen De Vleeschauwer.
5
 *
6
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
7
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
8
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
9
 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
10
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
11
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
12
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
14
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
15
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
16
 * SUCH DAMAGE.
17
 */
18
 
19
/*
20
 * fwft.v - convert standard fifo in first-word fall-through fifo.
21
 */
22
 
23
`include "timescale.v"
24
 
25
`undef DEBUG
26
//`define DEBUG 1
27
 
28
/*
29
 * Converts a normal fifo to a a first-word fall-through fifo.
30
 * Does not change data width: output data has same width as input data.
31
 */
32
 
33
module fwft_reader (rst, clk, clk_en,
34
                    fifo_rd_en, fifo_valid, fifo_dout,
35
                    valid, dout, rd_en);
36
 
37
  parameter [8:0]dta_width=9'd8;
38
 
39
  input                 rst;
40
  input                 clk;
41
  input                 clk_en;
42
  output reg            fifo_rd_en;
43
  input                 fifo_valid;
44
  input  [dta_width-1:0]fifo_dout;
45
  output                valid;
46
  output [dta_width-1:0]dout;
47
  input                 rd_en;
48
 
49
  reg    [dta_width-1:0]dta_0;
50
  reg    [dta_width-1:0]next_dta_0;
51
  reg                   dta_0_valid;
52
  reg                   next_dta_0_valid;
53
 
54
  reg    [dta_width-1:0]dta_1;
55
  reg    [dta_width-1:0]next_dta_1;
56
  reg                   dta_1_valid;
57
  reg                   next_dta_1_valid;
58
 
59
  reg    [dta_width-1:0]dta_2;
60
  reg    [dta_width-1:0]next_dta_2;
61
  reg                   dta_2_valid;
62
  reg                   next_dta_2_valid;
63
 
64
  /* keep reading until dta_1 valid */
65
  always @(posedge clk)
66
    if (~rst) fifo_rd_en <= 1'b0;
67
    else if (clk_en) fifo_rd_en <= ~next_dta_1_valid;
68
 
69
  /* outputs */
70
  assign valid = dta_0_valid;
71
  assign dout  = dta_0;
72
 
73
  /* writing data */
74
  always @*
75
    if (fifo_valid && ~dta_0_valid && ~dta_1_valid && ~dta_2_valid)
76
      begin
77
        next_dta_0 = fifo_dout;
78
        next_dta_0_valid = fifo_valid;
79
      end
80
    else
81
      begin
82
        next_dta_0 = dta_0;
83
        next_dta_0_valid = dta_0_valid;
84
      end
85
 
86
  always @*
87
    if (fifo_valid &&  dta_0_valid && ~dta_1_valid && ~dta_2_valid)
88
      begin
89
        next_dta_1 = fifo_dout;
90
        next_dta_1_valid = fifo_valid;
91
      end
92
    else
93
      begin
94
        next_dta_1 = dta_1;
95
        next_dta_1_valid = dta_1_valid;
96
      end
97
 
98
  always @*
99
    if (fifo_valid &&  dta_0_valid &&  dta_1_valid && ~dta_2_valid)
100
      begin
101
        next_dta_2 = fifo_dout;
102
        next_dta_2_valid = fifo_valid;
103
      end
104
    else
105
      begin
106
        next_dta_2 = dta_2;
107
        next_dta_2_valid = dta_2_valid;
108
      end
109
 
110
  /* reading data */
111
  always @(posedge clk)
112
    if (~rst)
113
      begin
114
        dta_0 <= {dta_width{1'b0}};
115
        dta_1 <= {dta_width{1'b0}};
116
        dta_2 <= {dta_width{1'b0}};
117
        dta_0_valid <= 1'b0;
118
        dta_1_valid <= 1'b0;
119
        dta_2_valid <= 1'b0;
120
      end
121
    else if (clk_en && rd_en && valid) /* discard rd_en if dout not valid */
122
      begin
123
        dta_0 <= next_dta_1;
124
        dta_1 <= next_dta_2;
125
        dta_2 <= {dta_width{1'b0}};
126
        dta_0_valid <= next_dta_1_valid;
127
        dta_1_valid <= next_dta_2_valid;
128
        dta_2_valid <= 1'b0;
129
      end
130
    else if (clk_en)
131
      begin
132
        dta_0 <= next_dta_0;
133
        dta_1 <= next_dta_1;
134
        dta_2 <= next_dta_2;
135
        dta_0_valid <= next_dta_0_valid;
136
        dta_1_valid <= next_dta_1_valid;
137
        dta_2_valid <= next_dta_2_valid;
138
      end
139
    else
140
      begin
141
        dta_0 <= dta_0;
142
        dta_1 <= dta_1;
143
        dta_2 <= dta_2;
144
        dta_0_valid <= dta_0_valid;
145
        dta_1_valid <= dta_1_valid;
146
        dta_2_valid <= dta_2_valid;
147
      end
148
 
149
`ifdef DEBUG
150
  always @(posedge clk)
151
    if (clk_en)
152
      begin
153
        $strobe("%m\tdout: %h valid: %h rd_en: %h fifo_dout: %h fifo_valid: %h fifo_rd_en: %h",
154
                     dout, valid, rd_en, fifo_dout, fifo_valid, fifo_rd_en);
155
        $strobe("%m\tdta_0: %h dta_0_valid: %h dta_1: %h dta_1_valid: %h dta_2: %h dta_2_valid: %h",
156
                     dta_0, dta_0_valid, dta_1, dta_1_valid, dta_2, dta_2_valid)
157
      end
158
`endif
159
 
160
endmodule
161
 
162
 
163
/*
164
 * Converts a normal fifo to a a first-word fall-through fifo.
165
 * Converts data width: output data is 2 times as wide as input data.
166
 */
167
 
168
module fwft2_reader (rst, clk, clk_en,
169
                    fifo_rd_en, fifo_valid, fifo_dout,
170
                    valid, dout, rd_en);
171
 
172
  parameter [8:0]dta_width=9'd8;
173
 
174
  input                 rst;
175
  input                 clk;
176
  input                 clk_en;
177
  output reg            fifo_rd_en;
178
  input                 fifo_valid;
179
  input  [dta_width-1:0]fifo_dout;
180
  output                valid;
181
  output [2*dta_width-1:0]dout;
182
  input                 rd_en;
183
 
184
  reg    [dta_width-1:0]dta_0;
185
  reg    [dta_width-1:0]next_dta_0;
186
  reg                   dta_0_valid;
187
  reg                   next_dta_0_valid;
188
 
189
  reg    [dta_width-1:0]dta_1;
190
  reg    [dta_width-1:0]next_dta_1;
191
  reg                   dta_1_valid;
192
  reg                   next_dta_1_valid;
193
 
194
  reg    [dta_width-1:0]dta_2;
195
  reg    [dta_width-1:0]next_dta_2;
196
  reg                   dta_2_valid;
197
  reg                   next_dta_2_valid;
198
 
199
  reg    [dta_width-1:0]dta_3;
200
  reg    [dta_width-1:0]next_dta_3;
201
  reg                   dta_3_valid;
202
  reg                   next_dta_3_valid;
203
 
204
  reg    [dta_width-1:0]dta_4;
205
  reg    [dta_width-1:0]next_dta_4;
206
  reg                   dta_4_valid;
207
  reg                   next_dta_4_valid;
208
 
209
  /* keep reading until dta_3 valid */
210
  always @(posedge clk)
211
    if (~rst) fifo_rd_en <= 1'b0;
212
    else if (clk_en) fifo_rd_en <= ~next_dta_3_valid;
213
 
214
  /* outputs */
215
  assign valid = dta_1_valid;
216
  assign dout  = {dta_0, dta_1};
217
 
218
  /* writing data */
219
  always @*
220
    if (fifo_valid && ~dta_0_valid && ~dta_1_valid && ~dta_2_valid && ~dta_3_valid && ~dta_4_valid)
221
      begin
222
        next_dta_0 = fifo_dout;
223
        next_dta_0_valid = fifo_valid;
224
      end
225
    else
226
      begin
227
        next_dta_0 = dta_0;
228
        next_dta_0_valid = dta_0_valid;
229
      end
230
 
231
  always @*
232
    if (fifo_valid &&  dta_0_valid && ~dta_1_valid && ~dta_2_valid && ~dta_3_valid && ~dta_4_valid)
233
      begin
234
        next_dta_1 = fifo_dout;
235
        next_dta_1_valid = fifo_valid;
236
      end
237
    else
238
      begin
239
        next_dta_1 = dta_1;
240
        next_dta_1_valid = dta_1_valid;
241
      end
242
 
243
  always @*
244
    if (fifo_valid &&  dta_0_valid &&  dta_1_valid && ~dta_2_valid && ~dta_3_valid && ~dta_4_valid)
245
      begin
246
        next_dta_2 = fifo_dout;
247
        next_dta_2_valid = fifo_valid;
248
      end
249
    else
250
      begin
251
        next_dta_2 = dta_2;
252
        next_dta_2_valid = dta_2_valid;
253
      end
254
 
255
  always @*
256
    if (fifo_valid &&  dta_0_valid &&  dta_1_valid &&  dta_2_valid && ~dta_3_valid && ~dta_4_valid)
257
      begin
258
        next_dta_3 = fifo_dout;
259
        next_dta_3_valid = fifo_valid;
260
      end
261
    else
262
      begin
263
        next_dta_3 = dta_3;
264
        next_dta_3_valid = dta_3_valid;
265
      end
266
 
267
  always @*
268
    if (fifo_valid &&  dta_0_valid &&  dta_1_valid &&  dta_2_valid &&  dta_3_valid && ~dta_4_valid)
269
      begin
270
        next_dta_4 = fifo_dout;
271
        next_dta_4_valid = fifo_valid;
272
      end
273
    else
274
      begin
275
        next_dta_4 = dta_4;
276
        next_dta_4_valid = dta_4_valid;
277
      end
278
 
279
  /* reading data */
280
  always @(posedge clk)
281
    if (~rst)
282
      begin
283
        dta_0 <= {dta_width{1'b0}};
284
        dta_1 <= {dta_width{1'b0}};
285
        dta_2 <= {dta_width{1'b0}};
286
        dta_3 <= {dta_width{1'b0}};
287
        dta_4 <= {dta_width{1'b0}};
288
        dta_0_valid <= 1'b0;
289
        dta_1_valid <= 1'b0;
290
        dta_2_valid <= 1'b0;
291
        dta_3_valid <= 1'b0;
292
        dta_4_valid <= 1'b0;
293
      end
294
    else if (clk_en && rd_en && valid) /* discard rd_en if dout not valid */
295
      begin
296
        dta_0 <= next_dta_2;
297
        dta_1 <= next_dta_3;
298
        dta_2 <= next_dta_4;
299
        dta_3 <= {dta_width{1'b0}};
300
        dta_4 <= {dta_width{1'b0}};
301
        dta_0_valid <= next_dta_2_valid;
302
        dta_1_valid <= next_dta_3_valid;
303
        dta_2_valid <= next_dta_4_valid;
304
        dta_3_valid <= 1'b0;
305
        dta_4_valid <= 1'b0;
306
      end
307
    else if (clk_en)
308
      begin
309
        dta_0 <= next_dta_0;
310
        dta_1 <= next_dta_1;
311
        dta_2 <= next_dta_2;
312
        dta_3 <= next_dta_3;
313
        dta_4 <= next_dta_4;
314
        dta_0_valid <= next_dta_0_valid;
315
        dta_1_valid <= next_dta_1_valid;
316
        dta_2_valid <= next_dta_2_valid;
317
        dta_3_valid <= next_dta_3_valid;
318
        dta_4_valid <= next_dta_4_valid;
319
      end
320
    else
321
      begin
322
        dta_0 <= dta_0;
323
        dta_1 <= dta_1;
324
        dta_2 <= dta_2;
325
        dta_3 <= dta_3;
326
        dta_4 <= dta_4;
327
        dta_0_valid <= dta_0_valid;
328
        dta_1_valid <= dta_1_valid;
329
        dta_2_valid <= dta_2_valid;
330
        dta_3_valid <= dta_3_valid;
331
        dta_4_valid <= dta_4_valid;
332
      end
333
 
334
`ifdef DEBUG
335
  always @(posedge clk)
336
    if (clk_en)
337
      begin
338
        $strobe("%m\tdout: %h valid: %h rd_en: %h fifo_dout: %h fifo_valid: %h fifo_rd_en: %h",
339
                     dout, valid, rd_en, fifo_dout, fifo_valid, fifo_rd_en);
340
        $strobe("%m\tdta_0: %h dta_0_valid: %h dta_1: %h dta_1_valid: %h dta_2: %h dta_2_valid: %h dta_3: %h dta_3_valid: %h dta_4: %h dta_4_valid: %h",
341
                     dta_0, dta_0_valid, dta_1, dta_1_valid, dta_2, dta_2_valid, dta_3, dta_3_valid, dta_4, dta_4_valid);
342
      end
343
`endif
344
endmodule
345
/* not truncated */

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.