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[/] [mpeg2fpga/] [trunk/] [rtl/] [mpeg2/] [getbits.v] - Blame information for rev 2

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1 2 kdv
/*
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 * getbits.v
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 *
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 * Copyright (c) 2007 Koen De Vleeschauwer.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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 * SUCH DAMAGE.
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 */
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/*
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 * getbits - read bitfields from incoming video stream
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 */
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`include "timescale.v"
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`undef DEBUG
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//`define DEBUG 1
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module getbits_fifo (clk, clk_en, rst,
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   vid_in, vid_in_rd_en, vid_in_rd_valid,
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   advance, align,
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   getbits, signbit, getbits_valid,
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   wait_state, rld_wr_almost_full, mvec_wr_almost_full, motcomp_busy, vld_en);
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  input            clk;                      // clock
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  input            clk_en;                   // clock enable
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  input            rst;                      // synchronous active low reset
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  input      [63:0]vid_in;
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  output reg       vid_in_rd_en;
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  input            vid_in_rd_valid;
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  input       [4:0]advance;                  // number of bits to advance the bitstream (advance <= 24). Enabled when getbits_valid asserted.
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  input            align;                    // byte-align getbits and move forward one byte. Enabled when getbits_valid asserted.
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  input            wait_state;               // asserted if vld needs to be frozen next clock cycle.
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  input            rld_wr_almost_full;       // asserted if rld fifo almost full
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  input            mvec_wr_almost_full;      // asserted if motion vector fifo almost full
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  input            motcomp_busy;             // asserted if motcomp fifo almost full
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  output reg [23:0]getbits;                  // bit-aligned elementary stream data. 
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  output reg       signbit;                  // In table B-14 and B-15, the rightmost bit of the variable length code is the sign bit.
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                                             // When decoding DCT variable length codes, signbit contains the sign bit of the
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                                             // previous clock's coefficient.
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  output reg       getbits_valid;            // getbits_valid is asserted when getbits is valid.
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  output reg       vld_en;                   // vld clock enable
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  reg       [128:0]dta;                      // 129 bits. No typo.
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  reg       [103:0]dummy;                    // dummy variable, not used.
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  reg         [7:0]cursor;
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  reg       [128:0]next_dta;
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  reg         [7:0]next_cursor;
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  reg        [23:0]next_getbits;
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  reg              next_signbit;
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  parameter
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    STATE_INIT      = 1'b0,
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    STATE_READY     = 1'b1;
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  reg               state;
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  reg               next;
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  /* next state logic */
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  always @*
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    case (state)
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      STATE_INIT:  if (vid_in_rd_valid && (next_cursor < 8'd64)) next = STATE_READY;
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                   else next = STATE_INIT;
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      STATE_READY: if (next_cursor > 63) next = STATE_INIT;
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                   else next = STATE_READY;
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      default      next = STATE_INIT;
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    endcase
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  /* state */
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  always @(posedge clk)
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    if(~rst) state <= STATE_INIT;
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    else if (clk_en) state <= next;
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    else state <= next;
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  /* registers */
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  always @*
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    if ((state == STATE_INIT) && vid_in_rd_valid) next_dta = {dta[64:0], vid_in};
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    else next_dta = dta;
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  wire [7:0]cursor_aligned = {cursor[7:3], 3'b0};
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  wire [7:0]advance_ext = {3'b0, advance};
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  always @*
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    case (state)
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      STATE_INIT:  if (vid_in_rd_valid) next_cursor = cursor - 8'd64;
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                   else next_cursor = cursor;
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      STATE_READY: if (align) next_cursor = cursor_aligned + 8'd8;
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                   else next_cursor = cursor + advance_ext;
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      default      next_cursor = cursor;
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    endcase
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  always @*
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    {next_signbit, next_getbits, dummy} = next_dta << next_cursor;
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  always @(posedge clk)
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    if (~rst) dta <= 129'b0;
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    else if (clk_en) dta <= next_dta;
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    else dta <= dta;
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  always @(posedge clk)
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    if (~rst) cursor <= 8'd128;
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    else if (clk_en) cursor <= next_cursor;
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    else cursor <= cursor;
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  always @(posedge clk)
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    if (~rst) signbit <= 1'b0;
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    else if (clk_en) signbit <= next_signbit;
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    else signbit <= signbit;
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  always @(posedge clk)
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    if (~rst) getbits <= 24'b0;
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    else if (clk_en) getbits <= next_getbits;
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    else getbits <= getbits;
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  always @(posedge clk)
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    if (~rst) getbits_valid <= 1'b0;
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    else if (clk_en) getbits_valid <= (next == STATE_READY);
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    else getbits_valid <= getbits_valid;
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  always @(posedge clk)
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    if (~rst) vid_in_rd_en <= 1'b0;
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    else if (clk_en) vid_in_rd_en <= (next == STATE_INIT) && ~vid_in_rd_en && ~vid_in_rd_valid;
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    else vid_in_rd_en <= vid_in_rd_en;
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  /* vld clock enable */
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  /*
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   * variable length decoding and fifo take turns;
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   * First vld determines how much to move forward in the bitstream;
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   * next clock, getbits moves that amount forward in the stream while vld waits;
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   * then vld analyzes the new position in the bitstream while getbits waits,
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   * and so on.
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   */
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  always @(posedge clk)
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    if (~rst) vld_en <= 1'b1;
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    // enable vld when getbits, rld, and motcomp ready, and not a wait state
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    else if (clk_en && vld_en) vld_en <= (next == STATE_READY) && ~wait_state && ~rld_wr_almost_full && ~mvec_wr_almost_full && ~motcomp_busy;
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    else if (clk_en) vld_en <= (next == STATE_READY) && ~rld_wr_almost_full && ~mvec_wr_almost_full && ~motcomp_busy;
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    else vld_en <= vld_en;
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  /* Debugging */
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`ifdef DEBUG
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   always @(posedge clk)
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     if (clk_en)
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       $strobe("%m\tvid_in: %h vid_in_rd_en: %d vid_in_rd_valid: %d advance: %d align: %d state: %d dta: %h cursor: %h signbit: %d getbits: %h getbits_valid: %d ",
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                    vid_in, vid_in_rd_en, vid_in_rd_valid, advance, align, state, dta, cursor, signbit, getbits, getbits_valid);
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`endif
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endmodule
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/* not truncated */

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