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/*
2
 * mem_addr.v
3
 *
4
 * Copyright (c) 2007 Koen De Vleeschauwer.
5
 *
6
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
7
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
8
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
9
 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
10
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
11
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
12
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
14
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
15
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
16
 * SUCH DAMAGE.
17
 */
18
 
19
/*
20
 * Memory address generation.
21
 */
22
 
23
`include "timescale.v"
24
 
25
`undef DEBUG
26
//`define DEBUG 1
27
 
28
 /*
29
  Calculates resulting memory address. Assumes 4:2:0 format. Coordinate origin is at top left.
30
  x axis is from left to right; y axis is from top to bottom.
31
 
32
    +------> x
33
    |
34
    |
35
    |
36
    v y
37
 
38
  - mv_x and mv_y are signed quantities, and will be scaled by 2 if chrominance addresses are computed.
39
  - delta_x and delta_y are unsigned, and will not be scaled if chrominance addresses are computed.
40
  - field_in_frame is asserted if a coordinates of a field-encoded frame picture are to be computed.
41
 
42
  Output:
43
  - address of 8-pixel 64-bit word.
44
  - offset_x: offset in bytes into the 8-pixel 64-bit word.
45
    If offset_x is 0, pixel is the leftmost byte of the 64-bit word. If offset_x is 7, pixel is the rightmost byte in the 64-bit word.
46
  - halfpixel_x: if set, horizontal halfpixel interpolation is needed.
47
  - halfpixel_y: if set, vertical halfpixel interpolation is needed.
48
  */
49
 
50
  /*
51
   * Note: par. 7.6.3.8, Semantic restrictions concerning predictions: (restricted slice structure)
52
   * "it is a restriction on the bitstream that reconstructed motion vectors shall not
53
   * refer to samples outside the boundary of the coded picture."
54
   */
55
 
56
module memory_address (
57
  clk, clk_en, rst,
58
  frame, frame_picture, field_in_frame, field, component, mb_width, horizontal_size, vertical_size,  macroblock_address, delta_x, delta_y, mv_x, mv_y, dta_in, valid_in,
59
  address, offset_x, halfpixel_x, halfpixel_y, dta_out, valid_out
60
  );
61
 
62
parameter dta_width=64;                        // dta_in, dta_out width
63
 
64
  input              clk;                      // clock
65
  input              clk_en;                   // clock enable
66
  input              rst;                      // synchronous active low reset
67
  input         [2:0]frame;                    // e.g. forward_reference_frame, backward_reference_frame, aux_frame, current_frame.
68
  input              frame_picture;            // assert if frame picture.
69
  input              field_in_frame;           // assert if accessing a field within a frame picture.
70
  input              field;                    // field number; 0 is top field, 1 is bottom field. Used in field pictures, or when accessing a field within a frame picture.
71
  input         [1:0]component;                // Luminance or chrominance. One of COMP_Y, COMP_CR, COMP_CB.
72
  input         [7:0]mb_width;                 // par. 6.3.3. width of the encoded luminance component of pictures in macroblocks
73
  input        [13:0]horizontal_size;          // par. 6.3.3. width of the displayable part of the luminance component of pictures in samples.
74
  input        [13:0]vertical_size;            // par. 6.3.3. height of the displayable part of the luminance component of the frame in lines.
75
  input        [12:0]macroblock_address;       // absolute position of the current macroblock. top-left macroblock has macroblock_address zero.
76
  input signed [12:0]delta_x;                  // horizontal offset, positive, in pixels.
77
  input signed [12:0]delta_y;                  // vertical offset, positive, in pixels.
78
  input signed [12:0]mv_x;                     // motion vector, horizontal component, signed, in halfpixels.
79
  input signed [12:0]mv_y;                     // motion vector, horizontal component, signed, in halfpixels.
80
  input [dta_width-1:0]dta_in;                 // data in
81
  input              valid_in;
82
 
83
  output reg   [21:0]address;                  // memory address of the 8-pixel block row.
84
  output reg    [2:0]offset_x;                 // Determines pixel offset within the 8-pixel block row. 0..7, 0 = leftmost pixel, msb; 7 = rightmost pixel, lsb.
85
  output reg         halfpixel_x;              // horizontal halfpixel offset. least significant bit of mv_x.
86
  output reg         halfpixel_y;              // vertical halfpixel offset. least significant bit of mv_x.
87
  output reg [dta_width-1:0]dta_out;           // data out is dta_in delayed so as to balance the delay in calculating address
88
  output reg         valid_out;
89
 
90
`include "vld_codes.v"
91
`include "mem_codes.v"
92
 
93
  /*
94
   * stage 0
95
   * - calculate macroblock (x, y) coordinates
96
   * - scale motion vectors
97
   */
98
 
99
  reg           [2:0]frame_0;
100
  reg                frame_picture_0;
101
  reg                field_in_frame_0;
102
  reg                field_0;
103
  reg           [1:0]component_0;
104
  reg           [7:0]mb_width_0;
105
  reg          [13:0]horizontal_size_0;
106
  reg          [13:0]vertical_size_0;
107
  reg signed   [12:0]delta_x_0;
108
  reg signed   [12:0]delta_y_0;
109
  reg signed   [12:0]mv_x_0;
110
  reg signed   [12:0]mv_y_0;
111
  reg signed   [12:0]mv_x_corr_0;
112
  reg signed   [12:0]mv_y_corr_0;
113
  reg           [7:0]macroblock_x_0; // current x-position, in macroblocks
114
  reg           [7:0]macroblock_y_0; // current y-position, in macroblocks
115
  reg [dta_width-1:0]dta_0;
116
  reg                valid_0;
117
  reg                error_0;
118
 
119
  /*
120
   * Macroblock (x, y) coordinate calculation assumes macroblock address
121
   * - starts at zero
122
   * - either stays the same, increments by one or is reset to zero.
123
   * Other combinations - eg. incrementing by two - are in error.
124
   */
125
 
126
  reg          [12:0]previous_macroblock_address;
127
 
128
  always @(posedge clk)
129
    if (~rst) previous_macroblock_address <= 13'd0;
130
    else if (clk_en) previous_macroblock_address <= macroblock_address;
131
    else previous_macroblock_address <= previous_macroblock_address;
132
 
133
  always @(posedge clk)
134
    if (~rst)
135
      begin
136
        macroblock_x_0 <= 8'd0;
137
        macroblock_y_0 <= 8'd0;
138
        error_0        <= 1'b1; // macroblock coordinates are unknown at reset
139
      end
140
    else if (clk_en && (macroblock_address == 13'd0))
141
      begin
142
        macroblock_x_0 <= 8'd0;
143
        macroblock_y_0 <= 8'd0;
144
        error_0        <= 1'b0; // coordinates of macroblock 0 are known
145
      end
146
    else if (clk_en && (macroblock_address == previous_macroblock_address))
147
      begin
148
        macroblock_x_0 <= macroblock_x_0;
149
        macroblock_y_0 <= macroblock_y_0;
150
        error_0        <= error_0;
151
      end
152
    else if (clk_en && (macroblock_address == (previous_macroblock_address + 13'd1)) && ((macroblock_x_0 + 8'd1) == mb_width))
153
      begin
154
        macroblock_x_0 <= 8'd0;
155
        macroblock_y_0 <= macroblock_y_0 + 8'd1;
156
        error_0        <= error_0;
157
      end
158
    else if (clk_en && (macroblock_address == (previous_macroblock_address + 13'd1)))
159
      begin
160
        macroblock_x_0 <= macroblock_x_0 + 8'd1;
161
        macroblock_y_0 <= macroblock_y_0;
162
        error_0        <= error_0;
163
      end
164
    else if (clk_en) // neither resets, nor stays the same, nor increments by one: assert error
165
      begin
166
        macroblock_x_0 <= macroblock_x_0;
167
        macroblock_y_0 <= macroblock_y_0;
168
        error_0        <= 1'b1;
169
      end
170
    else
171
      begin
172
        macroblock_x_0 <= macroblock_x_0;
173
        macroblock_y_0 <= macroblock_y_0;
174
        error_0        <= error_0;
175
      end
176
 
177
  /*
178
   *
179
   * - Motion vector scaling: divide motion vectors by two for chrominance macroblocks. par. 7.6.3.7 Motion vectors for chrominance components.
180
   *   Division by two is evaluated as a/2 = ( a + signbit(a))>>> 1;
181
   *   part1: set up signbit registers.
182
   */
183
 
184
  always @(posedge clk)
185
    if (~rst)
186
      begin
187
        mv_x_corr_0   <= 12'd0;
188
        mv_y_corr_0   <= 12'd0;
189
      end
190
    else if (clk_en)
191
      begin
192
        mv_x_corr_0   <= {11'b0, mv_x[12]};
193
        mv_y_corr_0   <= {11'b0, mv_y[12]};
194
      end
195
    else
196
      begin
197
        mv_x_corr_0   <= mv_x_corr_0;
198
        mv_y_corr_0   <= mv_y_corr_0;
199
     end
200
 
201
  /*
202
   * Pass on other registers
203
   */
204
 
205
  always @(posedge clk)
206
    if (~rst)
207
      begin
208
        frame_0          <= 3'b0;
209
        frame_picture_0  <= 1'b0;
210
        field_in_frame_0 <= 1'b0;
211
        field_0          <= 1'b0;
212
        component_0      <= 2'b0;
213
        mb_width_0       <= 8'd0;
214
        horizontal_size_0<= 14'd0;
215
        vertical_size_0  <= 14'd0;
216
        delta_x_0        <= 13'sd0;
217
        delta_y_0        <= 13'sd0;
218
        mv_x_0           <= 13'sd0;
219
        mv_y_0           <= 13'sd0;
220
        dta_0            <= {dta_width{1'b0}};
221
        valid_0          <= 1'b0;
222
      end
223
    else if (clk_en)
224
      begin
225
        frame_0          <= frame;
226
        frame_picture_0  <= frame_picture;
227
        field_in_frame_0 <= field_in_frame;
228
        field_0          <= field;
229
        component_0      <= component;
230
        mb_width_0       <= mb_width;
231
        horizontal_size_0<= horizontal_size;
232
        vertical_size_0  <= vertical_size;
233
        delta_x_0        <= delta_x;
234
        delta_y_0        <= delta_y;
235
        mv_x_0           <= mv_x;
236
        mv_y_0           <= mv_y;
237
        dta_0            <= dta_in;
238
        valid_0          <= valid_in;
239
      end
240
    else
241
      begin
242
        frame_0          <= frame_0;
243
        frame_picture_0  <= frame_picture_0;
244
        field_in_frame_0 <= field_in_frame_0;
245
        field_0          <= field_0;
246
        component_0      <= component_0;
247
        mb_width_0       <= mb_width_0;
248
        horizontal_size_0<= horizontal_size_0;
249
        vertical_size_0  <= vertical_size_0;
250
        delta_x_0        <= delta_x_0;
251
        delta_y_0        <= delta_y_0;
252
        mv_x_0           <= mv_x_0;
253
        mv_y_0           <= mv_y_0;
254
        dta_0            <= dta_0;
255
        valid_0          <= valid_0;
256
      end
257
 
258
  /*
259
   * Stage 1
260
   * - Motion vector scaling, part2: Apply motion vector correction and shift
261
   * - Calculate macroblock (x, y) coordinates in pixels
262
   */
263
 
264
  reg           [2:0]frame_1;
265
  reg                frame_picture_1;
266
  reg                field_in_frame_1;
267
  reg                field_1;
268
  reg           [1:0]component_1;
269
  reg           [7:0]mb_width_1;
270
  reg          [13:0]horizontal_size_1;
271
  reg          [13:0]vertical_size_1;
272
  reg signed   [12:0]delta_x_1;
273
  reg signed   [12:0]delta_y_1;
274
  reg signed   [12:0]mv_x_1;
275
  reg signed   [12:0]mv_y_1;
276
  reg signed   [12:0]pixel_x_1;
277
  reg signed   [12:0]pixel_y_1;
278
  reg [dta_width-1:0]dta_1;
279
  reg                valid_1;
280
  reg                error_1;
281
 
282
  always @(posedge clk)
283
    if (~rst)
284
      begin
285
        mv_x_1        <= 12'd0;
286
        mv_y_1        <= 12'd0;
287
      end
288
    else if ((clk_en) && (component_0 == COMP_Y)) /* luminance */
289
      begin
290
        mv_x_1        <= mv_x_0;
291
        mv_y_1        <= mv_y_0;
292
      end
293
    else if (clk_en) /* chrominance */
294
      begin
295
        mv_x_1        <= (mv_x_0 + mv_x_corr_0) >>> 1;
296
        mv_y_1        <= (mv_y_0 + mv_y_corr_0) >>> 1;
297
      end
298
    else
299
      begin
300
        mv_x_1        <= mv_x_1;
301
        mv_y_1        <= mv_y_1;
302
      end
303
 
304
  /*
305
   * Calculate macroblock (x, y) coordinates in pixels
306
   */
307
 
308
  always @(posedge clk)
309
    if (~rst)
310
      begin
311
        pixel_x_1     <= 12'sd0;
312
        pixel_y_1     <= 12'sd0;
313
      end
314
    else if ((clk_en) && (component_0 == COMP_Y)) /* luminance: 16x16 pixels/macroblock */
315
      begin
316
        pixel_x_1     <= macroblock_x_0 <<< 4 ;
317
        pixel_y_1     <= macroblock_y_0 <<< 4;
318
      end
319
    else if (clk_en) /* 4:2:0 chrominance: 8x8 pixels/macroblock*/
320
      begin
321
        pixel_x_1     <= macroblock_x_0 <<< 3 ;
322
        pixel_y_1     <= macroblock_y_0 <<< 3;
323
      end
324
    else
325
      begin
326
        pixel_x_1     <= pixel_x_1;
327
        pixel_y_1     <= pixel_y_1;
328
      end
329
 
330
  /*
331
   * Pass on other registers
332
   */
333
 
334
  always @(posedge clk)
335
    if (~rst)
336
      begin
337
        frame_1          <= 3'b0;
338
        frame_picture_1  <= 1'b0;
339
        field_in_frame_1 <= 1'b0;
340
        field_1          <= 1'b0;
341
        component_1      <= 2'b0;
342
        mb_width_1       <= 8'd0;
343
        horizontal_size_1<= 14'd0;
344
        vertical_size_1  <= 14'd0;
345
        delta_x_1        <= 12'sd0;
346
        delta_y_1        <= 12'sd0;
347
        dta_1            <= {dta_width{1'b0}};
348
        valid_1          <= 1'b0;
349
        error_1          <= 1'b0;
350
      end
351
    else if (clk_en)
352
      begin
353
        frame_1          <= frame_0;
354
        frame_picture_1  <= frame_picture_0;
355
        field_in_frame_1 <= field_in_frame_0;
356
        field_1          <= field_0;
357
        component_1      <= component_0;
358
        mb_width_1       <= mb_width_0;
359
        horizontal_size_1<= horizontal_size_0;
360
        vertical_size_1  <= vertical_size_0;
361
        delta_x_1        <= delta_x_0;
362
        delta_y_1        <= delta_y_0;
363
        dta_1            <= dta_0;
364
        valid_1          <= valid_0;
365
        error_1          <= error_0;
366
      end
367
    else
368
      begin
369
        frame_1          <= frame_1;
370
        frame_picture_1  <= frame_picture_1;
371
        field_in_frame_1 <= field_in_frame_1;
372
        field_1          <= field_1;
373
        component_1      <= component_1;
374
        mb_width_1       <= mb_width_1;
375
        horizontal_size_1<= horizontal_size_1;
376
        vertical_size_1  <= vertical_size_1;
377
        delta_x_1        <= delta_x_1;
378
        delta_y_1        <= delta_y_1;
379
        dta_1            <= dta_1;
380
        valid_1          <= valid_1;
381
        error_1          <= error_1;
382
      end
383
 
384
  /*
385
   * Stage 2
386
   * - Motion vector scaling: split motion vector in pixel and halfpixel components.
387
   */
388
 
389
  reg           [2:0]frame_2;
390
  reg                frame_picture_2;
391
  reg                field_in_frame_2;
392
  reg                field_2;
393
  reg           [1:0]component_2;
394
  reg           [7:0]mb_width_2;
395
  reg          [13:0]horizontal_size_2;
396
  reg          [13:0]vertical_size_2;
397
  reg signed   [12:0]delta_x_2;
398
  reg signed   [12:0]delta_y_2;
399
  reg signed   [12:0]mv_x_2;
400
  reg signed   [12:0]mv_y_2;
401
  reg signed   [12:0]pixel_x_2;
402
  reg signed   [12:0]pixel_y_2;
403
  reg                halfpixel_x_2;
404
  reg                halfpixel_y_2;
405
  reg [dta_width-1:0]dta_2;
406
  reg                valid_2;
407
  reg                error_2;
408
 
409
  always @(posedge clk)
410
    if (~rst)
411
      begin
412
        mv_x_2        <= 12'sd0;
413
        halfpixel_x_2 <= 1'd0;
414
        mv_y_2        <= 12'sd0;
415
        halfpixel_y_2 <= 1'd0;
416
      end
417
    else if (clk_en)
418
      begin
419
        mv_x_2        <= {mv_x_1[12], mv_x_1[12:1]};
420
        halfpixel_x_2 <= mv_x_1[0];
421
        mv_y_2        <= {mv_y_1[12], mv_y_1[12:1]};
422
        halfpixel_y_2 <= mv_y_1[0];
423
      end
424
    else
425
      begin
426
        mv_x_2        <= mv_x_2;
427
        halfpixel_x_2 <= halfpixel_x_2;
428
        mv_y_2        <= mv_y_2;
429
        halfpixel_y_2 <= halfpixel_y_2;
430
      end
431
 
432
  /*
433
   * Pass on other registers
434
   */
435
 
436
  always @(posedge clk)
437
    if (~rst)
438
      begin
439
        frame_2          <= 3'b0;
440
        frame_picture_2  <= 1'b0;
441
        field_in_frame_2 <= 1'b0;
442
        field_2          <= 1'b0;
443
        component_2      <= 2'b0;
444
        mb_width_2       <= 8'd0;
445
        horizontal_size_2<= 14'd0;
446
        vertical_size_2  <= 14'd0;
447
        delta_x_2        <= 12'sd0;
448
        delta_y_2        <= 12'sd0;
449
        pixel_x_2        <= 12'sd0;
450
        pixel_y_2        <= 12'sd0;
451
        dta_2            <= {dta_width{1'b0}};
452
        valid_2          <= 1'b0;
453
        error_2          <= 1'b0;
454
      end
455
    else if (clk_en)
456
      begin
457
        frame_2          <= frame_1;
458
        frame_picture_2  <= frame_picture_1;
459
        field_in_frame_2 <= field_in_frame_1;
460
        field_2          <= field_1;
461
        component_2      <= component_1;
462
        mb_width_2       <= mb_width_1;
463
        horizontal_size_2<= horizontal_size_1;
464
        vertical_size_2  <= vertical_size_1;
465
        delta_x_2        <= delta_x_1;
466
        delta_y_2        <= delta_y_1;
467
        pixel_x_2        <= pixel_x_1;
468
        pixel_y_2        <= pixel_y_1;
469
        dta_2            <= dta_1;
470
        valid_2          <= valid_1;
471
        error_2          <= error_1;
472
      end
473
    else
474
      begin
475
        frame_2          <= frame_2;
476
        frame_picture_2  <= frame_picture_2;
477
        field_in_frame_2 <= field_in_frame_2;
478
        field_2          <= field_2;
479
        component_2      <= component_2;
480
        mb_width_2       <= mb_width_2;
481
        horizontal_size_2<= horizontal_size_2;
482
        vertical_size_2  <= vertical_size_2;
483
        delta_x_2        <= delta_x_2;
484
        delta_y_2        <= delta_y_2;
485
        pixel_x_2        <= pixel_x_2;
486
        pixel_y_2        <= pixel_y_2;
487
        dta_2            <= dta_2;
488
        valid_2          <= valid_2;
489
        error_2          <= error_2;
490
      end
491
 
492
  /*
493
   * Stage 3
494
   * Frame and field images
495
   * - If top field of a field image
496
   *     - multiply y by two
497
   *     - multiply motion vector y by two
498
   *     - multiply delta y by two
499
   * - If bottom field of a field image
500
   *     - multiply y by two and add one
501
   *     - multiply motion vector y by two
502
   *     - multiply delta y by two
503
   * - If frame image and field_in_frame is not set
504
   *     - pass on y, motion vector y and delta y unchanged
505
   * - If frame image and field_in_frame is set and field is top field
506
   *     - pass on y unchanged
507
   *     - multiply motion vector y by two
508
   *     - multiply delta y by two
509
   * - If frame image and field_in_frame is set and field is bottom field
510
   *     - add one to y
511
   *     - multiply motion vector y by two
512
   *     - multiply delta y by two
513
   */
514
 
515
  reg           [2:0]frame_3;
516
  reg           [1:0]component_3;
517
  reg           [7:0]mb_width_3;
518
  reg          [13:0]horizontal_size_3;
519
  reg          [13:0]vertical_size_3;
520
  reg signed   [12:0]delta_x_3;
521
  reg signed   [12:0]delta_y_3;
522
  reg signed   [12:0]mv_x_3;
523
  reg signed   [12:0]mv_y_3;
524
  reg signed   [12:0]pixel_x_3;
525
  reg signed   [12:0]pixel_y_3;
526
  reg                halfpixel_x_3;
527
  reg                halfpixel_y_3;
528
  reg [dta_width-1:0]dta_3;
529
  reg                valid_3;
530
  reg                error_3;
531
 
532
  always @(posedge clk)
533
    if (~rst)
534
      begin
535
        delta_y_3 <= 13'sd0;
536
        mv_y_3    <= 13'sd0;
537
        pixel_y_3 <= 13'sd0;
538
      end
539
    else if (clk_en && ~frame_picture_2) /* field picture */
540
      begin
541
        delta_y_3 <= delta_y_2 <<< 1;
542
        mv_y_3    <= mv_y_2 <<< 1;
543
        pixel_y_3 <= {pixel_y_2[11:0], field_2}; /* multiply by 2; add 1 if bottom field */
544
      end
545
    else if (clk_en && frame_picture_2 && field_in_frame_2 && field_2) /* field-in-frame, bottom field */
546
      begin
547
        delta_y_3 <= delta_y_2 <<< 1;
548
        mv_y_3    <= mv_y_2 <<< 1;
549
        pixel_y_3 <= pixel_y_2 + 12'sd1;
550
      end
551
    else if (clk_en && frame_picture_2 && field_in_frame_2 && ~field_2) /* field-in-frame, top field */
552
      begin
553
        delta_y_3 <= delta_y_2 <<< 1;
554
        mv_y_3    <= mv_y_2 <<< 1;
555
        pixel_y_3 <= pixel_y_2;
556
      end
557
    else if (clk_en && frame_picture_2 && ~field_in_frame_2) /* frame picture */
558
      begin
559
        delta_y_3 <= delta_y_2;
560
        mv_y_3    <= mv_y_2;
561
        pixel_y_3 <= pixel_y_2;
562
      end
563
    else
564
      begin
565
        delta_y_3 <= delta_y_3;
566
        mv_y_3    <= mv_y_3;
567
        pixel_y_3 <= pixel_y_3;
568
      end
569
 
570
  /*
571
   * Pass on other registers
572
   */
573
 
574
  always @(posedge clk)
575
    if (~rst)
576
      begin
577
        frame_3          <= 3'b0;
578
        component_3      <= 2'b0;
579
        mb_width_3       <= 8'd0;
580
        horizontal_size_3<= 14'd0;
581
        vertical_size_3  <= 14'd0;
582
        delta_x_3        <= 12'sd0;
583
        mv_x_3           <= 12'sd0;
584
        pixel_x_3        <= 13'sd0;
585
        halfpixel_x_3    <= 1'b0;
586
        halfpixel_y_3    <= 1'b0;
587
        dta_3            <= {dta_width{1'b0}};
588
        valid_3          <= 1'b0;
589
        error_3          <= 1'b0;
590
      end
591
    else if (clk_en)
592
      begin
593
        frame_3          <= frame_2;
594
        component_3      <= component_2;
595
        mb_width_3       <= mb_width_2;
596
        horizontal_size_3<= horizontal_size_2;
597
        vertical_size_3  <= vertical_size_2;
598
        delta_x_3        <= delta_x_2;
599
        mv_x_3           <= mv_x_2;
600
        pixel_x_3        <= pixel_x_2;
601
        halfpixel_x_3    <= halfpixel_x_2;
602
        halfpixel_y_3    <= halfpixel_y_2;
603
        dta_3            <= dta_2;
604
        valid_3          <= valid_2;
605
        error_3          <= error_2;
606
      end
607
    else
608
      begin
609
        frame_3          <= frame_3;
610
        component_3      <= component_3;
611
        mb_width_3       <= mb_width_3;
612
        horizontal_size_3<= horizontal_size_3;
613
        vertical_size_3  <= vertical_size_3;
614
        delta_x_3        <= delta_x_3;
615
        mv_x_3           <= mv_x_3;
616
        pixel_x_3        <= pixel_x_3;
617
        halfpixel_x_3    <= halfpixel_x_3;
618
        halfpixel_y_3    <= halfpixel_y_3;
619
        dta_3            <= dta_3;
620
        valid_3          <= valid_3;
621
        error_3          <= error_3;
622
      end
623
 
624
  /*
625
   * Stage 4
626
   * Add (delta_x, delta_y) to (pixel_x, pixel_y)
627
   */
628
 
629
  reg           [2:0]frame_4;
630
  reg           [1:0]component_4;
631
  reg           [7:0]mb_width_4;
632
  reg signed   [12:0]mv_x_4;
633
  reg signed   [12:0]mv_y_4;
634
  reg signed   [12:0]pixel_x_4;
635
  reg signed   [12:0]pixel_y_4;
636
  reg                halfpixel_x_4;
637
  reg                halfpixel_y_4;
638
  reg signed   [12:0]width_4; // width in pixels of component
639
  reg signed   [12:0]height_4; // width in pixels of component
640
  reg [dta_width-1:0]dta_4;
641
  reg                valid_4;
642
  reg                error_4;
643
 
644
  always @(posedge clk)
645
    if (~rst)
646
      begin
647
        pixel_x_4     <= 12'sd0;
648
        pixel_y_4     <= 12'sd0;
649
      end
650
    else if (clk_en)
651
      begin
652
        pixel_x_4     <= pixel_x_3 + delta_x_3;
653
        pixel_y_4     <= pixel_y_3 + delta_y_3;
654
      end
655
    else
656
      begin
657
        pixel_x_4     <= pixel_x_4;
658
        pixel_y_4     <= pixel_y_4;
659
      end
660
 
661
  always @(posedge clk)
662
    if (~rst)
663
      begin
664
        width_4       <= 14'd0;
665
        height_4      <= 14'd0;
666
      end
667
    else if (clk_en && (component_3 == COMP_Y))
668
      begin
669
        width_4       <= {1'b0, horizontal_size_3[11:0]};
670
        height_4      <= {1'b0, vertical_size_3[11:0]};
671
      end
672
    else if (clk_en)
673
      begin
674
        width_4       <= {2'b0, horizontal_size_3[11:1]};
675
        height_4      <= {2'b0, vertical_size_3[11:1]};
676
      end
677
    else
678
      begin
679
        width_4       <= width_4;
680
        height_4      <= height_4;
681
      end
682
 
683
  /*
684
   * Pass on other registers
685
   */
686
 
687
  always @(posedge clk)
688
    if (~rst)
689
      begin
690
        frame_4          <= 3'b0;
691
        component_4      <= 2'b0;
692
        mb_width_4       <= 8'd0;
693
        mv_x_4           <= 12'sd0;
694
        mv_y_4           <= 12'sd0;
695
        halfpixel_x_4    <= 1'b0;
696
        halfpixel_y_4    <= 1'b0;
697
        dta_4            <= {dta_width{1'b0}};
698
        valid_4          <= 1'b0;
699
        error_4          <= 1'b0;
700
      end
701
    else if (clk_en)
702
      begin
703
        frame_4          <= frame_3;
704
        component_4      <= component_3;
705
        mb_width_4       <= mb_width_3;
706
        mv_x_4           <= mv_x_3;
707
        mv_y_4           <= mv_y_3;
708
        halfpixel_x_4    <= halfpixel_x_3;
709
        halfpixel_y_4    <= halfpixel_y_3;
710
        dta_4            <= dta_3;
711
        valid_4          <= valid_3;
712
        error_4          <= error_3;
713
      end
714
    else
715
      begin
716
        frame_4          <= frame_4;
717
        component_4      <= component_4;
718
        mb_width_4       <= mb_width_4;
719
        mv_x_4           <= mv_x_4;
720
        mv_y_4           <= mv_y_4;
721
        halfpixel_x_4    <= halfpixel_x_4;
722
        halfpixel_y_4    <= halfpixel_y_4;
723
        dta_4            <= dta_4;
724
        valid_4          <= valid_4;
725
        error_4          <= error_4;
726
      end
727
 
728
  /*
729
   * Stage 5
730
   * Add (mv_x, mv_y) to (pixel_x, pixel_y)
731
   */
732
 
733
  reg           [2:0]frame_5;
734
  reg           [1:0]component_5;
735
  reg           [7:0]mb_width_5;
736
  reg signed   [12:0]pixel_x_5;
737
  reg signed   [12:0]pixel_y_5;
738
  reg                halfpixel_x_5;
739
  reg                halfpixel_y_5;
740
  reg signed   [12:0]width_5;
741
  reg signed   [12:0]height_5;
742
  reg [dta_width-1:0]dta_5;
743
  reg                valid_5;
744
  reg                error_5;
745
 
746
  always @(posedge clk)
747
    if (~rst)
748
      begin
749
        pixel_x_5     <= 12'd0;
750
        pixel_y_5     <= 12'd0;
751
      end
752
    else if (clk_en)
753
      begin
754
        pixel_x_5     <= pixel_x_4 + mv_x_4;
755
        pixel_y_5     <= pixel_y_4 + mv_y_4;
756
      end
757
    else
758
      begin
759
        pixel_x_5     <= pixel_x_5;
760
        pixel_y_5     <= pixel_y_5;
761
      end
762
 
763
  always @(posedge clk)
764
    if (~rst)
765
      begin
766
        width_5       <= 13'sd0;
767
        height_5      <= 13'sd0;
768
      end
769
    else if (clk_en && ((width_4 == 13'sd0) || (height_4 == 13'sd0)))
770
      begin
771
        width_5       <= 13'sd0;
772
        height_5      <= 13'sd0;
773
      end
774
    else if (clk_en)
775
      begin
776
        width_5       <= width_4 - 13'sd1;
777
        height_5      <= height_4 - 13'sd1;
778
      end
779
    else
780
      begin
781
        width_5       <= width_5;
782
        height_5      <= height_5;
783
      end
784
 
785
  /*
786
   * Pass on other registers
787
   */
788
 
789
  always @(posedge clk)
790
    if (~rst)
791
      begin
792
        frame_5          <= 3'b0;
793
        component_5      <= 2'b0;
794
        mb_width_5       <= 8'd0;
795
        halfpixel_x_5    <= 1'b0;
796
        halfpixel_y_5    <= 1'b0;
797
        dta_5            <= {dta_width{1'b0}};
798
        valid_5          <= 1'b0;
799
        error_5          <= 1'b0;
800
      end
801
    else if (clk_en)
802
      begin
803
        frame_5          <= frame_4;
804
        component_5      <= component_4;
805
        mb_width_5       <= mb_width_4;
806
        halfpixel_x_5    <= halfpixel_x_4;
807
        halfpixel_y_5    <= halfpixel_y_4;
808
        dta_5            <= dta_4;
809
        valid_5          <= valid_4;
810
        error_5          <= error_4;
811
      end
812
    else
813
      begin
814
        frame_5          <= frame_5;
815
        component_5      <= component_5;
816
        mb_width_5       <= mb_width_5;
817
        halfpixel_x_5    <= halfpixel_x_5;
818
        halfpixel_y_5    <= halfpixel_y_5;
819
        dta_5            <= dta_5;
820
        valid_5          <= valid_5;
821
        error_5          <= error_5;
822
      end
823
 
824
  /*
825
   * Stage 6
826
   * - clip to image borders
827
   * - convert pixel_x, pixel_y to unsigned.
828
   * At this point pixel_x, pixel_y, halfpixel_x and halfpixel_y have been fully computed.
829
   */
830
 
831
  reg           [2:0]frame_6;
832
  reg           [1:0]component_6;
833
  reg           [7:0]mb_width_6;
834
  reg          [11:0]pixel_x_6;
835
  reg          [11:0]pixel_y_6;
836
  reg           [2:0]offset_x_6;
837
  reg                halfpixel_x_6;
838
  reg                halfpixel_y_6;
839
  reg [dta_width-1:0]dta_6;
840
  reg                valid_6;
841
  reg                error_6;
842
 
843
  wire signed  [12:0]horizontal_diff = pixel_x_5 - width_5;
844
  wire signed  [12:0]vertical_diff   = pixel_y_5 - height_5;
845
 
846
  /*
847
   * Even though par. 7.6.3.8 guarantees:
848
   * "it is a restriction on the bitstream that reconstructed motion vectors shall not
849
   * refer to samples outside the boundary of the coded picture."
850
   * we clip coordinates to safe ranges.
851
   * For luminance:
852
   * Clip pixel_x to range [0, horizontal_size-1]
853
   * Clip pixel_y to range [0, vertical_size-1]
854
   * For chrominance:
855
   * Clip pixel_x to range [0, (horizontal_size>>1)-1]
856
   * Clip pixel_y to range [0, (vertical_size>>1)-1]
857
   * Convert pixel_x, pixel_y to unsigned
858
   */
859
 
860
  always @(posedge clk)
861
    if (~rst) pixel_x_6 <= 12'd0;
862
    else if (clk_en && pixel_x_5[12]) pixel_x_6 <= 12'd0; // if pixel_x_5 < 0, clip to 0
863
    else if (clk_en && horizontal_diff[12]) pixel_x_6 <= pixel_x_5[11:0]; // if pixel_x_5 > horizontal_size - 1, clip to horizontal_size - 1
864
    else if (clk_en) pixel_x_6 <= width_5[11:0];
865
    else pixel_x_6 <= pixel_x_6;
866
 
867
  always @(posedge clk)
868
    if (~rst) pixel_y_6 <= 12'd0;
869
    else if (clk_en && pixel_y_5[12]) pixel_y_6 <= 12'd0; // if pixel_y_5 < 0, clip to 0
870
    else if (clk_en && vertical_diff[12]) pixel_y_6 <= pixel_y_5[11:0]; // if pixel_y_5 > vertical_size - 1, clip to vertical_size - 1
871
    else if (clk_en) pixel_y_6 <= height_5[11:0];
872
    else pixel_y_6 <= pixel_y_6;
873
 
874
  /*
875
   *   Calculate byte offset within 8-byte word (offset_x)
876
   */
877
 
878
  always @(posedge clk)
879
    if (~rst) offset_x_6 <= 3'd0;
880
    else if (clk_en) offset_x_6 <= pixel_x_5[2:0];
881
    else offset_x_6 <= offset_x_6;
882
 
883
  always @(posedge clk)
884
    if (~rst) error_6 <= 1'b0;
885
    else if (clk_en) error_6 <= error_5;
886
    else error_6 <= error_6;
887
 
888
  /*
889
   * Pass on other registers
890
   */
891
 
892
  always @(posedge clk)
893
    if (~rst)
894
      begin
895
        frame_6          <= 3'b0;
896
        component_6      <= 2'b0;
897
        mb_width_6       <= 8'd0;
898
        halfpixel_x_6    <= 1'b0;
899
        halfpixel_y_6    <= 1'b0;
900
        dta_6            <= {dta_width{1'b0}};
901
        valid_6          <= 1'b0;
902
      end
903
    else if (clk_en)
904
      begin
905
        frame_6          <= frame_5;
906
        component_6      <= component_5;
907
        mb_width_6       <= mb_width_5;
908
        halfpixel_x_6    <= halfpixel_x_5;
909
        halfpixel_y_6    <= halfpixel_y_5;
910
        dta_6            <= dta_5;
911
        valid_6          <= valid_5;
912
      end
913
    else
914
      begin
915
        frame_6          <= frame_6;
916
        component_6      <= component_6;
917
        mb_width_6       <= mb_width_6;
918
        halfpixel_x_6    <= halfpixel_x_6;
919
        halfpixel_y_6    <= halfpixel_y_6;
920
        dta_6            <= dta_6;
921
        valid_6          <= valid_6;
922
      end
923
 
924
  /*
925
   * Stage 7
926
   * Line stride, part1.
927
   * - multiply y with mb_width
928
   * - split x into two parts:
929
   *   - byte offset within 8-byte word (offset_x)
930
   *   - number of 8-byte words (word_x)
931
   */
932
 
933
  reg           [2:0]frame_7;
934
  reg           [1:0]component_7;
935
  reg                halfpixel_x_7;
936
  reg                halfpixel_y_7;
937
  reg          [21:0]address_7;
938
  reg           [2:0]offset_x_7;
939
  reg           [8:0]word_x_7;
940
  reg [dta_width-1:0]dta_7;
941
  reg                valid_7;
942
  reg                error_7;
943
 
944
  always @(posedge clk)
945
    if (~rst) address_7 <= 22'd0;
946
    else if (clk_en) address_7 <= pixel_y_6 * mb_width_6; /* Instantiate a multiplier :( */
947
    else address_7 <= address_7;
948
 
949
  always @(posedge clk)
950
    if (~rst) word_x_7 <= 3'd0;
951
    else if (clk_en) word_x_7 <= pixel_x_6[11:3];
952
    else word_x_7 <= word_x_7;
953
 
954
  /* if mb_width is zero we don't know MPEG2 horizontal picture size */
955
  always @(posedge clk)
956
    if (~rst) error_7 <= 1'b0;
957
    else if (clk_en) error_7 <= error_6 || (mb_width_6 == 8'd0);
958
    else error_7 <= error_7;
959
 
960
  /*
961
   * Pass on other registers
962
   */
963
 
964
  always @(posedge clk)
965
    if (~rst)
966
      begin
967
        frame_7          <= 3'b0;
968
        component_7      <= 2'b0;
969
        halfpixel_x_7    <= 1'b0;
970
        halfpixel_y_7    <= 1'b0;
971
        offset_x_7       <= 3'd0;
972
        dta_7            <= {dta_width{1'b0}};
973
        valid_7          <= 1'b0;
974
      end
975
    else if (clk_en)
976
      begin
977
        frame_7          <= frame_6;
978
        component_7      <= component_6;
979
        halfpixel_x_7    <= halfpixel_x_6;
980
        halfpixel_y_7    <= halfpixel_y_6;
981
        offset_x_7       <= offset_x_6;
982
        dta_7            <= dta_6;
983
        valid_7          <= valid_6;
984
      end
985
    else
986
      begin
987
        frame_7          <= frame_7;
988
        component_7      <= component_7;
989
        halfpixel_x_7    <= halfpixel_x_7;
990
        halfpixel_y_7    <= halfpixel_y_7;
991
        offset_x_7       <= offset_x_7;
992
        dta_7            <= dta_7;
993
        valid_7          <= valid_7;
994
      end
995
 
996
  /*
997
   * Stage 8
998
   * Line stride, part 2.
999
   * - if macroblock is a luminance block, multiply address by two
1000
   *   (luminance blocks are 16 pixels (bytes) wide; chrominance blocks only 8)
1001
   * - extend word_x
1002
   */
1003
 
1004
  reg           [2:0]frame_8;
1005
  reg           [1:0]component_8;
1006
  reg                halfpixel_x_8;
1007
  reg                halfpixel_y_8;
1008
  reg          [21:0]address_8;
1009
  reg           [2:0]offset_x_8;
1010
  reg          [21:0]word_x_8;
1011
  reg [dta_width-1:0]dta_8;
1012
  reg                valid_8;
1013
  reg                error_8;
1014
 
1015
  always @(posedge clk)
1016
    if (~rst) address_8 <= 22'd0;
1017
    else if (clk_en && (component_7 == COMP_Y)) address_8 <= address_7 << 1;
1018
    else if (clk_en) address_8 <= address_7;
1019
    else address_8 <= address_8;
1020
 
1021
  always @(posedge clk)
1022
    if (~rst) word_x_8 <= 22'd0;
1023
    else if (clk_en) word_x_8 <= word_x_7;
1024
    else word_x_8 <= word_x_8;
1025
 
1026
  /*
1027
   * Pass on other registers
1028
   */
1029
 
1030
  always @(posedge clk)
1031
    if (~rst)
1032
      begin
1033
        frame_8          <= 3'b0;
1034
        component_8      <= 2'b0;
1035
        halfpixel_x_8    <= 1'b0;
1036
        halfpixel_y_8    <= 1'b0;
1037
        offset_x_8       <= 3'd0;
1038
        dta_8            <= {dta_width{1'b0}};
1039
        valid_8          <= 1'b0;
1040
        error_8          <= 1'b0;
1041
      end
1042
    else if (clk_en)
1043
      begin
1044
        frame_8          <= frame_7;
1045
        component_8      <= component_7;
1046
        halfpixel_x_8    <= halfpixel_x_7;
1047
        halfpixel_y_8    <= halfpixel_y_7;
1048
        offset_x_8       <= offset_x_7;
1049
        dta_8            <= dta_7;
1050
        valid_8          <= valid_7;
1051
        error_8          <= error_7;
1052
      end
1053
    else
1054
      begin
1055
        frame_8          <= frame_8;
1056
        component_8      <= component_8;
1057
        halfpixel_x_8    <= halfpixel_x_8;
1058
        halfpixel_y_8    <= halfpixel_y_8;
1059
        offset_x_8       <= offset_x_8;
1060
        dta_8            <= dta_8;
1061
        valid_8          <= valid_8;
1062
        error_8          <= error_8;
1063
      end
1064
 
1065
  /*
1066
   * Stage 9
1067
   * Line stride, part 3.
1068
   * - add word_x to address
1069
   * - determine begin/end addresses of frame in memory.
1070
   */
1071
 
1072
  reg          [21:0]address_9;
1073
  reg          [21:0]base_address_9;
1074
  reg          [21:0]end_address_9;
1075
  reg                halfpixel_x_9;
1076
  reg                halfpixel_y_9;
1077
  reg           [2:0]offset_x_9;
1078
  reg [dta_width-1:0]dta_9;
1079
  reg                valid_9;
1080
  reg                error_9;
1081
 
1082
  always @(posedge clk)
1083
    if (~rst) address_9 <= 22'd0;
1084
    else if (clk_en) address_9 <= address_8 + word_x_8;
1085
    else address_9 <= address_9;
1086
 
1087
  always @(posedge clk)
1088
    if(~rst) base_address_9 <= 22'b0;
1089
    else if (clk_en)
1090
      case ({frame_8, component_8})
1091
        {3'd0, COMP_Y  }: base_address_9 <= FRAME_0_Y;
1092
        {3'd0, COMP_CR }: base_address_9 <= FRAME_0_CR;
1093
        {3'd0, COMP_CB }: base_address_9 <= FRAME_0_CB;
1094
        {3'd1, COMP_Y  }: base_address_9 <= FRAME_1_Y;
1095
        {3'd1, COMP_CR }: base_address_9 <= FRAME_1_CR;
1096
        {3'd1, COMP_CB }: base_address_9 <= FRAME_1_CB;
1097
        {3'd2, COMP_Y  }: base_address_9 <= FRAME_2_Y;
1098
        {3'd2, COMP_CR }: base_address_9 <= FRAME_2_CR;
1099
        {3'd2, COMP_CB }: base_address_9 <= FRAME_2_CB;
1100
        {3'd3, COMP_Y  }: base_address_9 <= FRAME_3_Y;
1101
        {3'd3, COMP_CR }: base_address_9 <= FRAME_3_CR;
1102
        {3'd3, COMP_CB }: base_address_9 <= FRAME_3_CB;
1103
        {3'd4, COMP_Y  }: base_address_9 <= OSD;
1104
        default           base_address_9 <= ADDR_ERR;
1105
      endcase
1106
    else base_address_9 <= base_address_9;
1107
 
1108
  always @(posedge clk)
1109
    if(~rst) end_address_9 <= 22'b0;
1110
    else if (clk_en)
1111
      case (component_8)
1112
        COMP_Y  : end_address_9 <= (22'd1 << WIDTH_Y);
1113
        COMP_CR,
1114
        COMP_CB : end_address_9 <= (22'd1 << WIDTH_C);
1115
        default   end_address_9 <= 22'b0;
1116
      endcase
1117
    else end_address_9 <= end_address_9;
1118
 
1119
  /*
1120
   * Pass on other registers
1121
   */
1122
 
1123
  always @(posedge clk)
1124
    if (~rst)
1125
      begin
1126
        halfpixel_x_9    <= 1'b0;
1127
        halfpixel_y_9    <= 1'b0;
1128
        offset_x_9       <= 3'd0;
1129
        dta_9            <= {dta_width{1'b0}};
1130
        valid_9          <= 1'b0;
1131
        error_9          <= 1'b0;
1132
      end
1133
    else if (clk_en)
1134
      begin
1135
        halfpixel_x_9    <= halfpixel_x_8;
1136
        halfpixel_y_9    <= halfpixel_y_8;
1137
        offset_x_9       <= offset_x_8;
1138
        dta_9            <= dta_8;
1139
        valid_9          <= valid_8;
1140
        error_9          <= error_8;
1141
      end
1142
    else
1143
      begin
1144
        halfpixel_x_9    <= halfpixel_x_9;
1145
        halfpixel_y_9    <= halfpixel_y_9;
1146
        offset_x_9       <= offset_x_9;
1147
        dta_9            <= dta_9;
1148
        valid_9          <= valid_9;
1149
        error_9          <= error_9;
1150
      end
1151
 
1152
  /*
1153
   * Stage 10
1154
   * - add base_address to address
1155
   * - if address exceeds end_address, set error flag.
1156
   */
1157
 
1158
  reg          [21:0]address_10;
1159
  reg                halfpixel_x_10;
1160
  reg                halfpixel_y_10;
1161
  reg           [2:0]offset_x_10;
1162
  reg [dta_width-1:0]dta_10;
1163
  reg                valid_10;
1164
  reg                error_10;
1165
 
1166
  /*
1167
   * add base_address to address
1168
   */
1169
 
1170
  always @(posedge clk)
1171
    if (~rst) address_10 <= 22'd0;
1172
    else if (clk_en) address_10 <= address_9 + base_address_9;
1173
    else address_10 <= address_10;
1174
 
1175
  /*
1176
   * if address exceeds end_address, set error flag.
1177
   */
1178
 
1179
  always @(posedge clk)
1180
    if (~rst) error_10 <= 1'b0;
1181
    else if (clk_en) error_10 <= error_9 || (address_9 > end_address_9);
1182
    else error_10 <= error_10;
1183
 
1184
  /*
1185
   * Pass on other registers
1186
   */
1187
 
1188
  always @(posedge clk)
1189
    if (~rst)
1190
      begin
1191
        halfpixel_x_10    <= 1'b0;
1192
        halfpixel_y_10    <= 1'b0;
1193
        offset_x_10       <= 3'd0;
1194
        dta_10            <= {dta_width{1'b0}};
1195
        valid_10          <= 1'b0;
1196
      end
1197
    else if (clk_en)
1198
      begin
1199
        halfpixel_x_10    <= halfpixel_x_9;
1200
        halfpixel_y_10    <= halfpixel_y_9;
1201
        offset_x_10       <= offset_x_9;
1202
        dta_10            <= dta_9;
1203
        valid_10          <= valid_9;
1204
      end
1205
    else
1206
      begin
1207
        halfpixel_x_10    <= halfpixel_x_10;
1208
        halfpixel_y_10    <= halfpixel_y_10;
1209
        offset_x_10       <= offset_x_10;
1210
        dta_10            <= dta_10;
1211
        valid_10          <= valid_10;
1212
      end
1213
 
1214
  /*
1215
   * Stage 11
1216
   * - Does nothing. (passes on data)
1217
   */
1218
 
1219
  reg          [21:0]address_11;
1220
  reg                halfpixel_x_11;
1221
  reg                halfpixel_y_11;
1222
  reg           [2:0]offset_x_11;
1223
  reg [dta_width-1:0]dta_11;
1224
  reg                valid_11;
1225
  reg                error_11;
1226
 
1227
  always @(posedge clk)
1228
    if (~rst) error_11 <= 1'b0;
1229
    else if (clk_en) error_11 <= error_10;
1230
    else error_11 <= error_11;
1231
 
1232
  /*
1233
   * Pass on other registers
1234
   */
1235
 
1236
  always @(posedge clk)
1237
    if (~rst)
1238
      begin
1239
        address_11        <= 22'b0;
1240
        halfpixel_x_11    <= 1'b0;
1241
        halfpixel_y_11    <= 1'b0;
1242
        offset_x_11       <= 3'd0;
1243
        dta_11            <= {dta_width{1'b0}};
1244
        valid_11          <= 1'b0;
1245
      end
1246
    else if (clk_en)
1247
      begin
1248
        address_11        <= address_10;
1249
        halfpixel_x_11    <= halfpixel_x_10;
1250
        halfpixel_y_11    <= halfpixel_y_10;
1251
        offset_x_11       <= offset_x_10;
1252
        dta_11            <= dta_10;
1253
        valid_11          <= valid_10;
1254
      end
1255
    else
1256
      begin
1257
        address_11        <= address_11;
1258
        halfpixel_x_11    <= halfpixel_x_11;
1259
        halfpixel_y_11    <= halfpixel_y_11;
1260
        offset_x_11       <= offset_x_11;
1261
        dta_11            <= dta_11;
1262
        valid_11          <= valid_11;
1263
      end
1264
 
1265
  /*
1266
   * Stage 12
1267
   * - assign output variables
1268
   * - if error flag set, set address to ADDR_ERR
1269
   */
1270
 
1271
  always @(posedge clk)
1272
    if (~rst) address <= 22'd0;
1273
    else if (clk_en && error_11) address <= ADDR_ERR;
1274
    else if (clk_en) address <= address_11;
1275
    else address <= address;
1276
 
1277
  /*
1278
   * Assign outputs
1279
   */
1280
 
1281
  always @(posedge clk)
1282
    if (~rst)
1283
      begin
1284
        halfpixel_x       <= 1'b0;
1285
        halfpixel_y       <= 1'b0;
1286
        offset_x          <= 3'd0;
1287
        dta_out           <= {dta_width{1'b0}};
1288
        valid_out         <= 1'b0;
1289
      end
1290
    else if (clk_en)
1291
      begin
1292
        halfpixel_x       <= halfpixel_x_11;
1293
        halfpixel_y       <= halfpixel_y_11;
1294
        offset_x          <= offset_x_11;
1295
        dta_out           <= dta_11;
1296
        valid_out         <= valid_11;
1297
      end
1298
    else
1299
      begin
1300
        halfpixel_x       <= halfpixel_x;
1301
        halfpixel_y       <= halfpixel_y;
1302
        offset_x          <= offset_x;
1303
        dta_out           <= dta_out;
1304
        valid_out         <= valid_out;
1305
      end
1306
 
1307
 
1308
`ifdef DEBUG
1309
  always @(posedge clk)
1310
    begin
1311
      $strobe("%m\tclk_en: %d frame: %d frame_picture: %d field_in_frame: %d field: %d component: %d mb_width: %d macroblock_address: %h delta_x: %d delta_y: %d mv_x: %d mv_y: %d dta_in: %d valid_in: %d",
1312
                   clk_en, frame, frame_picture, field_in_frame, field, component, mb_width, macroblock_address, delta_x, delta_y, mv_x, mv_y, dta_in, valid_in);
1313
      $strobe("%m\tclk_en: %d address: %h offset_x: %d halfpixel_x: %d halfpixel_y: %d dta_out: %d valid_out: %d",
1314
                   clk_en, address, offset_x, halfpixel_x, halfpixel_y, dta_out, valid_out);
1315
      $strobe("%m\tclk_en: %d frame_6: %d component_6: %d pixel_x_6: %d pixel_y_6: %d offset_x_6: %d halfpixel_x_6: %d halfpixel_y_6: %d dta_6: %d valid_6: %d",
1316
                   clk_en, frame_6, component_6, pixel_x_6, pixel_y_6, offset_x_6, halfpixel_x_6, halfpixel_y_6, dta_6, valid_6);
1317
 
1318
    end
1319
`endif
1320
 
1321
endmodule
1322
/* not truncated */

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