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kdv |
/*
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* mixer.v
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*
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* Copyright (c) 2007 Koen De Vleeschauwer.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* mixer: synchronize pixels to video h_sync, v_sync
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*/
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/*
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* HDMI Specification 1.0:
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* 6.4 Pixel-Repetition
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* Video formats with native pixel rates below 25 Mpixels/sec require pixel-repetition in order to be
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* carried across a TMDS link. 720x480i and 720x576i video format timings shall always be pixel-repeated.
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*
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* Here: if pixel_repetition repetition is asserted, each pixel is duplicated.
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*/
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`include "timescale.v"
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`undef DEBUG
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//`define DEBUG 1
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module mixer(
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clk, rst,
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pixel_repetition,
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y_in, u_in, v_in, osd_in, position_in, pixel_rd_en, pixel_rd_valid, pixel_rd_underflow,
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h_pos, v_pos, h_sync_in, v_sync_in, pixel_en_in,
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y_out, u_out, v_out, osd_out, h_sync_out, v_sync_out, pixel_en_out
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);
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input clk; // clock
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input rst; // synchronous active low reset
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input pixel_repetition; // if asserted, repeat each pixel once
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/* from pixel_queue fifo */
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input [7:0]y_in;
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input [7:0]u_in;
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input [7:0]v_in;
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input [7:0]osd_in;
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input [2:0]position_in;
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output reg pixel_rd_en;
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input pixel_rd_valid;
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input pixel_rd_underflow; // if pixel_rd_underflow we're outputting pixels faster than we're computing them
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/* from video sync generator */
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input [11:0]h_pos;
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input [11:0]v_pos;
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input h_sync_in;
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input v_sync_in;
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input pixel_en_in;
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/* to dvi transmitter */
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output reg [7:0]y_out;
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output reg [7:0]u_out;
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output reg [7:0]v_out;
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output reg [7:0]osd_out;
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output reg h_sync_out;
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output reg v_sync_out;
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output reg pixel_en_out;
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/* store pixel_queue fifo output */
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reg [7:0]y_0;
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reg [7:0]u_0;
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reg [7:0]v_0;
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reg [7:0]osd_0;
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reg [2:0]position_in_0;
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reg h_sync_0;
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reg v_sync_0;
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reg pixel_en_0;
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/* delay h_sync, v_sync, pixel_en by two clocks */
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reg pixel_en_1;
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reg h_sync_1;
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reg v_sync_1;
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reg pixel_en_2;
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reg h_sync_2;
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reg v_sync_2;
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`include "resample_codes.v"
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parameter [2:0]
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STATE_INIT = 3'h0, /* read pixel queue until the first pixel of a line is found */
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STATE_WAIT = 3'h1, /* wait until first pixel of the line will be displayed */
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STATE_FIRST_PIXEL = 3'h2, /* display first pixel of the line */
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STATE_REPEAT_FIRST_PIXEL = 3'h3, /* pixel repetition */
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STATE_PIXEL = 3'h4, /* display pixels */
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STATE_REPEAT_PIXEL = 3'h5, /* pixel repetition */
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STATE_LAST_PIXEL = 3'h6, /* display last pixel of the line */
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STATE_REPEAT_LAST_PIXEL = 3'h7; /* pixel repetition */
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reg [2:0]state;
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reg [2:0]next;
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wire first_pixel_read = (pixel_rd_valid && ((position_in == ROW_0_COL_0) || (position_in == ROW_1_COL_0) || (position_in == ROW_X_COL_0))) // first pixel at fifo output
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|| ((position_in_0 == ROW_0_COL_0) || (position_in_0 == ROW_1_COL_0) || (position_in_0 == ROW_X_COL_0)); // first pixel already stored
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wire display_first_pixel = (h_pos == 12'd0) && (((position_in_0 == ROW_0_COL_0) && (v_pos == 12'd0)) ||
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((position_in_0 == ROW_1_COL_0) && (v_pos == 12'd1)) ||
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((position_in_0 == ROW_X_COL_0) && (v_pos != 12'd0) && (v_pos != 12'd1)));
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wire last_pixel_read = pixel_rd_valid && (position_in == ROW_X_COL_LAST);
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/* next state logic */
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always @*
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case (state)
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STATE_INIT: if (first_pixel_read) next = STATE_WAIT;
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else next = STATE_INIT;
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STATE_WAIT: if (pixel_en_in && display_first_pixel) next = STATE_FIRST_PIXEL;
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else next = STATE_WAIT;
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STATE_FIRST_PIXEL: if (pixel_repetition) next = STATE_REPEAT_FIRST_PIXEL;
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else next = STATE_PIXEL;
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STATE_REPEAT_FIRST_PIXEL: next = STATE_PIXEL;
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STATE_PIXEL: if (pixel_rd_underflow) next = STATE_INIT;
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else if (pixel_repetition) next = STATE_REPEAT_PIXEL;
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else if (last_pixel_read) next = STATE_LAST_PIXEL;
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else next = STATE_PIXEL;
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STATE_REPEAT_PIXEL: if (pixel_rd_underflow) next = STATE_INIT;
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else if (last_pixel_read) next = STATE_LAST_PIXEL;
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else next = STATE_PIXEL;
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STATE_LAST_PIXEL: if (pixel_repetition) next = STATE_REPEAT_LAST_PIXEL;
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else next = STATE_INIT;
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STATE_REPEAT_LAST_PIXEL: next = STATE_INIT;
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default next = STATE_INIT;
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endcase
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/* state */
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always @(posedge clk)
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if(~rst) state <= STATE_INIT;
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else state <= next;
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/* registers */
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/* store pixel_fifo output */
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always @(posedge clk)
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if (~rst) y_0 <= 8'd0;
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else if (pixel_rd_valid) y_0 <= y_in;
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else y_0 <= y_0;
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always @(posedge clk)
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if (~rst) u_0 <= 8'd0;
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else if (pixel_rd_valid) u_0 <= u_in;
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else u_0 <= u_0;
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always @(posedge clk)
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if (~rst) v_0 <= 8'd0;
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else if (pixel_rd_valid) v_0 <= v_in;
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else v_0 <= v_0;
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always @(posedge clk)
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if (~rst) osd_0 <= 8'd0;
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else if (pixel_rd_valid) osd_0 <= osd_in;
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else osd_0 <= osd_0;
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always @(posedge clk)
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if (~rst) position_in_0 <= ROW_X_COL_X;
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else if (pixel_rd_valid) position_in_0 <= position_in;
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else position_in_0 <= position_in_0;
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/* read from pixel_fifo */
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always @(posedge clk)
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if (~rst) pixel_rd_en <= 1'b0;
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else
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case (state)
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STATE_INIT: pixel_rd_en <= ~pixel_rd_en && ~first_pixel_read;
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STATE_WAIT: pixel_rd_en <= 1'b0;
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STATE_FIRST_PIXEL: pixel_rd_en <= ~pixel_repetition;
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STATE_REPEAT_FIRST_PIXEL: pixel_rd_en <= 1'b1;
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STATE_PIXEL: pixel_rd_en <= ~pixel_repetition && ~last_pixel_read; // stop if last pixel of this line read
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STATE_REPEAT_PIXEL: pixel_rd_en <= ~last_pixel_read;
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STATE_LAST_PIXEL: pixel_rd_en <= 1'b0;
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STATE_REPEAT_LAST_PIXEL: pixel_rd_en <= 1'b0;
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default pixel_rd_en <= 1'b0;
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endcase
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/* delay sync gen output */
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always @(posedge clk)
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if (~rst) h_sync_0 <= 1'b0;
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else h_sync_0 <= h_sync_in;
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always @(posedge clk)
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if (~rst) v_sync_0 <= 1'b0;
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else v_sync_0 <= v_sync_in;
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always @(posedge clk)
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if (~rst) pixel_en_0 <= 1'b0;
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else pixel_en_0 <= pixel_en_in;
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/* default values of y_out, u_out and v_out are 16, 128, 128, which maps onto black */
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wire displaying = (state == STATE_FIRST_PIXEL) ||
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(state == STATE_REPEAT_FIRST_PIXEL) ||
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(state == STATE_PIXEL) ||
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(state == STATE_REPEAT_PIXEL) ||
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(state == STATE_LAST_PIXEL) ||
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(state == STATE_REPEAT_LAST_PIXEL);
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always @(posedge clk)
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if (~rst) y_out <= 8'b0;
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else if (pixel_en_2 && displaying) y_out <= y_0;
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else y_out <= 8'd16;
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always @(posedge clk)
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if (~rst) u_out <= 8'b0;
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else if (pixel_en_2 && displaying) u_out <= u_0;
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else u_out <= 8'd128;
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always @(posedge clk)
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if (~rst) v_out <= 8'b0;
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else if (pixel_en_2 && displaying) v_out <= v_0;
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else v_out <= 8'd128;
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always @(posedge clk)
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if (~rst) osd_out <= 8'b0;
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else if (pixel_en_2 && displaying) osd_out <= osd_0;
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else osd_out <= 8'd0;
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/*
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* delay h_sync, v_sync, pixel_en_out by two clocks
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*/
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always @(posedge clk)
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if (~rst) pixel_en_1 <= 1'b0;
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else pixel_en_1 <= pixel_en_0;
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always @(posedge clk)
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if (~rst) h_sync_1 <= 1'b0;
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else h_sync_1 <= h_sync_0;
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always @(posedge clk)
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if (~rst) v_sync_1 <= 1'b0;
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else v_sync_1 <= v_sync_0;
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always @(posedge clk)
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if (~rst) pixel_en_2 <= 1'b0;
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else pixel_en_2 <= pixel_en_1;
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always @(posedge clk)
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if (~rst) h_sync_2 <= 1'b0;
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else h_sync_2 <= h_sync_1;
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always @(posedge clk)
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if (~rst) v_sync_2 <= 1'b0;
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else v_sync_2 <= v_sync_1;
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always @(posedge clk)
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if (~rst) pixel_en_out <= 1'b0;
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else pixel_en_out <= pixel_en_2;
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always @(posedge clk)
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if (~rst) h_sync_out <= 1'b0;
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else h_sync_out <= h_sync_2;
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always @(posedge clk)
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if (~rst) v_sync_out <= 1'b0;
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else v_sync_out <= v_sync_2;
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`ifdef DEBUG
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always @(posedge clk)
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case (state)
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STATE_INIT: #0 $display("%m STATE_INIT");
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STATE_WAIT: #0 $display("%m STATE_WAIT");
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STATE_FIRST_PIXEL: #0 $display("%m STATE_FIRST_PIXEL");
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STATE_REPEAT_FIRST_PIXEL: #0 $display("%m STATE_REPEAT_FIRST_PIXEL");
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STATE_PIXEL: #0 $display("%m STATE_PIXEL");
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STATE_REPEAT_PIXEL: #0 $display("%m STATE_REPEAT_PIXEL");
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STATE_LAST_PIXEL: #0 $display("%m STATE_LAST_PIXEL");
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STATE_REPEAT_LAST_PIXEL: #0 $display("%m STATE_REPEAT_LAST_PIXEL");
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default #0 $display("%m *** Error: unknown state %d", state);
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endcase
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always @(posedge clk)
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$strobe("%m\tstate: %d y_in %d u_in %d v_in %d osd_in %d position_in %d pixel_rd_en %d pixel_rd_valid %d h_pos %d v_pos %d h_sync_in %d v_sync_in %d pixel_en_in %d y_out %d u_out %d v_out %d osd_out %d h_sync_out %d v_sync_out %d pixel_en_out %d",
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state, y_in, u_in, v_in, osd_in, position_in, pixel_rd_en, pixel_rd_valid, h_pos, v_pos, h_sync_in, v_sync_in, pixel_en_in, y_out, u_out, v_out, osd_out, h_sync_out, v_sync_out, pixel_en_out);
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`endif
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endmodule
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/* not truncated */
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