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[/] [mpeg2fpga/] [trunk/] [rtl/] [mpeg2/] [read_write.v] - Blame information for rev 2

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/*
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 * read_write.v
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 *
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 * Copyright (c) 2007 Koen De Vleeschauwer.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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 * SUCH DAMAGE.
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 */
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/*
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 * read_write - Interface for framestore readers/writers.
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 */
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`include "timescale.v"
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/*
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 *   Address is a 22-bit memory address, which unequivocally determines the location of one 64-bit macroblock row, 8 pixels wide, 8 bits per pixel.
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 *   Data is one 64-bit macroblock row, 8 pixels wide, 8 bits per pixel.
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 *
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 * Frame store and reader/writer may have different clocks.
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 * Reader/writer uses clock "clk", frame store uses clock "mem_clk".
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 * Only the reader/writer side has a clock enable clk_en; the frame store is free running.
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 */
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`undef CHECK
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`ifdef __IVERILOG__
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`define CHECK 1
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`endif
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module framestore_reader(
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  rst, clk,
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  wr_addr_clk_en, wr_addr_full, wr_addr_almost_full, wr_addr_en, wr_addr_ack, wr_addr_overflow, wr_addr, rd_dta_clk_en, rd_dta_almost_empty, rd_dta_empty, rd_dta_en, rd_dta_valid, rd_dta,
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  rd_addr_empty, rd_addr_en, rd_addr_valid, rd_addr, wr_dta_full, wr_dta_almost_full, wr_dta_en, wr_dta_ack, wr_dta_overflow, wr_dta
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  );
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  /*
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   * Note: maximum clock frequency may depend upon fifo depth.
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   * On Xilinx Spartan, once the fifo is too long to fit in single block ram, speed drops.
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   * For 64-bit words, a depth of 127-256 entries seems optimal. YMMV.
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   */
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  parameter [8:0]fifo_dta_depth=9'd7;       // number of levels in fifo = 2 ** fifo_depth. eg. fifo_depth=7 gives a fifo 128 levels deep.
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  parameter [8:0]fifo_addr_depth=9'd5;      // number of levels in fifo = 2 ** fifo_depth. eg. fifo_depth=5 gives a fifo 32 levels deep.
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  parameter [8:0]fifo_addr_threshold=9'd8;  // assert wr_addr_almost_full when 8 free slots left.
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  parameter [8:0]fifo_dta_threshold=9'd6;   // assert wr_dta_almost_full when 6 free slots left.
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  /* address and data fifo reset and clock */
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  input        rst;
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  input        clk;
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  /* reader side, writing address */
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  input        wr_addr_clk_en;
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  output       wr_addr_full;
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  output       wr_addr_almost_full;
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  input        wr_addr_en;
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  input  [21:0]wr_addr;
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  output       wr_addr_ack;
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  output       wr_addr_overflow;
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  /* reader side, reading data */
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  input        rd_dta_clk_en;
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  output       rd_dta_almost_empty;
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  output       rd_dta_empty;
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  input        rd_dta_en;
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  output [63:0]rd_dta;
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  output       rd_dta_valid;
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  /* frame store side, reading address */
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  output       rd_addr_empty;
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  input        rd_addr_en;
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  output [21:0]rd_addr;
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  output       rd_addr_valid;
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  /* frame store side, writing data */
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  output       wr_dta_full;
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  output       wr_dta_almost_full;
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  input        wr_dta_en;
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  output       wr_dta_ack;
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  input  [63:0]wr_dta;
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  output       wr_dta_overflow;
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  /* address fifo */
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  fifo_sc
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    #(.addr_width(fifo_addr_depth),
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    .dta_width(9'd22), // block row address is 22 bits.
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    .prog_thresh(fifo_addr_threshold))
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    reader_addr_fifo (
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    .rst(rst),
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    .clk(clk),
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    .din(wr_addr),
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    .wr_en(wr_addr_en && wr_addr_clk_en),
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    .wr_ack(wr_addr_ack),
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    .full(wr_addr_full),
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    .overflow(wr_addr_overflow),
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    .prog_full(wr_addr_almost_full),
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    .dout(rd_addr),
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    .rd_en(rd_addr_en),
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    .valid(rd_addr_valid),
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    .underflow(),
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    .empty(rd_addr_empty),
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    .prog_empty()
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    );
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  /*
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   * Generate an "almost full" signal when framestore should stop treating read requests for this reader.
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   * The 'almost full' signal is actually asserted when only 6 free slots remain in the fifo.
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   */
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  fifo_sc
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    #(.addr_width(fifo_dta_depth),
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    .dta_width(9'd64), // one block row is 8 pixels at 8 bits each, 64 bits total.
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    .prog_thresh(fifo_dta_threshold))   // assert prog_full when fifo has space for 8 (or less) entries (= 1 block).
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    reader_dta_fifo (
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    .rst(rst),
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    .clk(clk),
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    .din(wr_dta),
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    .wr_en(wr_dta_en),
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    .wr_ack(wr_dta_ack),
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    .full(wr_dta_full),
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    .overflow(wr_dta_overflow),
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    .dout(rd_dta),
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    .rd_en(rd_dta_en && rd_dta_clk_en),
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    .valid(rd_dta_valid),
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    .underflow(),
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    .empty(rd_dta_empty),
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    .prog_empty(rd_dta_almost_empty),
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    .prog_full(wr_dta_almost_full)
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    );
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`ifdef CHECK
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  always @(posedge clk)
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    if (wr_addr_overflow)
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      begin
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        #0 $display ("%m\t*** error: framestore_reader addr fifo overflow. ***");
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        $stop;
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      end
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  always @(posedge clk)
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    if (wr_dta_overflow)
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      begin
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        #0 $display ("%m\t*** error: framestore_reader data fifo overflow. ***");
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        $stop;
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      end
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`endif
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endmodule
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module framestore_writer(
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  rst, clk, clk_en,
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  wr_full, wr_almost_full, wr_ack, wr_en, wr_addr, wr_dta, wr_overflow,
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  rd_empty, rd_almost_empty, rd_valid, rd_en, rd_addr, rd_dta
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  );
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  /*
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   * Fifo depth.
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   * Note: maximum clock frequency depends upon fifo depth.
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   * On Xilinx Spartan, once you go beyond a single block ram, speed drops.  XXX Check.
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   * For 64-bit words, a depth of around 256 seems optimal. YMMV.
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   */
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  parameter [8:0]fifo_depth=9'd7;      // number of levels in fifo = 2 ** fifo_depth. eg. fifo_depth=7 gives a fifo 128 levels deep.
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  parameter [8:0]fifo_threshold=9'd8;  // assert wr_almost_full when 8 free slots left.
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  /* fifo reset and clock */
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  input        rst;
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  input        clk;
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  input        clk_en;
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  /* writer side, writing command and address */
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  output       wr_full;
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  output       wr_almost_full;
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  output       wr_ack;
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  input        wr_en;
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  input  [21:0]wr_addr;
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  input  [63:0]wr_dta;
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  output       wr_overflow;
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  /* frame store side, reading command and address */
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  output       rd_empty;
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  output       rd_almost_empty;
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  output       rd_valid;
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  input        rd_en;
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  output [21:0]rd_addr;
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  output [63:0]rd_dta;
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  fifo_sc
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    #(.addr_width(fifo_depth),
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    .dta_width(9'd86), // 22 bit address + 64 bit data = 86 bits
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    .prog_thresh(fifo_threshold))  // assert prog_empty when fifo has 8 (or less than 8) entries.
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    writer_fifo (
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    .rst(rst),
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    .clk(clk),
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    .din({wr_addr, wr_dta}),
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    .wr_en(wr_en && clk_en),
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    .full(wr_full),
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    .prog_full(wr_almost_full),
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    .wr_ack(wr_ack),
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    .overflow(wr_overflow),
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    .dout({rd_addr, rd_dta}),
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    .rd_en(rd_en),
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    .empty(rd_empty),
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    .prog_empty(rd_almost_empty),
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    .valid(rd_valid),
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    .underflow()
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    );
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`ifdef CHECK
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  always @(posedge clk)
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    if (wr_overflow)
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      begin
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        #0 $display ("%m\t*** error: framestore_writer fifo overflow ***");
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        $stop;
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      end
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`endif
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endmodule
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/* not truncated */

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