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[/] [mpeg2fpga/] [trunk/] [rtl/] [mpeg2/] [resample_dta.v] - Blame information for rev 2

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/*
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 * resample_dta.v
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 *
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 * Copyright (c) 2007 Koen De Vleeschauwer.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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 * SUCH DAMAGE.
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 */
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/*
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 * resample_dta - chroma resampling: read pixel data from memory fifo.
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 */
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`include "timescale.v"
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`undef DEBUG
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//`define DEBUG 1
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module resample_dta (
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  clk, clk_en, rst,
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  fifo_read, fifo_valid,
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  disp_rd_dta_empty, disp_rd_dta_en, disp_rd_dta_valid, disp_rd_dta,
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  resample_rd_en, resample_rd_dta, resample_rd_valid,
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  fifo_osd, fifo_y, fifo_u_upper, fifo_u_lower, fifo_v_upper, fifo_v_lower, fifo_position
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  );
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  input            clk;                      // clock
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  input            clk_en;                   // clock enable
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  input            rst;                      // synchronous active low reset
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  input            fifo_read;                // resample_bilinear asserts 'fifo_read' when resample_bilineear clocks in fifo_* data
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  output reg       fifo_valid;               // resample_dta asserts 'fifo_valid' when fifo_* valid
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  /* chroma resampling: reading reconstructed frame data */
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  input            disp_rd_dta_empty;
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  output           disp_rd_dta_en;
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  input            disp_rd_dta_valid;
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  input      [63:0]disp_rd_dta;
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  output           resample_rd_en;
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  input       [2:0]resample_rd_dta;
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  input            resample_rd_valid;
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  /* registers to read disp_rd_dta fifo in.
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     16 pixels - a macroblock - wide.
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     Two rows of chrominance information are stored, as we will have to interpolate between these two rows. */
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  output reg [127:0]fifo_osd;          /* osd data */
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  output reg [127:0]fifo_y;            /* lumi */
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  output reg  [63:0]fifo_u_upper;      /* chromi, upper row */
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  output reg  [63:0]fifo_u_lower;      /* chromi, lower row */
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  output reg  [63:0]fifo_v_upper;      /* chromi, upper row */
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  output reg  [63:0]fifo_v_lower;      /* chromi, lower row */
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  output reg   [2:0]fifo_position;     /* position of pixels, as in  resample_codes */
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  /* first-word fall-through fifo readers */
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  wire             disp_fwft_valid;
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  wire      [127:0]disp_fwft_dout;
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  reg              disp_fwft_rd_en;
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  wire             resample_fwft_valid;
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  wire        [2:0]resample_fwft_dout;
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  reg              resample_fwft_rd_en;
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  parameter [3:0]
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    STATE_INIT        = 4'h0,
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    STATE_RD_OSD      = 4'h1,
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    STATE_RD_Y        = 4'h2,
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    STATE_RD_U        = 4'h3,
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    STATE_RD_V        = 4'h4,
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    STATE_RD_POS      = 4'h5,
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    STATE_READY       = 4'h6,
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    STATE_WAIT        = 4'h7;
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  reg          [3:0]state;
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  reg          [3:0]next;
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  /* next state logic */
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  always @*
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    case (state)
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      STATE_INIT:         next = STATE_RD_OSD;
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      STATE_RD_OSD:       if (disp_fwft_valid) next = STATE_RD_Y;
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                          else next = STATE_RD_OSD;
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      STATE_RD_Y:         if (disp_fwft_valid) next = STATE_RD_U;
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                          else next = STATE_RD_Y;
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      STATE_RD_U:         if (disp_fwft_valid) next = STATE_RD_V;
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                          else next = STATE_RD_U;
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      STATE_RD_V:         if (disp_fwft_valid) next = STATE_RD_POS;
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                          else next = STATE_RD_V;
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      STATE_RD_POS:       if (resample_fwft_valid) next = STATE_READY;
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                          else next = STATE_RD_POS;
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                          /* raise fifo_valid; wait for fifo_read to go high */
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      STATE_READY:        if (fifo_read) next = STATE_WAIT;
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                          else next = STATE_READY;
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                          /* wait for fifo_read to drop, then lower fifo_valid */
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      STATE_WAIT:         if (~fifo_read) next = STATE_RD_OSD;
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                          else next = STATE_WAIT;
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      default             next = STATE_INIT;
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    endcase
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  /* state */
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  always @(posedge clk)
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    if(~rst) state <= STATE_INIT;
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    else if (clk_en) state <= next;
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    else state <= state;
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  /* inform resample_bilinear data is valid */
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  always @(posedge clk)
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    if(~rst) fifo_valid <= 1'b0;
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    else if (clk_en && (state == STATE_READY)) fifo_valid <= 1'b1;
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    else if (clk_en && (state == STATE_WAIT)) fifo_valid <= fifo_read; // drop fifo_valid when fifo_read is lowered
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    else if (clk_en) fifo_valid <= 1'b0;
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    else fifo_valid <= fifo_valid;
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  /* disp fifo read enable */
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  always @(posedge clk)
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    if(~rst) disp_fwft_rd_en <= 1'b0;
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    else if (clk_en) disp_fwft_rd_en <= (next == STATE_RD_OSD) || (next == STATE_RD_Y) || (next == STATE_RD_U) ||(next == STATE_RD_V);
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    else disp_fwft_rd_en <= disp_fwft_rd_en;
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  /* resample fifo read enable */
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  always @(posedge clk)
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    if(~rst) resample_fwft_rd_en <= 1'b0;
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    else if (clk_en) resample_fwft_rd_en <= (next == STATE_RD_POS);
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    else resample_fwft_rd_en <= resample_fwft_rd_en;
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  /* read data from disp fifo */
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  always @(posedge clk)
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    if (~rst) fifo_osd <= 128'b0;
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    else if (clk_en && (state == STATE_RD_OSD) && disp_fwft_valid) fifo_osd <= disp_fwft_dout;
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    else fifo_osd <= fifo_osd;
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  always @(posedge clk)
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    if (~rst) fifo_y <= 128'b0;
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    else if (clk_en && (state == STATE_RD_Y) && disp_fwft_valid) fifo_y <= disp_fwft_dout;
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    else fifo_y <= fifo_y;
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  always @(posedge clk)
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    if (~rst) {fifo_u_upper, fifo_u_lower} <= 64'b0;
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    else if (clk_en && (state == STATE_RD_U) && disp_fwft_valid) {fifo_u_upper, fifo_u_lower} <= disp_fwft_dout;
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    else {fifo_u_upper, fifo_u_lower} <= {fifo_u_upper, fifo_u_lower};
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  always @(posedge clk)
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    if (~rst) {fifo_v_upper, fifo_v_lower} <= 64'b0;
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    else if (clk_en && (state == STATE_RD_V) && disp_fwft_valid) {fifo_v_upper, fifo_v_lower} <= disp_fwft_dout;
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    else {fifo_v_upper, fifo_v_lower} <= {fifo_v_upper, fifo_v_lower};
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  /* read data from resample fifo */
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  always @(posedge clk)
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    if (~rst) fifo_position <= 2'b0;
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    else if (clk_en && (state == STATE_RD_POS) && resample_fwft_valid) fifo_position <= resample_fwft_dout;
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    else fifo_position <= fifo_position;
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  /* fifo readers */
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  fwft2_reader
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    #(.dta_width(9'd64))
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  disp_fwft_reader (
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    .rst(rst),
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    .clk(clk),
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    .clk_en(clk_en),
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    .fifo_rd_en(disp_rd_dta_en),
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    .fifo_valid(disp_rd_dta_valid),
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    .fifo_dout(disp_rd_dta),
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    .valid(disp_fwft_valid),
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    .dout(disp_fwft_dout),
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    .rd_en(disp_fwft_rd_en)
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    );
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  fwft_reader
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    #(.dta_width(9'd3))
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  resample_fwft_reader (
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    .rst(rst),
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    .clk(clk),
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    .clk_en(clk_en),
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    .fifo_rd_en(resample_rd_en),
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    .fifo_valid(resample_rd_valid),
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    .fifo_dout(resample_rd_dta),
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    .valid(resample_fwft_valid),
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    .dout(resample_fwft_dout),
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    .rd_en(resample_fwft_rd_en)
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    );
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`ifdef DEBUG
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  always @(posedge clk)
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    if (clk_en)
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        case (state)
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        STATE_INIT:                   #0 $display("%m\tSTATE_INIT");
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        STATE_RD_OSD:                 #0 $display("%m\tSTATE_RD_OSD");
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        STATE_RD_Y:                   #0 $display("%m\tSTATE_RD_Y");
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        STATE_RD_U:                   #0 $display("%m\tSTATE_RD_U");
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        STATE_RD_V:                   #0 $display("%m\tSTATE_RD_V");
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        STATE_RD_POS:                 #0 $display("%m\tSTATE_RD_POS");
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        STATE_READY:                  #0 $display("%m\tSTATE_READY");
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        STATE_WAIT:                   #0 $display("%m\tSTATE_WAIT");
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        default                       #0 $display("%m\t*** Error: unknown state %d", state);
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      endcase
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  always @(posedge clk)
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    $strobe("%m\tstate: %d fifo_read: %d fifo_valid: %d fifo_osd: %32h fifo_y: %32h fifo_u_upper: %16h fifo_u_lower: %16h fifo_v_upper: %16h fifo_v_lower: %16h fifo_position: %d disp_rd_dta_en: %d disp_rd_dta_valid: %d disp_rd_dta: %16h resample_rd_en: %d resample_rd_valid: %d resample_rd_dta: %d", state, fifo_read, fifo_valid, fifo_osd, fifo_y, fifo_u_upper, fifo_u_lower, fifo_v_upper, fifo_v_lower, fifo_position, disp_rd_dta_en, disp_rd_dta_valid, disp_rd_dta, resample_rd_en, resample_rd_valid, resample_rd_dta);
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`endif
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endmodule
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/* not truncated */

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