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[/] [mpeg2fpga/] [trunk/] [rtl/] [mpeg2/] [reset.v] - Blame information for rev 2

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1 2 kdv
/*
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 * reset.v
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 *
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 * Copyright (c) 2007 Koen De Vleeschauwer.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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 * SUCH DAMAGE.
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 */
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/*
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 * Generate reset signals.
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 *   Accepts an asynchronous reset signal, and generates reset signals in the clk, mem_clk and dot_clk domains
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 *   which are at least three clock cycles long.
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 *
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 * Xilinx FIFO18/FIFO36 primitives:
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 * "The reset signal must be high for at least three read clock and three write clock cycles."
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 *
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 */
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`include "timescale.v"
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module reset (clk, mem_clk, dot_clk, async_rst, watchdog_rst,
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              clk_rst, mem_rst, dot_rst, hard_rst);
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  input clk;                  /* decoder clock */
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  input mem_clk;              /* memory clock */
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  input dot_clk;              /* pixel clock */
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  input async_rst;            /* global reset, asynchronous. */
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  input watchdog_rst;         /* watchdog-generated reset, synchronous with clk. Goes low when watchdog timer expires. */
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  output clk_rst;             /* global reset, synchronized to decoder clock. Goes low when "async_rst" or "watchdog_rst" goes low. */
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  output mem_rst;             /* global reset, synchronized to memory clock. Goes low when "async_rst" or "watchdog_rst" goes low. */
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  output dot_rst;             /* global reset, synchronized to pixel clock. Goes low when "async_rst" or "watchdog_rst" goes low. */
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  output hard_rst;            /* "hard" reset signal. Goes low when "async_rst" input pin goes low. */
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  /* synchronize async_rst and watchdog with clk */
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  wire clk_rst_0;
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  wire clk_watchdog_0;
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  sync_reset clk_sreset_0 (
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    .clk(clk),
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    .asyncrst(async_rst),
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    .syncrst(clk_rst_0)
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    );
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  sync_reset clk_swatchdog_0 (
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    .clk(clk),
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    .asyncrst(watchdog_rst),
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    .syncrst(clk_watchdog_0)
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    );
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  /* combine async_rst and watchdog into a common reset signal */
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  wire comm_rst = clk_rst_0 && clk_watchdog_0;
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  /* synchronize common reset signal to the three system clocks */
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  wire clk_rst_1;
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  wire mem_rst_1;
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  wire dot_rst_1;
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  sync_reset clk_sreset_1 (
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    .clk(clk),
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    .asyncrst(comm_rst),
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    .syncrst(clk_rst_1)
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    );
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  sync_reset mem_sreset_1 (
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    .clk(mem_clk),
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    .asyncrst(comm_rst),
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    .syncrst(mem_rst_1)
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    );
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  sync_reset dot_sreset_1 (
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    .clk(dot_clk),
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    .asyncrst(comm_rst),
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    .syncrst(dot_rst_1)
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    );
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  /*
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   * combine all three resets - this produces a reset which is at least three clock cycles long in any clock domain
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   */
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  wire global_rst = clk_rst_1 && mem_rst_1 && dot_rst_1;
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  /*
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   * Now synchronize global reset back to the individual clocks
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   */
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  sync_reset clk_sreset_2 (
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    .clk(clk),
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    .asyncrst(global_rst),
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    .syncrst(clk_rst)
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    );
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  sync_reset mem_sreset_2 (
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    .clk(mem_clk),
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    .asyncrst(global_rst),
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    .syncrst(mem_rst)
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    );
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  sync_reset dot_sreset_2 (
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    .clk(dot_clk),
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    .asyncrst(global_rst),
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    .syncrst(dot_rst)
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    );
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  /*
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   * "Hard" reset signal. Goes low when the "rst" input pin goes low.
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   * Use two synchronizers so delay from async_rst to hard_rst is the same as the delay from async_rst to clk_rst.
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   */
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  wire hard_rst_1;
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  sync_reset hard_sreset_1 (
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    .clk(clk),
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    .asyncrst(clk_rst_0),
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    .syncrst(hard_rst_1)
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    );
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  sync_reset hard_sreset_2 (
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    .clk(clk),
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    .asyncrst(hard_rst_1),
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    .syncrst(hard_rst)
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    );
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endmodule
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/* not truncated */
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