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/*
2
 * rld.v
3
 *
4
 * Copyright (c) 2007 Koen De Vleeschauwer.
5
 *
6
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
7
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
8
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
9
 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
10
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
11
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
12
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
14
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
15
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
16
 * SUCH DAMAGE.
17
 */
18
 
19
/*
20
 * rld - run/length decoder.
21
 * input:  DCT coefficients, as run/signed level pairs, quantizer matrix updates. output: blocks of 64 DCT coefficients, signed.
22
 */
23
 
24
`include "timescale.v"
25
 
26
`undef DEBUG
27
//`define DEBUG 1
28
`undef DEBUG_IQUANT
29
//`define DEBUG_IQUANT 1
30
`undef CHECK
31
`ifdef __IVERILOG__
32
`define CHECK 1
33
`endif
34
 
35
module rld(clk, clk_en, rst,
36
  idct_fifo_almost_full,
37
  dct_coeff_rd_run, dct_coeff_rd_signed_level, dct_coeff_rd_end,                                            // dct run/level values input
38
  alternate_scan_rd, q_scale_type_rd, macroblock_intra_rd, intra_dc_precision_rd, quantiser_scale_code_rd,  // aux variables
39
  quant_wr_data_rd, quant_wr_addr_rd, quant_rst_rd, quant_wr_intra_rd, quant_wr_non_intra_rd,               // quantizer matrix updates
40
  quant_wr_chroma_intra_rd, quant_wr_chroma_non_intra_rd,
41
  rld_cmd_rd,                                                                                               // rld command: rld_DCT or RLD_QUANT
42
  rld_rd_valid, rld_rd_en,                                                                                  // rld_fifo read enable
43
  quant_rst, quant_rd_addr, quant_rd_intra_data, quant_rd_non_intra_data,                                   // interface with quantizer matrices
44
  quant_wr_data, quant_wr_addr, quant_wr_en_intra, quant_wr_en_non_intra,
45
  quant_wr_en_chroma_intra, quant_wr_en_chroma_non_intra, quant_alternate_scan,
46
  iquant_level, iquant_eob, iquant_valid                                                                    // interface with idct - dct coefficients output 
47
  );
48
 
49
  input                    clk;                          // clock
50
  input                    clk_en;                       // clock enable
51
  input                    rst;                          // synchronous active low reset
52
  input                    idct_fifo_almost_full;
53
  input               [5:0]dct_coeff_rd_run;
54
  input signed       [11:0]dct_coeff_rd_signed_level;
55
  input                    dct_coeff_rd_end;
56
  input                    alternate_scan_rd;            // choose zigzag scan order 0 or 1
57
  input                    q_scale_type_rd;              // whether linear or non-linear quantiser scale
58
  input                    macroblock_intra_rd;          // whether intra or non-intra macroblock
59
  input               [1:0]intra_dc_precision_rd;        // 
60
  input               [4:0]quantiser_scale_code_rd;      // quantiser scale code, par. 7.4.2.2
61
  input               [7:0]quant_wr_data_rd;
62
  input               [5:0]quant_wr_addr_rd;
63
  input                    quant_rst_rd;
64
  input                    quant_wr_intra_rd;
65
  input                    quant_wr_non_intra_rd;
66
  input                    quant_wr_chroma_intra_rd;
67
  input                    quant_wr_chroma_non_intra_rd;
68
  input               [1:0]rld_cmd_rd;
69
  input                    rld_rd_valid;
70
  output reg               rld_rd_en;
71
 
72
  output reg               quant_rst;
73
  output reg          [5:0]quant_rd_addr;             // address bus for reading quantizer matrix rams
74
  input               [7:0]quant_rd_intra_data;       // data bus for reading quantizer matrix rams
75
  input               [7:0]quant_rd_non_intra_data;   // data bus for reading quantizer matrix rams
76
  output reg          [7:0]quant_wr_data;
77
  output reg          [5:0]quant_wr_addr;
78
  output reg               quant_wr_en_intra;
79
  output reg               quant_wr_en_non_intra;
80
  output reg               quant_wr_en_chroma_intra;
81
  output reg               quant_wr_en_chroma_non_intra;
82
  output reg               quant_alternate_scan;
83
 
84
  output reg signed  [11:0]iquant_level;              // inverse quantized dct coefficient
85
  output reg               iquant_eob;                // asserted at last inverse quantized dct coefficient of block
86
  output reg               iquant_valid;              // asserted when inverse quantized dct coefficient valid
87
 
88
  reg          [6:0]run;
89
  reg signed  [11:0]level;       // 12 bits
90
  wire signed [12:0]sign_level;  // 13 bits; sign(level): 0 if level == 0; 1 if level > 0; -1 if level < 0.
91
  reg               level_valid;
92
  reg               end_of_block;
93
  reg          [6:0]cnt;
94
  reg          [6:0]quantiser_scale;
95
 
96
  reg signed  [12:0]iquant_level_0; // 13 bits
97
  reg signed  [12:0]iquant_level_1; // 13 bits
98
  reg signed  [12:0]iquant_level_2; // 13 bits
99
  reg signed  [22:0]iquant_level_3; // 22 bits
100
  reg signed  [11:0]iquant_level_4; // 12 bits
101
  reg signed  [11:0]iquant_level_5; // 12 bits
102
  reg         [14:0]iquant_factor_2; // 15 bits
103
  reg          [5:0]iquant_addr_0;
104
  reg          [5:0]iquant_addr_1;
105
  reg          [5:0]iquant_addr_2;
106
  reg          [5:0]iquant_addr_3;
107
  reg          [5:0]iquant_addr_4;
108
  reg          [5:0]iquant_addr_5;
109
  reg               iquant_intra_dc;
110
  reg               iquant_intra_dc_0;
111
  reg               iquant_intra_dc_1;
112
  reg               iquant_intra_dc_2;
113
  reg               iquant_eob_0;
114
  reg               iquant_eob_1;
115
  reg               iquant_eob_2;
116
  reg               iquant_eob_3;
117
  reg               iquant_eob_4;
118
  reg               iquant_eob_5;
119
  reg               iquant_valid_0;
120
  reg               iquant_valid_1;
121
  reg               iquant_valid_2;
122
  reg               iquant_valid_3;
123
  reg               iquant_valid_4;
124
  reg               iquant_valid_5;
125
 
126
  reg               iquant_oddness;
127
  reg               iquant_valid_out_0;
128
  reg               iquant_eob_out_0;
129
 
130
  reg          [6:0]ram_rd_addr;
131
  wire        [11:0]ram0_rd_data;
132
  wire        [11:0]ram1_rd_data;
133
  reg          [5:0]ram_wr_addr;
134
  reg         [11:0]ram_wr_data;
135
  reg               ram0_wr_enable;
136
  reg               ram1_wr_enable;
137
  reg               ram0_rd_enable;
138
  reg               ram1_rd_enable;
139
  reg               ram_write_select;
140
  reg               ram_initialized;          // reset at powerup, set after first block is written.
141
 
142
  reg          [2:0]state;
143
  reg          [2:0]next;
144
 
145
  parameter [2:0]
146
    STATE_INIT      = 3'd0,
147
    STATE_IDLE      = 3'd1,
148
    STATE_RUN       = 3'd2,
149
    STATE_LEVEL     = 3'd3,
150
    STATE_END_RUN   = 3'd4,
151
    STATE_QUANT     = 3'd5;
152
 
153
`include "zigzag_table.v"
154
`include "vld_codes.v"
155
 
156
/* next state logic */
157
  always @*
158
    case (state)
159
      STATE_INIT:                 if (idct_fifo_almost_full) next = STATE_INIT;
160
                                  else next = STATE_IDLE;
161
 
162
      STATE_IDLE:                 if (~rld_rd_valid) next = STATE_IDLE;                                                                // wait for next input
163
                                  else if ((rld_cmd_rd == RLD_DCT) && dct_coeff_rd_end) next = STATE_END_RUN;                             // end of block received
164
                                  else if ((rld_cmd_rd == RLD_DCT) && (cnt <= 7'd63) && (dct_coeff_rd_run == 6'd0)) next = STATE_LEVEL;   // output level
165
                                  else if ((rld_cmd_rd == RLD_DCT) && (cnt <= 7'd63)) next = STATE_RUN;                                // output run of zeroes
166
                                  else if (rld_cmd_rd == RLD_QUANT) next = STATE_QUANT;                                                // update quantiser matrices
167
                                  else next = STATE_IDLE;
168
 
169
 
170
      STATE_RUN:                  if (cnt == 7'd63) next = STATE_IDLE;                                             // all 64 levels have been output. 
171
                                  else if (run == 6'd1) next = STATE_LEVEL;                                        // run of zeroes has been output. output level next.
172
                                  else next = STATE_RUN;                                                           // output run of zeroes 
173
 
174
      STATE_LEVEL:                if (cnt == 7'd63) next = STATE_IDLE;                                             // all 64 levels have been output.
175
                                  else next = STATE_IDLE;                                                          // level has been output. wait for next coefficient.
176
 
177
      STATE_END_RUN:              if (cnt >= 7'd63) next = STATE_INIT;                                             // final zeroes have been output. wait for next block.
178
                                  else next = STATE_END_RUN;                                                       // output end run of zeroes
179
 
180
      STATE_QUANT:                next = STATE_IDLE;                                                               // update quantiser matrix
181
 
182
      default                     next = STATE_INIT;
183
    endcase
184
 
185
/* state */
186
  always @(posedge clk)
187
    if(~rst) state <= STATE_INIT;
188
    else if (clk_en) state <= next;
189
    else  state <= state;
190
 
191
/* buffer fifo output */
192
  reg                 [5:0]dct_coeff_run;
193
  reg signed         [11:0]dct_coeff_signed_level;
194
  reg                      dct_coeff_end;
195
  reg                      alternate_scan;            // choose zigzag scan order 0 or 1
196
  reg                      q_scale_type;              // whether linear or non-linear quantiser scale
197
  reg                      macroblock_intra;          // whether intra or non-intra macroblock
198
  reg                 [1:0]intra_dc_precision;        // 
199
  reg                 [4:0]quantiser_scale_code;      // quantiser scale code, par. 7.4.2.2
200
 
201
  always @(posedge clk)
202
    if (~rst) dct_coeff_run <= 6'd0;
203
    else if (clk_en && rld_rd_valid) dct_coeff_run <= dct_coeff_rd_run;
204
    else  dct_coeff_run <= dct_coeff_run;
205
 
206
  always @(posedge clk)
207
    if (~rst) dct_coeff_signed_level <= 12'd0;
208
    else if (clk_en && rld_rd_valid) dct_coeff_signed_level <= dct_coeff_rd_signed_level;
209
    else  dct_coeff_signed_level <= dct_coeff_signed_level;
210
 
211
  always @(posedge clk)
212
    if (~rst) dct_coeff_end <= 1'd0;
213
    else if (clk_en && rld_rd_valid) dct_coeff_end <= dct_coeff_rd_end;
214
    else  dct_coeff_end <= dct_coeff_end;
215
 
216
  always @(posedge clk)
217
    if (~rst) alternate_scan <= 1'd0;
218
    else if (clk_en && rld_rd_valid) alternate_scan <= alternate_scan_rd;
219
    else  alternate_scan <= alternate_scan;
220
 
221
  always @(posedge clk)
222
    if (~rst) q_scale_type <= 1'd0;
223
    else if (clk_en && rld_rd_valid) q_scale_type <= q_scale_type_rd;
224
    else  q_scale_type <= q_scale_type;
225
 
226
  always @(posedge clk)
227
    if (~rst) macroblock_intra <= 1'd0;
228
    else if (clk_en && rld_rd_valid) macroblock_intra <= macroblock_intra_rd;
229
    else  macroblock_intra <= macroblock_intra;
230
 
231
  always @(posedge clk)
232
    if (~rst) intra_dc_precision <= 2'd0;
233
    else if (clk_en && rld_rd_valid) intra_dc_precision <= intra_dc_precision_rd;
234
    else  intra_dc_precision <= intra_dc_precision;
235
 
236
  always @(posedge clk)
237
    if (~rst) quantiser_scale_code <= 5'd0;
238
    else if (clk_en && rld_rd_valid) quantiser_scale_code <= quantiser_scale_code_rd;
239
    else  quantiser_scale_code <= quantiser_scale_code;
240
 
241
/* internal registers */
242
 
243
  always @(posedge clk)
244
    if (~rst) run <= 6'd0;
245
    else if (clk_en && (state == STATE_IDLE)) run <= dct_coeff_rd_run;
246
    else if (clk_en && (state == STATE_RUN)) run <= run - 6'd1;
247
    else run <= run;
248
 
249
  always @(posedge clk)
250
    if (~rst) cnt <= 6'd0;
251
    else if (clk_en && (state == STATE_INIT)) cnt <= 6'd0;
252
    else if (clk_en && ((state == STATE_RUN) || (state == STATE_LEVEL) || (state == STATE_END_RUN))) cnt <= cnt + 6'd1;
253
    else cnt <= cnt;
254
 
255
  always @(posedge clk)
256
    if (~rst) level <= 12'd0;
257
    else if (clk_en && ((state == STATE_RUN) || (state == STATE_END_RUN))) level <= 12'd0;
258
    else if (clk_en && (state == STATE_LEVEL)) level <= dct_coeff_signed_level;
259
    else level <= level;
260
 
261
  always @(posedge clk)
262
    if (~rst) level_valid <= 1'd0;
263
    else if (clk_en) level_valid <= ((state == STATE_RUN) || (state == STATE_LEVEL) || (state == STATE_END_RUN)) && (cnt <= 6'd63);
264
    else level_valid <= level_valid;
265
 
266
  always @(posedge clk)
267
    if (~rst) end_of_block <= 1'd0;
268
    else if (clk_en) end_of_block <= ((state == STATE_RUN) || (state == STATE_LEVEL) || (state == STATE_END_RUN)) && (cnt == 6'd63);
269
    else end_of_block <= end_of_block;
270
 
271
  always @(posedge clk)
272
    if (~rst) iquant_intra_dc <= 1'd0;
273
    else if (clk_en) iquant_intra_dc <= macroblock_intra && (cnt == 6'd0);
274
    else iquant_intra_dc <= iquant_intra_dc;
275
 
276
  always @(posedge clk)
277
    if (~rst) rld_rd_en <= 1'd0;
278
    else if (clk_en && (state == STATE_IDLE)) rld_rd_en <= ~rld_rd_en && ~rld_rd_valid;
279
    else if (clk_en) rld_rd_en <= 1'b0;
280
    else rld_rd_en <= rld_rd_en;
281
 
282
  /*
283
   * quantiser rams interface
284
   */
285
 
286
  always @(posedge clk)
287
    if (~rst) quant_rst <= 1'b0;
288
    else if (clk_en && (state == STATE_IDLE) && rld_rd_valid && (rld_cmd_rd == RLD_QUANT)) quant_rst <= quant_rst_rd;
289
    else if (clk_en) quant_rst <= 1'b0;
290
    else quant_rst <= quant_rst;
291
 
292
  always @(posedge clk)
293
    if (~rst) quant_rd_addr <= 6'd0;
294
    else if (clk_en) quant_rd_addr <= scan_reverse(quant_alternate_scan, cnt[5:0]); // do inverse zig-zag
295
    else quant_rd_addr <= quant_rd_addr;
296
 
297
  always @(posedge clk)
298
    if (~rst) quant_wr_data <= 8'b0;
299
    else if (clk_en && (state == STATE_IDLE) && rld_rd_valid && (rld_cmd_rd == RLD_QUANT)) quant_wr_data <= quant_wr_data_rd;
300
    else quant_wr_data <= quant_wr_data;
301
 
302
  always @(posedge clk)
303
    if (~rst) quant_wr_addr <= 6'b0;
304
    else if (clk_en && (state == STATE_IDLE) && rld_rd_valid && (rld_cmd_rd == RLD_QUANT)) quant_wr_addr <= quant_wr_addr_rd;
305
    else quant_wr_addr <= quant_wr_addr;
306
 
307
  always @(posedge clk)
308
    if (~rst) quant_wr_en_intra <= 1'b0;
309
    else if (clk_en && (state == STATE_IDLE) && rld_rd_valid && (rld_cmd_rd == RLD_QUANT)) quant_wr_en_intra <= quant_wr_intra_rd;
310
    else if (clk_en) quant_wr_en_intra <= 1'b0;
311
    else quant_wr_en_intra <= quant_wr_en_intra;
312
 
313
  always @(posedge clk)
314
    if (~rst) quant_wr_en_non_intra <= 1'b0;
315
    else if (clk_en && (state == STATE_IDLE) && rld_rd_valid && (rld_cmd_rd == RLD_QUANT)) quant_wr_en_non_intra <= quant_wr_non_intra_rd;
316
    else if (clk_en) quant_wr_en_non_intra <= 1'b0;
317
    else quant_wr_en_non_intra <= quant_wr_en_non_intra;
318
 
319
  always @(posedge clk)
320
    if (~rst) quant_wr_en_chroma_intra <= 1'b0;
321
    else if (clk_en && (state == STATE_IDLE) && rld_rd_valid && (rld_cmd_rd == RLD_QUANT)) quant_wr_en_chroma_intra <= quant_wr_chroma_intra_rd;
322
    else if (clk_en) quant_wr_en_chroma_intra <= 1'b0;
323
    else quant_wr_en_chroma_intra <= quant_wr_en_chroma_intra;
324
 
325
  always @(posedge clk)
326
    if (~rst) quant_wr_en_chroma_non_intra <= 1'b0;
327
    else if (clk_en && (state == STATE_IDLE) && rld_rd_valid && (rld_cmd_rd == RLD_QUANT)) quant_wr_en_chroma_non_intra <= quant_wr_chroma_non_intra_rd;
328
    else if (clk_en) quant_wr_en_chroma_non_intra <= 1'b0;
329
    else quant_wr_en_chroma_non_intra <= quant_wr_en_chroma_non_intra;
330
 
331
  always @(posedge clk)
332
    if (~rst) quant_alternate_scan <= 1'b0;
333
    else if (clk_en && (state == STATE_IDLE) && rld_rd_valid && ((rld_cmd_rd == RLD_DCT) || (rld_cmd_rd == RLD_QUANT))) quant_alternate_scan <= alternate_scan_rd;
334
    else quant_alternate_scan <= quant_alternate_scan;
335
 
336
  /*
337
   * inverse quantisation, pipelined. (par. 7.4)
338
   */
339
 
340
  /*
341
   * first stage. Special case of Intra DC coefficient. (par. 7.4.1)
342
   *
343
   */
344
  assign sign_level = { {12{level[11]}}, |level}; // +1 if level > 0 ; 0 if level = 0; -1 if level < 0
345
 
346
  always @(posedge clk)
347
    if (~rst) iquant_level_0 <= 13'd0;
348
    else if (clk_en)
349
      begin // Par. 7.4.2.3
350
        if (iquant_intra_dc)
351
          case (intra_dc_precision) // intra dc coefficient, par. 7.4.1
352
            2'd0: iquant_level_0 <= level << 3;
353
            2'd1: iquant_level_0 <= level << 2;
354
            2'd2: iquant_level_0 <= level << 1;
355
            2'd3: iquant_level_0 <= {level[11], level}; // sign extend level
356
          endcase
357
        else if (macroblock_intra) // intra block but not dc coefficient
358
          iquant_level_0 <= level << 1; // iquant_valid_0 <= 2 * level (par. 7.4.2.3)
359
        else // non-intra block
360
          iquant_level_0 <= (level <<< 1) + sign_level; // iquant_valid_0 <= 2 * level + k; k = sign(level) (par. 7.4.2.3)
361
      end
362
    else iquant_level_0 <= iquant_level_0;
363
 
364
  /*
365
   * "oddness" of sum of previous iquant_levels. See par. 7.4.4, note 1.
366
   */
367
 
368
  always @(posedge clk)
369
    if (~rst) iquant_oddness <= 1'd0;
370
    else if (clk_en && iquant_valid_4 && iquant_eob_4) iquant_oddness <= 1'b0;
371
    else if (clk_en && iquant_valid_4) iquant_oddness <= iquant_oddness ^ iquant_level_4[0];
372
    else iquant_oddness <= iquant_oddness;
373
 
374
  /*
375
   * "oddness" of sum of all iquant_levels (previous and current). See par. 7.4.4, note 1.
376
   */
377
 
378
  wire iquant_oddness_sum = iquant_oddness ^ iquant_level_4[0];
379
  wire signed [15:0]iquant_factor_2_signed = {1'b0, iquant_factor_2};
380
  wire signed [22:0]iquant_level_3_correction = {17'b0, {5{iquant_level_2[12]}}};
381
 
382
  always @(posedge clk)
383
    if (~rst)
384
      begin
385
        iquant_level_1 <= 13'd0;
386
        iquant_level_2 <= 13'd0;
387
        iquant_level_3 <= 18'd0;
388
        iquant_level_4 <= 12'd0;
389
        iquant_level_5 <= 12'd0;
390
      end
391
    else if (clk_en)
392
      begin
393
        iquant_level_1 <= iquant_level_0;
394
        iquant_level_2 <= iquant_level_1;
395
        if (iquant_intra_dc_2)
396
          iquant_level_3 <= {{10{iquant_level_2[12]}}, iquant_level_2} ; // sign extend
397
        else
398
          /*
399
           * par. 7.4.2.3, note 1: the above equation uses the "/" operator as defined in 4.1
400
           * par. 4.1 defines / as Integer division with truncation of the result toward zero.
401
           * For example, 7/4 and -7/-4 are truncated to 1 and -7/4 and 7/-4 are truncated to -1.
402
           *
403
           * >>> 5 divides positive numbers correctly by 32.
404
           * It does not correctly divide negative numbers by 32; for instance -1 >>> 5 is -1.
405
           * For correct results, add sd31 to negative numbers.
406
           * Here: add 5'bsssss, with s the sign bit of the product.
407
           */
408
          // Xilinx ISE 6.3 doesn't know $signed
409
          //iquant_level_3 <= (iquant_level_2 * $signed({1'b0, iquant_factor_2}) + $signed({5{iquant_level_2[12]}})) >>> 5; // signed multiply
410
          iquant_level_3 <= (iquant_level_2 * iquant_factor_2_signed + iquant_level_3_correction) >>> 5; // signed multiply
411
        if ((iquant_level_3[22:11] == 12'b000000000000) || (iquant_level_3[22:11] == 12'b111111111111))
412
          iquant_level_4 <= iquant_level_3[11:0];
413
        else
414
          iquant_level_4 <= {iquant_level_3[22], {11{~iquant_level_3[22]}}}; // Saturation, par. 7.4.3
415
        iquant_level_5 <= (iquant_oddness_sum || ~iquant_eob_4) ? iquant_level_4 : {iquant_level_4[11:1], ~iquant_level_4[0]}; // Mismatch control, par. 7.4.4, implemented as of note 1.
416
      end
417
    else
418
      begin
419
        iquant_level_1 <= iquant_level_1;
420
        iquant_level_2 <= iquant_level_2;
421
        iquant_level_3 <= iquant_level_3;
422
        iquant_level_4 <= iquant_level_4;
423
        iquant_level_5 <= iquant_level_5;
424
      end
425
 
426
  wire [7:0]quant_mat = macroblock_intra ? quant_rd_intra_data : quant_rd_non_intra_data;
427
 
428
  reg          [6:0]quantiser_scale_0;
429
  reg          [6:0]quantiser_scale_1;
430
 
431
  always @(posedge clk)
432
    if (~rst)
433
      begin
434
        quantiser_scale_0 <= 7'd0;
435
        quantiser_scale_1 <= 7'd0;
436
      end
437
    else if (clk_en)
438
      begin
439
        quantiser_scale_0 <= quantiser_scale;
440
        quantiser_scale_1 <= quantiser_scale_0;
441
      end
442
    else
443
      begin
444
        quantiser_scale_0 <= quantiser_scale_0;
445
        quantiser_scale_1 <= quantiser_scale_1;
446
      end
447
 
448
  always @(posedge clk)
449
    if (~rst) iquant_factor_2 <= 15'd0;
450
    else if (clk_en) iquant_factor_2 <= quantiser_scale_1 * quant_mat; // unsigned multiply
451
    else iquant_factor_2 <= iquant_factor_2;
452
 
453
  always @(posedge clk)
454
    if (~rst)
455
      begin
456
        iquant_addr_0 <= 6'b0;
457
        iquant_addr_1 <= 6'b0;
458
        iquant_addr_2 <= 6'b0;
459
        iquant_addr_3 <= 6'b0;
460
        iquant_addr_4 <= 6'b0;
461
        iquant_addr_5 <= 6'b0;
462
      end
463
    else if (clk_en)
464
      begin
465
        iquant_addr_0 <= quant_rd_addr;
466
        iquant_addr_1 <= iquant_addr_0;
467
        iquant_addr_2 <= iquant_addr_1;
468
        iquant_addr_3 <= iquant_addr_2;
469
        iquant_addr_4 <= iquant_addr_3;
470
        iquant_addr_5 <= iquant_addr_4;
471
      end
472
    else
473
      begin
474
        iquant_addr_0 <= iquant_addr_0;
475
        iquant_addr_1 <= iquant_addr_1;
476
        iquant_addr_2 <= iquant_addr_2;
477
        iquant_addr_3 <= iquant_addr_3;
478
        iquant_addr_4 <= iquant_addr_4;
479
        iquant_addr_5 <= iquant_addr_5;
480
      end
481
 
482
  always @(posedge clk)
483
    if (~rst)
484
      begin
485
        iquant_valid_0 <= 1'b0;
486
        iquant_valid_1 <= 1'b0;
487
        iquant_valid_2 <= 1'b0;
488
        iquant_valid_3 <= 1'b0;
489
        iquant_valid_4 <= 1'b0;
490
        iquant_valid_5 <= 1'b0;
491
      end
492
    else if (clk_en)
493
      begin
494
        iquant_valid_0 <= level_valid;
495
        iquant_valid_1 <= iquant_valid_0;
496
        iquant_valid_2 <= iquant_valid_1;
497
        iquant_valid_3 <= iquant_valid_2;
498
        iquant_valid_4 <= iquant_valid_3;
499
        iquant_valid_5 <= iquant_valid_4;
500
      end
501
    else
502
      begin
503
        iquant_valid_0 <= iquant_valid_0;
504
        iquant_valid_1 <= iquant_valid_1;
505
        iquant_valid_2 <= iquant_valid_2;
506
        iquant_valid_3 <= iquant_valid_3;
507
        iquant_valid_4 <= iquant_valid_4;
508
        iquant_valid_5 <= iquant_valid_5;
509
      end
510
 
511
  always @(posedge clk)
512
    if (~rst)
513
      begin
514
        iquant_intra_dc_0 <= 1'b0;
515
        iquant_intra_dc_1 <= 1'b0;
516
        iquant_intra_dc_2 <= 1'b0;
517
      end
518
    else if (clk_en)
519
      begin
520
        iquant_intra_dc_0 <= iquant_intra_dc;
521
        iquant_intra_dc_1 <= iquant_intra_dc_0;
522
        iquant_intra_dc_2 <= iquant_intra_dc_1;
523
      end
524
    else
525
      begin
526
        iquant_intra_dc_0 <= iquant_intra_dc_0;
527
        iquant_intra_dc_1 <= iquant_intra_dc_1;
528
        iquant_intra_dc_2 <= iquant_intra_dc_2;
529
      end
530
 
531
  always @(posedge clk)
532
    if (~rst)
533
      begin
534
        iquant_eob_0 <= 1'b0;
535
        iquant_eob_1 <= 1'b0;
536
        iquant_eob_2 <= 1'b0;
537
        iquant_eob_3 <= 1'b0;
538
        iquant_eob_4 <= 1'b0;
539
        iquant_eob_5 <= 1'b0;
540
      end
541
    else if (clk_en)
542
      begin
543
        iquant_eob_0 <= end_of_block;
544
        iquant_eob_1 <= iquant_eob_0;
545
        iquant_eob_2 <= iquant_eob_1;
546
        iquant_eob_3 <= iquant_eob_2;
547
        iquant_eob_4 <= iquant_eob_3;
548
        iquant_eob_5 <= iquant_eob_4;
549
      end
550
    else
551
      begin
552
        iquant_eob_0 <= iquant_eob_0;
553
        iquant_eob_1 <= iquant_eob_1;
554
        iquant_eob_2 <= iquant_eob_2;
555
        iquant_eob_3 <= iquant_eob_3;
556
        iquant_eob_4 <= iquant_eob_4;
557
        iquant_eob_5 <= iquant_eob_5;
558
      end
559
 
560
  /* ram select */
561
 
562
  always @(posedge clk)
563
    if (~rst) ram_write_select <= 1'd0;
564
    else if (clk_en && iquant_valid_5 && iquant_eob_5) ram_write_select <= ~ram_write_select;
565
    else ram_write_select <= ram_write_select;
566
 
567
  always @(posedge clk)
568
    if (~rst) ram_initialized <= 1'd0; // reset at powerup
569
    else if (clk_en && iquant_valid_5) ram_initialized <= ram_initialized || iquant_eob_5; // set once first block has been written
570
    else ram_initialized <= ram_initialized;
571
 
572
  /* write to ram */
573
 
574
  always @(posedge clk)
575
    if (~rst) ram_wr_addr <= 6'd0;
576
    else if (clk_en) ram_wr_addr <= iquant_addr_5;
577
    else ram_wr_addr <= ram_wr_addr;
578
 
579
  always @(posedge clk)
580
    if (~rst) ram_wr_data <= 12'd0;
581
    else if (clk_en) ram_wr_data <= iquant_level_5;
582
    else ram_wr_data <= ram_wr_data;
583
 
584
  always @(posedge clk)
585
    if (~rst) ram0_wr_enable <= 1'b0;
586
    else if (clk_en) ram0_wr_enable <= iquant_valid_5 && ram_write_select;
587
    else ram0_wr_enable <= ram0_wr_enable;
588
 
589
  always @(posedge clk)
590
    if (~rst) ram1_wr_enable <= 1'b0;
591
    else if (clk_en) ram1_wr_enable <= iquant_valid_5 && ~ram_write_select;
592
    else ram1_wr_enable <= ram1_wr_enable;
593
 
594
  /* read from ram */
595
 
596
  always @(posedge clk)
597
    if (~rst) ram0_rd_enable <= 1'b0;
598
    else if (clk_en && iquant_valid_5 && iquant_eob_5) ram0_rd_enable <= ram_write_select;
599
    else ram0_rd_enable <= ram0_rd_enable;
600
 
601
  always @(posedge clk)
602
    if (~rst) ram1_rd_enable <= 1'b0;
603
    else if (clk_en && iquant_valid_5 && iquant_eob_5) ram1_rd_enable <= ~ram_write_select;
604
    else ram1_rd_enable <= ram1_rd_enable;
605
 
606
  /* ram_rd_addr counts from 0 to 64; 64 being "idle". */
607
  always @(posedge clk)
608
    if (~rst) ram_rd_addr <= 7'd64;
609
    else if (clk_en && iquant_valid_5 && iquant_eob_5) ram_rd_addr <= 6'd0;
610
    else if (clk_en && ~ram_rd_addr[6] ) ram_rd_addr <= ram_rd_addr + 1'd1; // count to 64
611
    else ram_rd_addr <= ram_rd_addr;
612
 
613
  always @(posedge clk)
614
    if (~rst) iquant_level <= 12'd0;
615
    else if (clk_en && ram_initialized) iquant_level <= ram_write_select ? ram1_rd_data : ram0_rd_data;
616
    else iquant_level <= iquant_level;
617
 
618
  always @(posedge clk)
619
    if (~rst) iquant_valid_out_0 <= 1'd0;
620
    else if (clk_en) iquant_valid_out_0 <= ~ram_rd_addr[6] && ram_initialized;
621
    else iquant_valid_out_0 <= iquant_valid_out_0;
622
 
623
  always @(posedge clk)
624
    if (~rst) iquant_eob_out_0 <= 1'd0;
625
    else if (clk_en) iquant_eob_out_0 <= (ram_rd_addr == 6'd63);
626
    else iquant_eob_out_0 <= iquant_eob_out_0;
627
 
628
  always @(posedge clk)
629
    if (~rst) iquant_valid <= 1'd0;
630
    else if (clk_en) iquant_valid <= iquant_valid_out_0;
631
    else iquant_valid <= iquant_valid;
632
 
633
  always @(posedge clk)
634
    if (~rst) iquant_eob <= 1'd0;
635
    else if (clk_en) iquant_eob <= iquant_eob_out_0;
636
    else iquant_eob <= iquant_eob;
637
 
638
  /*
639
   * The two rams for un-zigzagging the dct coefficients.
640
   * One is being written while the other is being read.
641
   */
642
 
643
  dpram_sc
644
    #(.addr_width(6),                                         // number of bits in address bus
645
    .dta_width(12))                                           // number of bits in data bus
646
    ram0 (
647
    .rst(rst),                                                // reset, active low
648
    .clk(clk),                                                // clock, rising edge trigger
649
    .wr_en(ram0_wr_enable),                                   // write enable, active high
650
    .wr_addr(ram_wr_addr),                                    // write address
651
    .din(ram_wr_data),                                        // data input
652
    .rd_en(ram0_rd_enable),                                   // read enable, active high
653
    .rd_addr(ram_rd_addr[5:0]),                               // read address
654
    .dout(ram0_rd_data)                                       // data output
655
    );
656
 
657
  dpram_sc
658
    #(.addr_width(6),                                         // number of bits in address bus
659
    .dta_width(12))                                           // number of bits in data bus
660
    ram1 (
661
    .rst(rst),                                                // reset, active low
662
    .clk(clk),                                                // clock, rising edge trigger
663
    .wr_en(ram1_wr_enable),                                   // write enable, active high
664
    .wr_addr(ram_wr_addr),                                    // write address
665
    .din(ram_wr_data),                                        // data input
666
    .rd_en(ram1_rd_enable),                                   // read enable, active high
667
    .rd_addr(ram_rd_addr[5:0]),                               // read address
668
    .dout(ram1_rd_data)                                       // data output
669
    );
670
 
671
  /* Calculate quantiser scale, using Table 7-6, par. 7.4.2.2 */
672
 
673
  always @(posedge clk)
674
    if (~rst) quantiser_scale <= 7'd0;
675
    else if (clk_en) quantiser_scale <= q_scale_type ? non_linear_quantiser_scale(quantiser_scale_code) : {1'b0, quantiser_scale_code, 1'b0};
676
    else quantiser_scale <= quantiser_scale;
677
 
678
  /*
679
   * Table 7-6: Relation between quantiser_scale and quantiser_scale_code
680
   */
681
 
682
  function [6:0]non_linear_quantiser_scale;
683
    input [4:0]scale_code;
684
    begin
685
      casex(scale_code)
686
        5'd1:  non_linear_quantiser_scale = 7'd1;
687
        5'd2:  non_linear_quantiser_scale = 7'd2;
688
        5'd3:  non_linear_quantiser_scale = 7'd3;
689
        5'd4:  non_linear_quantiser_scale = 7'd4;
690
        5'd5:  non_linear_quantiser_scale = 7'd5;
691
        5'd6:  non_linear_quantiser_scale = 7'd6;
692
        5'd7:  non_linear_quantiser_scale = 7'd7;
693
        5'd8:  non_linear_quantiser_scale = 7'd8;
694
        5'd9:  non_linear_quantiser_scale = 7'd10;
695
        5'd10: non_linear_quantiser_scale = 7'd12;
696
        5'd11: non_linear_quantiser_scale = 7'd14;
697
        5'd12: non_linear_quantiser_scale = 7'd16;
698
        5'd13: non_linear_quantiser_scale = 7'd18;
699
        5'd14: non_linear_quantiser_scale = 7'd20;
700
        5'd15: non_linear_quantiser_scale = 7'd22;
701
        5'd16: non_linear_quantiser_scale = 7'd24;
702
        5'd17: non_linear_quantiser_scale = 7'd28;
703
        5'd18: non_linear_quantiser_scale = 7'd32;
704
        5'd19: non_linear_quantiser_scale = 7'd36;
705
        5'd20: non_linear_quantiser_scale = 7'd40;
706
        5'd21: non_linear_quantiser_scale = 7'd44;
707
        5'd22: non_linear_quantiser_scale = 7'd48;
708
        5'd23: non_linear_quantiser_scale = 7'd52;
709
        5'd24: non_linear_quantiser_scale = 7'd56;
710
        5'd25: non_linear_quantiser_scale = 7'd64;
711
        5'd26: non_linear_quantiser_scale = 7'd72;
712
        5'd27: non_linear_quantiser_scale = 7'd80;
713
        5'd28: non_linear_quantiser_scale = 7'd88;
714
        5'd29: non_linear_quantiser_scale = 7'd96;
715
        5'd30: non_linear_quantiser_scale = 7'd104;
716
        5'd31: non_linear_quantiser_scale = 7'd112;
717
        default non_linear_quantiser_scale = 7'd0; // Error
718
      endcase
719
    end
720
  endfunction
721
 
722
 
723
`ifdef CHECK
724
  always @(posedge clk)
725
    if (rst && clk_en && iquant_valid && (^iquant_level === 1'bx))
726
      begin
727
        $display ("%m\t*** Error: iquant value undefined ***");
728
        $stop;
729
      end
730
`endif
731
 
732
`ifdef DEBUG
733
/* show input runlength/level values */
734
always @(posedge clk)
735
  if (clk_en && rld_rd_valid)
736
    begin
737
      if (dct_coeff_end)
738
        begin
739
          $display ("%m\tDCT: end of block");
740
        end
741
      else
742
        begin
743
          $display ("%m\tDCT: %0d/%0d", dct_coeff_run, dct_coeff_signed_level);
744
        end
745
    end
746
`endif
747
 
748
 
749
`ifdef DEBUG_IQUANT
750
/* show output runlength/level values */
751
 
752
always @(posedge clk)
753
  if (clk_en && ((state == STATE_RUN) || (state == STATE_END_RUN) || (state == STATE_LEVEL)))
754
    begin
755
      $strobe ("%m\t\tlevel: %d", level);
756
    end
757
 
758
always @(posedge clk)
759
  if (clk_en)
760
    $strobe("%m\t\tcnt: %x run: %x rld_rd_en: %d", cnt, run, rld_rd_en);
761
 
762
always @(posedge clk)
763
  if (clk_en)
764
    begin
765
      $strobe("%m\t\tlevel:          %5d quant_rd_addr: %2d level_valid_0:  %d end_of_block: %d macroblock_intra:", level, quant_rd_addr, level_valid, end_of_block, macroblock_intra);
766
      $strobe("%m\t\tiquant_level_0: %5d iquant_addr_0: %2d iquant_valid_0: %d iquant_eob_0: %d iquant_intra_dc_0: %d quant_mat: %d quantiser_scale: %d ", iquant_level_0, iquant_addr_0, iquant_valid_0, iquant_eob_0, iquant_intra_dc_0, quant_mat , quantiser_scale);
767
      $strobe("%m\t\tiquant_level_1: %5d iquant_addr_1: %2d iquant_valid_1: %d iquant_eob_1: %d iquant_intra_dc_1: %d quant_mat: %d quantiser_scale: %d", iquant_level_1, iquant_addr_1, iquant_valid_1, iquant_eob_1, iquant_intra_dc_1,quant_mat , quantiser_scale);
768
      $strobe("%m\t\tiquant_level_2: %5d iquant_addr_2: %2d iquant_valid_2: %d iquant_eob_2: %d iquant_intra_dc_2: %d quant_mat: %d quantiser_scale: %d iquant_factor_2: %d", iquant_level_2, iquant_addr_2, iquant_valid_2, iquant_eob_2, iquant_intra_dc_2, quant_mat , quantiser_scale, iquant_factor_2);
769
      $strobe("%m\t\tiquant_level_3: %5d iquant_addr_3: %2d iquant_valid_3: %d iquant_eob_3: %d", iquant_level_3, iquant_addr_3, iquant_valid_3, iquant_eob_3);
770
      $strobe("%m\t\tiquant_level_4: %5d iquant_addr_4: %2d iquant_valid_4: %d iquant_eob_4: %d", iquant_level_4, iquant_addr_4, iquant_valid_4, iquant_eob_4);
771
      $strobe("%m\t\tiquant_level_5: %5d iquant_addr_5: %2d iquant_valid_5: %d iquant_eob_5: %d iquant_oddness: %d iquant_oddness_sum: %d", iquant_level_5, iquant_addr_5, iquant_valid_5, iquant_eob_5, iquant_oddness, iquant_oddness_sum);
772
      $strobe("%m\t\tiquant_level:   %5d ram_rd_addr:   %2d iquant_valid:   %d iquant_eob:   %d", iquant_level, ram_rd_addr, iquant_valid, iquant_eob);
773
    end
774
 
775
always @(posedge clk)
776
  if (clk_en)
777
    begin
778
      if (iquant_valid) $strobe("%m\t\tiquant_level", iquant_level);
779
    end
780
 
781
always @(posedge clk)
782
  if (clk_en)
783
    case (state)
784
      STATE_INIT:         #0 $display("%m\t\tSTATE_INIT");
785
      STATE_IDLE:         #0 $display("%m\t\tSTATE_IDLE");
786
      STATE_RUN:          #0 $display("%m\t\tSTATE_RUN");
787
      STATE_LEVEL:        #0 $display("%m\t\tSTATE_LEVEL");
788
      STATE_END_RUN:      #0 $display("%m\t\tSTATE_END_RUN");
789
      STATE_QUANT:        #0 $display("%m\t\tSTATE_QUANT");
790
      default             #0 $display("%m\t\t *** Unknown state %h *** ", state);
791
    endcase
792
 
793
`endif
794
 
795
endmodule
796
 
797
/*
798
 * rld_fifo - run/length decoder fifo.
799
 * input:  DCT coefficients, as run/signed level pairs. Quantizer updates. output: DCT coefficients, as run/signed level pairs. Quantizer updates.
800
 */
801
 
802
module rld_fifo(clk, clk_en, rst,
803
  dct_coeff_wr_run, dct_coeff_wr_signed_level, dct_coeff_wr_end,                                                  // dct run/level values input
804
  alternate_scan_wr, macroblock_intra_wr, intra_dc_precision_wr, q_scale_type_wr, quantiser_scale_code_wr,        // aux variables input
805
  quant_wr_data_wr, quant_wr_addr_wr,                                                                             // quantizer input
806
  quant_rst_wr, quant_wr_intra_wr, quant_wr_non_intra_wr, quant_wr_chroma_intra_wr, quant_wr_chroma_non_intra_wr, // quantizer input
807
  rld_cmd_wr, rld_wr_en, rld_wr_almost_full, rld_wr_overflow,                                                     // command to run-length decoding
808
  dct_coeff_rd_run, dct_coeff_rd_signed_level, dct_coeff_rd_end,                                                  // dct run/level values output
809
  alternate_scan_rd, macroblock_intra_rd, intra_dc_precision_rd, q_scale_type_rd, quantiser_scale_code_rd,        // aux variables output
810
  quant_wr_data_rd, quant_wr_addr_rd,                                                                             // quantizer output
811
  quant_rst_rd, quant_wr_intra_rd, quant_wr_non_intra_rd, quant_wr_chroma_intra_rd, quant_wr_chroma_non_intra_rd, // quantizer output
812
  rld_cmd_rd, rld_rd_en, rld_rd_valid                                                                             // command to run-length decoding
813
  );
814
 
815
  input                    clk;                              // clock
816
  input                    clk_en;                           // clock enable
817
  input                    rst;                              // synchronous active low reset
818
  input               [5:0]dct_coeff_wr_run;
819
  input signed       [11:0]dct_coeff_wr_signed_level;
820
  input                    dct_coeff_wr_end;
821
 
822
  input                    alternate_scan_wr;                // from slice - choose zigzag scan order 0 or 1
823
  input                    macroblock_intra_wr;              // from slice - whether intra or non-intra macroblock
824
  input               [1:0]intra_dc_precision_wr;            // from ves
825
  input                    q_scale_type_wr;                  // from ves - whether linear or non-linear quantiser scale
826
  input               [4:0]quantiser_scale_code_wr;          // from slice - quantiser scale code, par. 7.4.2.2
827
 
828
  input               [7:0]quant_wr_data_wr;                 // data bus for quantizer matrix rams
829
  input               [5:0]quant_wr_addr_wr;                 // address bus for quantizer matrix rams
830
  input                    quant_rst_wr;                     // reset quantizer matrices to default values
831
  input                    quant_wr_intra_wr;                // write to intra quantizer matrix
832
  input                    quant_wr_non_intra_wr;            // write to non-intra quantizer matrix
833
  input                    quant_wr_chroma_intra_wr;         // write to intra chroma quantizer matrix
834
  input                    quant_wr_chroma_non_intra_wr;     // write to non-intra chroma quantizer matrix
835
 
836
  input               [1:0]rld_cmd_wr;
837
  input                    rld_wr_en;
838
  output                   rld_wr_almost_full;               // ask vld to wait for rld
839
  output                   rld_wr_overflow;
840
 
841
  output              [5:0]dct_coeff_rd_run;
842
  output signed      [11:0]dct_coeff_rd_signed_level;
843
  output                   dct_coeff_rd_end;
844
 
845
  output                   alternate_scan_rd;
846
  output                   macroblock_intra_rd;
847
  output              [1:0]intra_dc_precision_rd;
848
  output                   q_scale_type_rd;
849
  output              [4:0]quantiser_scale_code_rd;
850
 
851
  output              [7:0]quant_wr_data_rd;                 // data bus for quantizer matrix rams
852
  output              [5:0]quant_wr_addr_rd;                 // address bus for quantizer matrix rams
853
  output                   quant_rst_rd;                     // reset quantizer matrices to default values
854
  output                   quant_wr_intra_rd;                // write to intra quantizer matrix
855
  output                   quant_wr_non_intra_rd;            // write to non-intra quantizer matrix
856
  output                   quant_wr_chroma_intra_rd;         // write to intra chroma quantizer matrix
857
  output                   quant_wr_chroma_non_intra_rd;     // write to non-intra chroma quantizer matrix
858
 
859
  output               [1:0]rld_cmd_rd;
860
  input                    rld_rd_en;                        // read dct run/level values
861
  output                   rld_rd_valid;
862
 
863
`include "fifo_size.v"
864
`include "vld_codes.v"
865
 
866
 /*
867
  * We write dct or iquant data to the fifo, depending upon rld_cmd.
868
  * Note alternate_scan and rld_cmd are common to both, so we put them in the same position (bits 0..2) in both cases.
869
  */
870
 
871
  wire                     alternate_scan_rd_dummy;
872
  wire                [1:0]rld_cmd_rd_dummy;
873
  wire                [8:0]dummy_1 = 9'b0;
874
  wire                [8:0]dummy_2;
875
 
876
  wire               [30:0]dct_wr_dta = {dct_coeff_wr_run, dct_coeff_wr_signed_level, dct_coeff_wr_end, macroblock_intra_wr, intra_dc_precision_wr, q_scale_type_wr, quantiser_scale_code_wr, alternate_scan_wr, rld_cmd_wr};
877
  wire               [30:0]quant_wr_dta = {dummy_1, quant_wr_data_wr, quant_wr_addr_wr, quant_rst_wr, quant_wr_intra_wr, quant_wr_non_intra_wr, quant_wr_chroma_intra_wr, quant_wr_chroma_non_intra_wr, alternate_scan_wr, rld_cmd_wr};
878
 
879
  wire               [30:0]rld_rd_dta;
880
  assign                   {dct_coeff_rd_run, dct_coeff_rd_signed_level, dct_coeff_rd_end, macroblock_intra_rd, intra_dc_precision_rd, q_scale_type_rd, quantiser_scale_code_rd, alternate_scan_rd, rld_cmd_rd} = rld_rd_dta;
881
  assign                   {dummy_2, quant_wr_data_rd, quant_wr_addr_rd, quant_rst_rd, quant_wr_intra_rd, quant_wr_non_intra_rd, quant_wr_chroma_intra_rd, quant_wr_chroma_non_intra_rd, alternate_scan_rd_dummy, rld_cmd_rd_dummy} = rld_rd_dta;
882
 
883
  fifo_sc
884
    #(.addr_width(RLD_DEPTH),
885
    .dta_width(9'd31),
886
    .prog_thresh(RLD_THRESHOLD))
887
    rld_fifo (
888
    .rst(rst),
889
    .clk(clk),
890
    .din((rld_cmd_wr == RLD_DCT) ? dct_wr_dta : quant_wr_dta),
891
    .wr_en(rld_wr_en && clk_en),
892
    .full(),
893
    .wr_ack(),
894
    .overflow(rld_wr_overflow),
895
    .prog_full(rld_wr_almost_full),
896
    .dout(rld_rd_dta),
897
    .rd_en(rld_rd_en && clk_en),
898
    .empty(),
899
    .valid(rld_rd_valid),
900
    .underflow(),
901
    .prog_empty()
902
    );
903
 
904
 
905
`ifdef CHECK
906
  always @(posedge clk)
907
    if (rld_wr_overflow)
908
      begin
909
        #0 $display("%m\t*** error: rld_fifo overflow. **");
910
        $stop;
911
      end
912
`endif
913
 
914
`ifdef DEBUG
915
always @(posedge clk)
916
  if (clk_en)
917
    begin
918
      $strobe("%m\tclk_en: %d dct_coeff_wr_run: %d dct_coeff_wr_signed_level: %d dct_coeff_wr_end: %d alternate_scan_wr: %d macroblock_intra_wr: %d intra_dc_precision_wr: %d q_scale_type_wr: %d quantiser_scale_code_wr: %d rld_cmd_wr: %d rld_wr_en: %d",
919
      clk_en, dct_coeff_wr_run, dct_coeff_wr_signed_level, dct_coeff_wr_end, alternate_scan_wr, macroblock_intra_wr, intra_dc_precision_wr, q_scale_type_wr, quantiser_scale_code_wr, rld_cmd_wr, rld_wr_en);
920
      $strobe("%m\tclk_en: %d quant_wr_data_wr: %d quant_wr_addr_wr: %d quant_rst_wr: %d quant_wr_intra_wr: %d quant_wr_non_intra_wr: %d quant_wr_chroma_intra_wr: %d quant_wr_chroma_non_intra_wr: %d rld_cmd_wr: %d rld_wr_en: %d",
921
      clk_en, quant_wr_data_wr, quant_wr_addr_wr, quant_rst_wr, quant_wr_intra_wr, quant_wr_non_intra_wr, quant_wr_chroma_intra_wr, quant_wr_chroma_non_intra_wr, rld_cmd_wr, rld_wr_en);
922
    end
923
 
924
`endif
925
endmodule
926
/* not truncated */

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