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[/] [mpeg2fpga/] [trunk/] [rtl/] [mpeg2/] [synchronizer.v] - Blame information for rev 2

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1 2 kdv
/*
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 * synchronizer.v
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 *
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 * Copyright (c) 2007 Koen De Vleeschauwer.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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 * SUCH DAMAGE.
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 */
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/*
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 * reset synchronizer.
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 * input: asynchronous reset asyncrst_n, active low.
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 * output: synchronous reset syncrst_n, active low, with a width of four clocks.
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 *
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 * After http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf , par. 6.0
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 */
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`undef DEBUG
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//`define DEBUG 1
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`include "timescale.v"
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module sync_reset (clk, asyncrst, syncrst);
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  input  clk, asyncrst;
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  output reg syncrst;
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  reg    [3:0]rff1;
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  always @(posedge clk or negedge asyncrst)
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    if (!asyncrst) {syncrst, rff1} <= 5'b0;
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    else           {syncrst, rff1} <= {rff1, 1'b1};
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endmodule
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/*
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 * register synchronizer.
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 * input: asynchronous register asyncreg
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 * output: syncreg, register synchronized to clk
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 * parameter 'width' determines register width.
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 */
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module sync_reg (clk, rst, asyncreg, syncreg);
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parameter width=8;
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  input                clk;
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  input                rst;  // synchronous with clk
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  input     [width-1:0]asyncreg;
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  output reg[width-1:0]syncreg;
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  reg   [width-1:0]rff1;
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  always @(posedge clk or negedge rst)
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    if (!rst) {syncreg, rff1} <= {(2*width){1'b0}};
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    else      {syncreg, rff1} <= {rff1, asyncreg};
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`ifdef DEBUG
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  always @(posedge clk)
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    $strobe("%m\trst: %h asyncreg : %h syncreg: %h", rst, asyncreg, syncreg);
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`endif
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endmodule
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/* not truncated */

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