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[/] [mpeg2fpga/] [trunk/] [rtl/] [mpeg2/] [xfifo_sc.v] - Blame information for rev 2

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/*
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 * fifo_sc.v
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 *
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 * Copyright (c) 2007 Koen De Vleeschauwer.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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 * SUCH DAMAGE.
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 */
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/*
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 * fifo with common clock for read and write port.
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 */
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`include "timescale.v"
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module xfifo_sc (
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        clk,
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        rst,
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        din,
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        wr_en,
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        full,
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        wr_ack,
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        overflow,
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        prog_full,
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        dout,
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        rd_en,
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        empty,
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        valid,
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        underflow,
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        prog_empty
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        );
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  parameter [8:0]dta_width=9'd8;      /* Data bus width */
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  parameter [8:0]addr_width=9'd8;     /* Address bus width, determines fifo size by evaluating 2^addr_width */
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  parameter [8:0]prog_thresh=9'd1;    /* Programmable threshold constant for prog_empty and prog_full */
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  input          clk;
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  input          rst;         /* low active sync master reset */
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  /* read port */
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  output reg [dta_width-1:0]dout; /* data output */
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  input          rd_en;       /* read enable */
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  output reg     empty;       /* asserted if fifo is empty; no additional reads can be performed */
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  output reg     valid;       /* valid (read acknowledge): indicates rd_en was asserted during previous clock cycle and data was succesfully read from fifo and placed on dout */
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  output reg     underflow;   /* underflow (read error): indicates rd_en was asserted during previous clock cycle but no data was read from fifo because fifo was empty */
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  output reg     prog_empty;  /* indicates the fifo has prog_thresh entries, or less. threshold for asserting prog_empty is prog_thresh */
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  /* write port */
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  input  [dta_width-1:0]din;  /* data input */
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  input          wr_en;       /* write enable */
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  output reg     full;        /* asserted if fifo is full; no additional writes can be performed */
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  output reg     overflow;    /* overflow (write error): indicates wr_en was asserted during previous clock cycle but no data was written to fifo because fifo was full */
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  output reg     wr_ack;      /* write acknowledge: indicates wr_en was asserted during previous clock cycle and data was succesfully written to fifo */
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  output reg     prog_full;   /* indicates the fifo has prog_thresh free entries, or less, left. threshold for asserting prog_full is 2^addr_width - prog_thresh */
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  /* Writing when the fifo is full, or reading while the fifo is empty, does not destroy the contents of the fifo. */
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  /*
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   * read and write addresses
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   */
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  reg  [addr_width:0]wr_addr;
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  reg  [addr_width:0]rd_addr;
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  reg  [addr_width:0]next_wr_addr;
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  reg  [addr_width:0]next_rd_addr;
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  always @*
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    if (wr_en && ~full) next_wr_addr = wr_addr + 1'b1;
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    else next_wr_addr = wr_addr;
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  always @*
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    if (rd_en && ~empty) next_rd_addr = rd_addr + 1'b1;
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    else next_rd_addr = rd_addr;
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  always @(posedge clk)
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    if (~rst) wr_addr <= 1'b0;
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    else wr_addr <= next_wr_addr;
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  always @(posedge clk)
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    if (~rst) rd_addr <= 1'b0;
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    else rd_addr <= next_rd_addr;
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  /*
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   * empty and full
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   */
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  always @(posedge clk)
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    if (~rst) empty <= 1'b1;
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    else empty <= (next_wr_addr == next_rd_addr);
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  always @(posedge clk)
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    if (~rst) full <= 1'b0;
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    else full <= (next_wr_addr[addr_width-1:0] == next_rd_addr[addr_width-1:0]) && (next_wr_addr[addr_width] != next_rd_addr[addr_width]);
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  /*
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   * valid and wr_ack
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   */
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  always @(posedge clk)
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    if (~rst) valid <= 1'b0;
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    else valid <= rd_en && ~empty;
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  always @(posedge clk)
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    if (~rst) wr_ack <= 1'b0;
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    else wr_ack <= wr_en && ~full;
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  /*
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   * underflow and overflow
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   */
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  always @(posedge clk)
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    if (~rst) underflow <= 1'b0;
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    else underflow <= rd_en && empty;
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  always @(posedge clk)
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    if (~rst) overflow <= 1'b0;
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    else overflow <= wr_en && full;
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  /*
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   * prog_empty and prog_full
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   */
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  wire [addr_width:0]next_count = next_wr_addr - next_rd_addr;
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  wire [addr_width:0]lower_threshold = prog_thresh + 1'b1;
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  wire [addr_width:0]max_count = 1'b1 << addr_width;
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  wire [addr_width:0]upper_threshold = max_count - lower_threshold;
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  always @(posedge clk)
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    if (~rst) prog_empty <= 1'b1;
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    else prog_empty <= (next_count < lower_threshold);
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  always @(posedge clk)
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    if (~rst) prog_full <= 1'b0;
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    else prog_full <= (next_count > upper_threshold);
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  /*
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   * dual-port ram w/registered output
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   */
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  reg    [dta_width-1:0]ram[(1 << addr_width)-1:0];
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  always @(posedge clk)
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    if (~rst) dout <= 0;
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    else if (~empty) dout <= ram[rd_addr[addr_width-1:0]];
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    else dout <= dout;
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  always @(posedge clk)
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    if (wr_en && ~full) ram[wr_addr[addr_width-1:0]] <= din;
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endmodule
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/* not truncated */

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