OpenCores
URL https://opencores.org/ocsvn/mpeg2fpga/mpeg2fpga/trunk

Subversion Repositories mpeg2fpga

[/] [mpeg2fpga/] [trunk/] [rtl/] [mpeg2/] [xilinx_fifo144.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 kdv
/*
2
 * xilinx_fifo144.v
3
 *
4
 * Copyright (c) 2007 Koen De Vleeschauwer.
5
 *
6
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
7
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
8
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
9
 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
10
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
11
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
12
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
14
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
15
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
16
 * SUCH DAMAGE.
17
 */
18
 
19
/*
20
 * FIFO144
21
 * Connect two 72-bit wide FIFO36_72 in parallel to create one 144-bit wide fifo.
22
 */
23
 
24
`include "timescale.v"
25
 
26
module FIFO144 (ALMOSTEMPTY, ALMOSTFULL, DO, EMPTY, FULL, RDERR, WRERR, DI, RDCLK, RDEN, RST, WRCLK, WREN);
27
 
28
  parameter [8:0]ALMOST_FULL_OFFSET=9'h080;
29
  parameter [8:0]ALMOST_EMPTY_OFFSET=9'h080;
30
  parameter DO_REG=1;
31
  parameter EN_SYN="FALSE";
32
 
33
  output ALMOSTEMPTY;
34
  output ALMOSTFULL;
35
  output [143:0]DO;
36
  output EMPTY;
37
  output FULL;
38
  output reg RDERR;
39
  output reg WRERR;
40
  input [143:0]DI;
41
  input RDCLK;
42
  input RDEN;
43
  input RST;
44
  input WRCLK;
45
  input WREN;
46
 
47
  wire fifo_wren;
48
  wire fifo_rden;
49
 
50
  wire [63:0]fifo1_di;
51
  wire [7:0]fifo1_dip;
52
  wire [63:0]fifo1_do;
53
  wire [7:0]fifo1_dop;
54
  wire fifo1_empty;
55
  wire fifo1_full;
56
  wire fifo1_almost_empty;
57
  wire fifo1_almost_full;
58
  wire fifo1_rderr;
59
  wire fifo1_wrerr;
60
 
61
  wire [63:0]fifo2_di;
62
  wire [7:0]fifo2_dip;
63
  wire [63:0]fifo2_do;
64
  wire [7:0]fifo2_dop;
65
  wire fifo2_empty;
66
  wire fifo2_full;
67
  wire fifo2_almost_empty;
68
  wire fifo2_almost_full;
69
  wire fifo2_rderr;
70
  wire fifo2_wrerr;
71
 
72
  assign DO = {fifo2_dop, fifo2_do, fifo1_dop, fifo1_do};
73
  assign {fifo2_dip,fifo2_di, fifo1_dip, fifo1_di} = DI;
74
 
75
  assign EMPTY = fifo1_empty || fifo2_empty;
76
  assign FULL = fifo1_full || fifo2_full;
77
  assign ALMOSTEMPTY = fifo1_almost_empty || fifo2_almost_empty;
78
  assign ALMOSTFULL = fifo1_almost_full || fifo2_almost_full;
79
 
80
  always @(posedge RDCLK)
81
    if (RST) RDERR <= 1'b0;
82
    else RDERR <= RDEN && EMPTY;
83
 
84
  always @(posedge WRCLK)
85
    if (RST) WRERR <= 1'b0;
86
    else WRERR <= WREN && FULL;
87
 
88
  assign fifo_wren = WREN && ~FULL;
89
  assign fifo_rden = RDEN && ~EMPTY;
90
 
91
  // FIFO36_72: 72x36k Synchronous/Asynchronous BlockRAM FIFO /w ECC
92
  //             Virtex-5
93
  // Xilinx HDL Libraries Guide, version 8.2.2
94
  FIFO36_72 #(
95
     .ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET),   // Sets almost full threshold
96
     .ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET), // Sets the almost empty threshold
97
     .DO_REG(DO_REG),                           // Enable output register (0 or 1)
98
                                                //   Must be 1 if EN_SYN = "FALSE"
99
     .EN_ECC_READ("FALSE"),                     // Enable ECC decoder, "TRUE" or "FALSE"
100
     .EN_ECC_WRITE("FALSE"),                    // Enable ECC encoder, "TRUE" or "FALSE"
101
     .EN_SYN(EN_SYN),                           // Specifies FIFO as Asynchronous ("FALSE")
102
                                                //   or Synchronous ("TRUE")
103
     .FIRST_WORD_FALL_THROUGH("FALSE")          // Sets the FIFO FWFT to "TRUE" or "FALSE
104
  ) FIFO36_72_slice0 (
105
     .ALMOSTEMPTY(fifo1_almost_empty),          // 1-bit almost empty output flag
106
     .ALMOSTFULL(fifo1_almost_full),            // 1-bit almost full output flag
107
     .DBITERR(),                                // 1-bit double bit error status output
108
     .DO(fifo1_do),                             // 32-bit data output
109
     .DOP(fifo1_dop),                           // 4-bit parity data output
110
     .ECCPARITY(),                              // 8-bit generated error correction parity
111
     .EMPTY(fifo1_empty),                       // 1-bit empty output flag
112
     .FULL(fifo1_full),                         // 1-bit full output flag
113
     .RDCOUNT(),                                // 9-bit read count output
114
     .RDERR(fifo1_rderr),                       // 1-bit read error output
115
     .SBITERR(),                                // 1-bit single bit error status output
116
     .WRCOUNT(),                                // 9-bit write count output
117
     .WRERR(fifo1_wrerr),                       // 1-bit write error
118
     .DI(fifo1_di),                             // 32-bit data input
119
     .DIP(fifo1_dip),                           // 4-bit parity input
120
     .RDCLK(RDCLK),                             // 1-bit read clock input
121
     .RDEN(fifo_rden),                          // 1-bit read enable input
122
     .RST(RST),                                 // 1-bit reset input
123
     .WRCLK(WRCLK),                             // 1-bit write clock input
124
     .WREN(fifo_wren)                           // 1-bit write enable input
125
  );
126
 
127
  // FIFO36_72: 72x36k Synchronous/Asynchronous BlockRAM FIFO /w ECC
128
  //             Virtex-5
129
  // Xilinx HDL Libraries Guide, version 8.2.2
130
  FIFO36_72 #(
131
     .ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET),   // Sets almost full threshold
132
     .ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET), // Sets the almost empty threshold
133
     .DO_REG(DO_REG),                           // Enable output register (0 or 1)
134
                                                //   Must be 1 if EN_SYN = "FALSE"
135
     .EN_ECC_READ("FALSE"),                     // Enable ECC decoder, "TRUE" or "FALSE"
136
     .EN_ECC_WRITE("FALSE"),                    // Enable ECC encoder, "TRUE" or "FALSE"
137
     .EN_SYN(EN_SYN),                           // Specifies FIFO as Asynchronous ("FALSE")
138
                                                //   or Synchronous ("TRUE")
139
     .FIRST_WORD_FALL_THROUGH("FALSE")          // Sets the FIFO FWFT to "TRUE" or "FALSE
140
  ) FIFO36_72_slice1 (
141
     .ALMOSTEMPTY(fifo2_almost_empty),          // 1-bit almost empty output flag
142
     .ALMOSTFULL(fifo2_almost_full),            // 1-bit almost full output flag
143
     .DBITERR(),                                // 1-bit double bit error status output
144
     .DO(fifo2_do),                             // 32-bit data output
145
     .DOP(fifo2_dop),                           // 4-bit parity data output
146
     .ECCPARITY(),                              // 8-bit generated error correction parity
147
     .EMPTY(fifo2_empty),                       // 1-bit empty output flag
148
     .FULL(fifo2_full),                         // 1-bit full output flag
149
     .RDCOUNT(),                                // 9-bit read count output
150
     .RDERR(fifo2_rderr),                       // 1-bit read error output
151
     .SBITERR(),                                // 1-bit single bit error status output
152
     .WRCOUNT(),                                // 9-bit write count output
153
     .WRERR(fifo2_wrerr),                       // 1-bit write error
154
     .DI(fifo2_di),                             // 32-bit data input
155
     .DIP(fifo2_dip),                           // 4-bit parity input
156
     .RDCLK(RDCLK),                             // 1-bit read clock input
157
     .RDEN(fifo_rden),                          // 1-bit read enable input
158
     .RST(RST),                                 // 1-bit reset input
159
     .WRCLK(WRCLK),                             // 1-bit write clock input
160
     .WREN(fifo_wren)                           // 1-bit write enable input
161
  );
162
 
163
`ifdef CHECK_GENERATE
164
  initial
165
    $display("%m: fifo parameters: ALMOST_FULL_OFFSET=%0d ALMOST_EMPTY_OFFSET=%0d DO_REG=%0d EN_SYN=%s",
166
      ALMOST_FULL_OFFSET, ALMOST_EMPTY_OFFSET, DO_REG, EN_SYN);
167
`endif
168
 
169
endmodule
170
/* not truncated */
171
 

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.