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[/] [mpeg2fpga/] [trunk/] [rtl/] [mpeg2/] [xilinx_fifo_dc.v] - Blame information for rev 2

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/*
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 * xilinx_fifo_dc.v
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 *
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 * Copyright (c) 2007 Koen De Vleeschauwer.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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 * SUCH DAMAGE.
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 */
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/*
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 * fifo with independent clock for read and write port.
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 */
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`include "timescale.v"
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module xilinx_fifo_dc (
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        rst,
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        wr_clk,
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        din,
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        wr_en,
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        full,
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        wr_ack,
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        overflow,
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        prog_full,
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        rd_clk,
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        dout,
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        rd_en,
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        empty,
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        valid,
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        underflow,
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        prog_empty
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        );
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  parameter [8:0]dta_width=9'd8;      /* Data bus width */
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  parameter [8:0]addr_width=9'd8;     /* Address bus width, determines fifo size by evaluating 2^addr_width */
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  parameter [8:0]prog_thresh=9'd1;    /* Programmable threshold constant for prog_empty and prog_full */
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  input          rst;         /* low active sync master reset */
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  /* read port */
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  input          rd_clk;      /* read clock. positive edge active */
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  output [dta_width-1:0]dout; /* data output */
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  input          rd_en;       /* read enable */
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  output         empty;       /* asserted if fifo is empty; no additional reads can be performed */
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  output         valid;       /* valid (read acknowledge): indicates rd_en was asserted during previous clock cycle and data was succesfully read from fifo and placed on dout */
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  output         underflow;   /* underflow (read error): indicates rd_en was asserted during previous clock cycle but no data was read from fifo because fifo was empty */
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  output         prog_empty;  /* indicates the fifo has prog_thresh entries, or less. threshold for asserting prog_empty is prog_thresh */
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  /* write port */
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  input          wr_clk;      /* write clock. positive edge active */
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  input  [dta_width-1:0]din;  /* data input */
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  input          wr_en;       /* write enable */
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  output         full;        /* asserted if fifo is full; no additional writes can be performed */
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  output         overflow;    /* overflow (write error): indicates wr_en was asserted during previous clock cycle but no data was written to fifo because fifo was full */
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  output         wr_ack;      /* write acknowledge: indicates wr_en was asserted during previous clock cycle and data was succesfully written to fifo */
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  output         prog_full;   /* indicates the fifo has prog_thresh free entries, or less, left. threshold for asserting prog_full is 2^addr_width - prog_thresh  */
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  /* Writing when the fifo is full, or reading while the fifo is empty, does not destroy the contents of the fifo. */
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  xilinx_fifo #(
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    .ALMOST_FULL_OFFSET(prog_thresh),
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    .ALMOST_EMPTY_OFFSET(prog_thresh),
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    .DATA_WIDTH(dta_width),
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    .ADDR_WIDTH(addr_width),
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    .DO_REG(1),
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    .EN_SYN("FALSE")
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    )
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  xilinx_fifo_dc (
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    .ALMOSTEMPTY(prog_empty),
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    .ALMOSTFULL(prog_full),
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    .DO(dout),
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    .EMPTY(empty),
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    .FULL(full),
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    .RDERR(underflow),
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    .VALID(valid),
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    .WRERR(overflow),
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    .WR_ACK(wr_ack),
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    .DI(din),
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    .RDCLK(rd_clk),
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    .RDEN(rd_en),
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    .RST(rst),
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    .WRCLK(wr_clk),
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    .WREN(wr_en)
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     );
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`ifdef CHECK_GENERATE
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    initial
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      $display("%m: fifo parameters: dta_width=%0d addr_width=%0d prog_thresh=%0d", dta_width, addr_width, prog_thresh);
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`endif
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endmodule
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/* not truncated */

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