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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Generic Dual-Port Synchronous RAM                           ////
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////                                                              ////
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////  This file is part of memory library available from          ////
6
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
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////                                                              ////
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////  Description                                                 ////
9
////  This block is a wrapper with common dual-port               ////
10
////  synchronous memory interface for different                  ////
11
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
12
////  interface it also provides behavioral model of generic      ////
13
////  dual-port synchronous RAM.                                  ////
14
////  It also contains a fully synthesizeable model for FPGAs.    ////
15
////  It should be used in all OPENCORES designs that want to be  ////
16
////  portable accross different target technologies and          ////
17
////  independent of target memory.                               ////
18
////                                                              ////
19
////  Supported ASIC RAMs are:                                    ////
20
////  - Artisan Dual-Port Sync RAM                                ////
21
////  - Avant! Two-Port Sync RAM (*)                              ////
22
////  - Virage 2-port Sync RAM                                    ////
23
////                                                              ////
24
////  Supported FPGA RAMs are:                                    ////
25
////  - Generic FPGA (VENDOR_FPGA)                                ////
26
////    Tested RAMs: Altera, Xilinx                               ////
27
////    Synthesis tools: LeonardoSpectrum, Synplicity             ////
28
////  - Xilinx (VENDOR_XILINX)                                    ////
29
////  - Altera (VENDOR_ALTERA)                                    ////
30
////                                                              ////
31
////  To Do:                                                      ////
32
////   - fix Avant!                                               ////
33
////   - add additional RAMs (VS etc)                             ////
34
////                                                              ////
35
////  Author(s):                                                  ////
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////      - Richard Herveille, richard@asics.ws                   ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
49
//// and/or modify it under the terms of the GNU Lesser General   ////
50
//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
61
//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
65
//
66
// CVS Revision History
67
//
68
// $Log: generic_dpram.v,v $
69
// Revision 1.4  2002/09/28 08:18:52  rherveille
70
// Changed synthesizeable FPGA memory implementation.
71
// Fixed some issues with Xilinx BlockRAM
72
//
73
// Revision 1.3  2001/11/09 00:34:18  samg
74
// minor changes: unified with all common rams
75
//
76
// Revision 1.2  2001/11/08 19:11:31  samg
77
// added valid checks to behvioral model
78
//
79
// Revision 1.1.1.1  2001/09/14 09:57:10  rherveille
80
// Major cleanup.
81
// Files are now compliant to Altera & Xilinx memories.
82
// Memories are now compatible, i.e. drop-in replacements.
83
// Added synthesizeable generic FPGA description.
84
// Created "generic_memories" cvs entry.
85
//
86
// Revision 1.1.1.2  2001/08/21 13:09:27  damjan
87
// *** empty log message ***
88
//
89
// Revision 1.1  2001/08/20 18:23:20  damjan
90
// Initial revision
91
//
92
// Revision 1.1  2001/08/09 13:39:33  lampret
93
// Major clean-up.
94
//
95
// Revision 1.2  2001/07/30 05:38:02  lampret
96
// Adding empty directories required by HDL coding guidelines
97
//
98
//
99
 
100
`include "timescale.v"
101
 
102
//`define VENDOR_FPGA
103
//`define VENDOR_XILINX
104
//`define VENDOR_ALTERA
105
 
106
module generic_dpram(
107
        // Generic synchronous dual-port RAM interface
108
        rclk, rrst, rce, oe, raddr, do,
109
        wclk, wrst, wce, we, waddr, di
110
);
111
 
112
        //
113
        // Default address and data buses width
114
        //
115
        parameter aw = 5;  // number of bits in address-bus
116
        parameter dw = 16; // number of bits in data-bus
117
 
118
        //
119
        // Generic synchronous double-port RAM interface
120
        //
121
        // read port
122
        input           rclk;  // read clock, rising edge trigger
123
        input           rrst;  // read port reset, active high
124
        input           rce;   // read port chip enable, active high
125
        input           oe;        // output enable, active high
126
        input  [aw-1:0] raddr; // read address
127
        output [dw-1:0] do;    // data output
128
 
129
        // write port
130
        input          wclk;  // write clock, rising edge trigger
131
        input          wrst;  // write port reset, active high
132
        input          wce;   // write port chip enable, active high
133
        input          we;    // write enable, active high
134
        input [aw-1:0] waddr; // write address
135
        input [dw-1:0] di;    // data input
136
 
137
        //
138
        // Module body
139
        //
140
 
141
`ifdef VENDOR_FPGA
142
        //
143
        // Instantiation synthesizeable FPGA memory
144
        //
145
        // This code has been tested using LeonardoSpectrum and Synplicity.
146
        // The code correctly instantiates Altera EABs and Xilinx BlockRAMs.
147
        //
148
        reg [dw-1:0] mem [(1<<aw) -1:0]; // instantiate memory
149
        reg [aw-1:0] ra;                 // register read address
150
 
151
        // read operation
152
        always @(posedge rclk)
153
          if (rce)
154
            ra <= #1 raddr;
155
 
156
        assign do = mem[ra];
157
 
158
        // write operation
159
        always@(posedge wclk)
160
                if (we && wce)
161
                        mem[waddr] <= #1 di;
162
 
163
`else
164
 
165
`ifdef VENDOR_XILINX
166
        //
167
        // Instantiation of FPGA memory:
168
        //
169
        // Virtex/Spartan2 BlockRAMs
170
        //
171
        xilinx_ram_dp xilinx_ram(
172
                // read port
173
                .CLKA(rclk),
174
                .RSTA(rrst),
175
                .ENA(rce),
176
                .ADDRA(raddr),
177
                .DIA( {dw{1'b0}} ),
178
                .WEA(1'b0),
179
                .DOA(do),
180
 
181
                // write port
182
                .CLKB(wclk),
183
                .RSTB(wrst),
184
                .ENB(wce),
185
                .ADDRB(waddr),
186
                .DIB(di),
187
                .WEB(we),
188
                .DOB()
189
        );
190
 
191
        defparam
192
                xilinx_ram.dwidth = dw,
193
                xilinx_ram.awidth = aw;
194
 
195
`else
196
 
197
`ifdef VENDOR_ALTERA
198
        //
199
        // Instantiation of FPGA memory:
200
        //
201
        // Altera FLEX/APEX EABs
202
        //
203
        altera_ram_dp altera_ram(
204
                // read port
205
                .rdclock(rclk),
206
                .rdclocken(rce),
207
                .rdaddress(raddr),
208
                .q(do),
209
 
210
                // write port
211
                .wrclock(wclk),
212
                .wrclocken(wce),
213
                .wren(we),
214
                .wraddress(waddr),
215
                .data(di)
216
        );
217
 
218
        defparam
219
                altera_ram.dwidth = dw,
220
                altera_ram.awidth = aw;
221
 
222
`else
223
 
224
`ifdef VENDOR_ARTISAN
225
 
226
        //
227
        // Instantiation of ASIC memory:
228
        //
229
        // Artisan Synchronous Double-Port RAM (ra2sh)
230
        //
231
        art_hsdp #(dw, 1<<aw, aw) artisan_sdp(
232
                // read port
233
                .qa(do),
234
                .clka(rclk),
235
                .cena(~rce),
236
                .wena(1'b1),
237
                .aa(raddr),
238
                .da( {dw{1'b0}} ),
239
                .oena(~oe),
240
 
241
                // write port
242
                .qb(),
243
                .clkb(wclk),
244
                .cenb(~wce),
245
                .wenb(~we),
246
                .ab(waddr),
247
                .db(di),
248
                .oenb(1'b1)
249
        );
250
 
251
`else
252
 
253
`ifdef VENDOR_AVANT
254
 
255
        //
256
        // Instantiation of ASIC memory:
257
        //
258
        // Avant! Asynchronous Two-Port RAM
259
        //
260
        avant_atp avant_atp(
261
                .web(~we),
262
                .reb(),
263
                .oeb(~oe),
264
                .rcsb(),
265
                .wcsb(),
266
                .ra(raddr),
267
                .wa(waddr),
268
                .di(di),
269
                .do(do)
270
        );
271
 
272
`else
273
 
274
`ifdef VENDOR_VIRAGE
275
 
276
        //
277
        // Instantiation of ASIC memory:
278
        //
279
        // Virage Synchronous 2-port R/W RAM
280
        //
281
        virage_stp virage_stp(
282
                // read port
283
                .CLKA(rclk),
284
                .MEA(rce_a),
285
                .ADRA(raddr),
286
                .DA( {dw{1'b0}} ),
287
                .WEA(1'b0),
288
                .OEA(oe),
289
                .QA(do),
290
 
291
                // write port
292
                .CLKB(wclk),
293
                .MEB(wce),
294
                .ADRB(waddr),
295
                .DB(di),
296
                .WEB(we),
297
                .OEB(1'b1),
298
                .QB()
299
        );
300
 
301
`else
302
 
303
        //
304
        // Generic dual-port synchronous RAM model
305
        //
306
 
307
        //
308
        // Generic RAM's registers and wires
309
        //
310
        reg     [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
311
        reg     [dw-1:0] do_reg;            // RAM data output register
312
 
313
        //
314
        // Data output drivers
315
        //
316
        assign do = (oe & rce) ? do_reg : {dw{1'bz}};
317
 
318
        // read operation
319
        always @(posedge rclk)
320
                if (rce)
321
                        do_reg <= #1 (we && (waddr==raddr)) ? {dw{1'b x}} : mem[raddr];
322
 
323
        // write operation
324
        always @(posedge wclk)
325
                if (wce && we)
326
                        mem[waddr] <= #1 di;
327
 
328
 
329
        // Task prints range of memory
330
        // *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
331
        task print_ram;
332
        input [aw-1:0] start;
333
        input [aw-1:0] finish;
334
        integer rnum;
335
        begin
336
                for (rnum=start;rnum<=finish;rnum=rnum+1)
337
                        $display("Addr %h = %h",rnum,mem[rnum]);
338
        end
339
        endtask
340
 
341
`endif // !VENDOR_VIRAGE
342
`endif // !VENDOR_AVANT
343
`endif // !VENDOR_ARTISAN
344
`endif // !VENDOR_ALTERA
345
`endif // !VENDOR_XILINX
346
`endif // !VENDOR_FPGA
347
 
348
endmodule
349
 
350
//
351
// Black-box modules
352
//
353
 
354
`ifdef VENDOR_ALTERA
355
        module altera_ram_dp(
356
                data,
357
                wraddress,
358
                rdaddress,
359
                wren,
360
                wrclock,
361
                wrclocken,
362
                rdclock,
363
                rdclocken,
364
                q) /* synthesis black_box */;
365
 
366
                parameter awidth = 7;
367
                parameter dwidth = 8;
368
 
369
                input [dwidth -1:0] data;
370
                input [awidth -1:0] wraddress;
371
                input [awidth -1:0] rdaddress;
372
                input               wren;
373
                input               wrclock;
374
                input               wrclocken;
375
                input               rdclock;
376
                input               rdclocken;
377
                output [dwidth -1:0] q;
378
 
379
                // synopsis translate_off
380
                // exemplar translate_off
381
 
382
                syn_dpram_rowr #(
383
                        "UNUSED",
384
                        dwidth,
385
                        awidth,
386
                        1 << awidth
387
                )
388
                altera_dpram_model (
389
                        // read port
390
                        .RdClock(rdclock),
391
                        .RdClken(rdclocken),
392
                        .RdAddress(rdaddress),
393
                        .RdEn(1'b1),
394
                        .Q(q),
395
 
396
                        // write port
397
                        .WrClock(wrclock),
398
                        .WrClken(wrclocken),
399
                        .WrAddress(wraddress),
400
                        .WrEn(wren),
401
                        .Data(data)
402
                );
403
 
404
                // exemplar translate_on
405
                // synopsis translate_on
406
 
407
        endmodule
408
`endif // VENDOR_ALTERA
409
 
410
`ifdef VENDOR_XILINX
411
        module xilinx_ram_dp (
412
                ADDRA,
413
                CLKA,
414
                ADDRB,
415
                CLKB,
416
                DIA,
417
                WEA,
418
                DIB,
419
                WEB,
420
                ENA,
421
                ENB,
422
                RSTA,
423
                RSTB,
424
                DOA,
425
                DOB) /* synthesis black_box */ ;
426
 
427
        parameter awidth = 7;
428
        parameter dwidth = 8;
429
 
430
        // port_a
431
        input               CLKA;
432
        input               RSTA;
433
        input               ENA;
434
        input [awidth-1:0]  ADDRA;
435
        input [dwidth-1:0]  DIA;
436
        input               WEA;
437
        output [dwidth-1:0] DOA;
438
 
439
        // port_b
440
        input               CLKB;
441
        input               RSTB;
442
        input               ENB;
443
        input [awidth-1:0]  ADDRB;
444
        input [dwidth-1:0]  DIB;
445
        input               WEB;
446
        output [dwidth-1:0] DOB;
447
 
448
        // insert simulation model
449
 
450
 
451
        // synopsys translate_off
452
        // exemplar translate_off
453
 
454
        C_MEM_DP_BLOCK_V1_0 #(
455
                awidth,
456
                awidth,
457
                1,
458
                1,
459
                "0",
460
                1 << awidth,
461
                1 << awidth,
462
                1,
463
                1,
464
                1,
465
                1,
466
                1,
467
                1,
468
                1,
469
                1,
470
                1,
471
                1,
472
                1,
473
                1,
474
                1,
475
                "",
476
                16,
477
                0,
478
                0,
479
                1,
480
                1,
481
                1,
482
                1,
483
                dwidth,
484
                dwidth)
485
        xilinx_dpram_model (
486
                .ADDRA(ADDRA),
487
                .CLKA(CLKA),
488
                .ADDRB(ADDRB),
489
                .CLKB(CLKB),
490
                .DIA(DIA),
491
                .WEA(WEA),
492
                .DIB(DIB),
493
                .WEB(WEB),
494
                .ENA(ENA),
495
                .ENB(ENB),
496
                .RSTA(RSTA),
497
                .RSTB(RSTB),
498
                .DOA(DOA),
499
                .DOB(DOB));
500
 
501
                // exemplar translate_on
502
                // synopsys translate_on
503
 
504
        endmodule
505
`endif // VENDOR_XILINX

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