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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Dual-Port Synchronous RAM                           ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common dual-port               ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  dual-port synchronous RAM.                                  ////
////  It also contains a fully synthesizeable model for FPGAs.    ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Dual-Port Sync RAM                                ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage 2-port Sync RAM                                    ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Generic FPGA (VENDOR_FPGA)                                ////
////    Tested RAMs: Altera, Xilinx                               ////
////    Synthesis tools: LeonardoSpectrum, Synplicity             ////
////  - Xilinx (VENDOR_XILINX)                                    ////
////  - Altera (VENDOR_ALTERA)                                    ////
////                                                              ////
////  To Do:                                                      ////
////   - fix Avant!                                               ////
////   - add additional RAMs (VS etc)                             ////
////                                                              ////
////  Author(s):                                                  ////
////      - Richard Herveille, richard@asics.ws                   ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: generic_dpram.v,v $
// Revision 1.4  2002/09/28 08:18:52  rherveille
// Changed synthesizeable FPGA memory implementation.
// Fixed some issues with Xilinx BlockRAM
//
// Revision 1.3  2001/11/09 00:34:18  samg
// minor changes: unified with all common rams
//
// Revision 1.2  2001/11/08 19:11:31  samg
// added valid checks to behvioral model
//
// Revision 1.1.1.1  2001/09/14 09:57:10  rherveille
// Major cleanup.
// Files are now compliant to Altera & Xilinx memories.
// Memories are now compatible, i.e. drop-in replacements.
// Added synthesizeable generic FPGA description.
// Created "generic_memories" cvs entry.
//
// Revision 1.1.1.2  2001/08/21 13:09:27  damjan
// *** empty log message ***
//
// Revision 1.1  2001/08/20 18:23:20  damjan
// Initial revision
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
`include "timescale.v"
 
//`define VENDOR_FPGA
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
 
module generic_dpram(
        // Generic synchronous dual-port RAM interface
        rclk, rrst, rce, oe, raddr, do,
        wclk, wrst, wce, we, waddr, di
);
 
        //
        // Default address and data buses width
        //
        parameter aw = 5;  // number of bits in address-bus
        parameter dw = 16; // number of bits in data-bus
 
        //
        // Generic synchronous double-port RAM interface
        //
        // read port
        input           rclk;  // read clock, rising edge trigger
        input           rrst;  // read port reset, active high
        input           rce;   // read port chip enable, active high
        input           oe;        // output enable, active high
        input  [aw-1:0] raddr; // read address
        output [dw-1:0] do;    // data output
 
        // write port
        input          wclk;  // write clock, rising edge trigger
        input          wrst;  // write port reset, active high
        input          wce;   // write port chip enable, active high
        input          we;    // write enable, active high
        input [aw-1:0] waddr; // write address
        input [dw-1:0] di;    // data input
 
        //
        // Module body
        //
 
`ifdef VENDOR_FPGA
        //
        // Instantiation synthesizeable FPGA memory
        //
        // This code has been tested using LeonardoSpectrum and Synplicity.
        // The code correctly instantiates Altera EABs and Xilinx BlockRAMs.
        //
        reg [dw-1:0] mem [(1<<aw) -1:0]; // instantiate memory
        reg [aw-1:0] ra;                 // register read address
 
        // read operation
        always @(posedge rclk)
          if (rce)
            ra <= #1 raddr;
 
        assign do = mem[ra];
 
        // write operation
        always@(posedge wclk)
                if (we && wce)
                        mem[waddr] <= #1 di;
 
`else
 
`ifdef VENDOR_XILINX
        //
        // Instantiation of FPGA memory:
        //
        // Virtex/Spartan2 BlockRAMs
        //
        xilinx_ram_dp xilinx_ram(
                // read port
                .CLKA(rclk),
                .RSTA(rrst),
                .ENA(rce),
                .ADDRA(raddr),
                .DIA( {dw{1'b0}} ),
                .WEA(1'b0),
                .DOA(do),
 
                // write port
                .CLKB(wclk),
                .RSTB(wrst),
                .ENB(wce),
                .ADDRB(waddr),
                .DIB(di),
                .WEB(we),
                .DOB()
        );
 
        defparam
                xilinx_ram.dwidth = dw,
                xilinx_ram.awidth = aw;
 
`else
 
`ifdef VENDOR_ALTERA
        //
        // Instantiation of FPGA memory:
        //
        // Altera FLEX/APEX EABs
        //
        altera_ram_dp altera_ram(
                // read port
                .rdclock(rclk),
                .rdclocken(rce),
                .rdaddress(raddr),
                .q(do),
 
                // write port
                .wrclock(wclk),
                .wrclocken(wce),
                .wren(we),
                .wraddress(waddr),
                .data(di)
        );
 
        defparam
                altera_ram.dwidth = dw,
                altera_ram.awidth = aw;
 
`else
 
`ifdef VENDOR_ARTISAN
 
        //
        // Instantiation of ASIC memory:
        //
        // Artisan Synchronous Double-Port RAM (ra2sh)
        //
        art_hsdp #(dw, 1<<aw, aw) artisan_sdp(
                // read port
                .qa(do),
                .clka(rclk),
                .cena(~rce),
                .wena(1'b1),
                .aa(raddr),
                .da( {dw{1'b0}} ),
                .oena(~oe),
 
                // write port
                .qb(),
                .clkb(wclk),
                .cenb(~wce),
                .wenb(~we),
                .ab(waddr),
                .db(di),
                .oenb(1'b1)
        );
 
`else
 
`ifdef VENDOR_AVANT
 
        //
        // Instantiation of ASIC memory:
        //
        // Avant! Asynchronous Two-Port RAM
        //
        avant_atp avant_atp(
                .web(~we),
                .reb(),
                .oeb(~oe),
                .rcsb(),
                .wcsb(),
                .ra(raddr),
                .wa(waddr),
                .di(di),
                .do(do)
        );
 
`else
 
`ifdef VENDOR_VIRAGE
 
        //
        // Instantiation of ASIC memory:
        //
        // Virage Synchronous 2-port R/W RAM
        //
        virage_stp virage_stp(
                // read port
                .CLKA(rclk),
                .MEA(rce_a),
                .ADRA(raddr),
                .DA( {dw{1'b0}} ),
                .WEA(1'b0),
                .OEA(oe),
                .QA(do),
 
                // write port
                .CLKB(wclk),
                .MEB(wce),
                .ADRB(waddr),
                .DB(di),
                .WEB(we),
                .OEB(1'b1),
                .QB()
        );
 
`else
 
        //
        // Generic dual-port synchronous RAM model
        //
 
        //
        // Generic RAM's registers and wires
        //
        reg     [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
        reg     [dw-1:0] do_reg;            // RAM data output register
 
        //
        // Data output drivers
        //
        assign do = (oe & rce) ? do_reg : {dw{1'bz}};
 
        // read operation
        always @(posedge rclk)
                if (rce)
                        do_reg <= #1 (we && (waddr==raddr)) ? {dw{1'b x}} : mem[raddr];
 
        // write operation
        always @(posedge wclk)
                if (wce && we)
                        mem[waddr] <= #1 di;
 
 
        // Task prints range of memory
        // *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
        task print_ram;
        input [aw-1:0] start;
        input [aw-1:0] finish;
        integer rnum;
        begin
                for (rnum=start;rnum<=finish;rnum=rnum+1)
                        $display("Addr %h = %h",rnum,mem[rnum]);
        end
        endtask
 
`endif // !VENDOR_VIRAGE
`endif // !VENDOR_AVANT
`endif // !VENDOR_ARTISAN
`endif // !VENDOR_ALTERA
`endif // !VENDOR_XILINX
`endif // !VENDOR_FPGA
 
endmodule
 
//
// Black-box modules
//
 
`ifdef VENDOR_ALTERA
        module altera_ram_dp(
                data,
                wraddress,
                rdaddress,
                wren,
                wrclock,
                wrclocken,
                rdclock,
                rdclocken,
                q) /* synthesis black_box */;
 
                parameter awidth = 7;
                parameter dwidth = 8;
 
                input [dwidth -1:0] data;
                input [awidth -1:0] wraddress;
                input [awidth -1:0] rdaddress;
                input               wren;
                input               wrclock;
                input               wrclocken;
                input               rdclock;
                input               rdclocken;
                output [dwidth -1:0] q;
 
                // synopsis translate_off
                // exemplar translate_off
 
                syn_dpram_rowr #(
                        "UNUSED",
                        dwidth,
                        awidth,
                        1 << awidth
                )
                altera_dpram_model (
                        // read port
                        .RdClock(rdclock),
                        .RdClken(rdclocken),
                        .RdAddress(rdaddress),
                        .RdEn(1'b1),
                        .Q(q),
 
                        // write port
                        .WrClock(wrclock),
                        .WrClken(wrclocken),
                        .WrAddress(wraddress),
                        .WrEn(wren),
                        .Data(data)
                );
 
                // exemplar translate_on
                // synopsis translate_on
 
        endmodule
`endif // VENDOR_ALTERA
 
`ifdef VENDOR_XILINX
        module xilinx_ram_dp (
                ADDRA,
                CLKA,
                ADDRB,
                CLKB,
                DIA,
                WEA,
                DIB,
                WEB,
                ENA,
                ENB,
                RSTA,
                RSTB,
                DOA,
                DOB) /* synthesis black_box */ ;
 
        parameter awidth = 7;
        parameter dwidth = 8;
 
        // port_a
        input               CLKA;
        input               RSTA;
        input               ENA;
        input [awidth-1:0]  ADDRA;
        input [dwidth-1:0]  DIA;
        input               WEA;
        output [dwidth-1:0] DOA;
 
        // port_b
        input               CLKB;
        input               RSTB;
        input               ENB;
        input [awidth-1:0]  ADDRB;
        input [dwidth-1:0]  DIB;
        input               WEB;
        output [dwidth-1:0] DOB;
 
        // insert simulation model
 
 
        // synopsys translate_off
        // exemplar translate_off
 
        C_MEM_DP_BLOCK_V1_0 #(
                awidth,
                awidth,
                1,
                1,
                "0",
                1 << awidth,
                1 << awidth,
                1,
                1,
                1,
                1,
                1,
                1,
                1,
                1,
                1,
                1,
                1,
                1,
                1,
                "",
                16,
                0,
                0,
                1,
                1,
                1,
                1,
                dwidth,
                dwidth)
        xilinx_dpram_model (
                .ADDRA(ADDRA),
                .CLKA(CLKA),
                .ADDRB(ADDRB),
                .CLKB(CLKB),
                .DIA(DIA),
                .WEA(WEA),
                .DIB(DIB),
                .WEB(WEB),
                .ENA(ENA),
                .ENB(ENB),
                .RSTA(RSTA),
                .RSTB(RSTB),
                .DOA(DOA),
                .DOB(DOB));
 
                // exemplar translate_on
                // synopsys translate_on
 
        endmodule
`endif // VENDOR_XILINX

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Subversion Repositories mpeg2fpga

[/] [mpeg2fpga/] [trunk/] [tools/] [ieee1180/] [ieee1180/] [generic_dpram.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	kdv	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Dual-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common dual-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// dual-port synchronous RAM. ////`
14			`//// It also contains a fully synthesizeable model for FPGAs. ////`
15			`//// It should be used in all OPENCORES designs that want to be ////`
16			`//// portable accross different target technologies and ////`
17			`//// independent of target memory. ////`
18			`//// ////`
19			`//// Supported ASIC RAMs are: ////`
20			`//// - Artisan Dual-Port Sync RAM ////`
21			`//// - Avant! Two-Port Sync RAM (*) ////`
22			`//// - Virage 2-port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Generic FPGA (VENDOR_FPGA) ////`
26			`//// Tested RAMs: Altera, Xilinx ////`
27			`//// Synthesis tools: LeonardoSpectrum, Synplicity ////`
28			`//// - Xilinx (VENDOR_XILINX) ////`
29			`//// - Altera (VENDOR_ALTERA) ////`
30			`//// ////`
31			`//// To Do: ////`
32			`//// - fix Avant! ////`
33			`//// - add additional RAMs (VS etc) ////`
34			`//// ////`
35			`//// Author(s): ////`
36			`//// - Richard Herveille, richard@asics.ws ////`
37			`//// - Damjan Lampret, lampret@opencores.org ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//// ////`
41			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
42			`//// ////`
43			`//// This source file may be used and distributed without ////`
44			`//// restriction provided that this copyright statement is not ////`
45			`//// removed from the file and that any derivative work contains ////`
46			`//// the original copyright notice and the associated disclaimer. ////`
47			`//// ////`
48			`//// This source file is free software; you can redistribute it ////`
49			`//// and/or modify it under the terms of the GNU Lesser General ////`
50			`//// Public License as published by the Free Software Foundation; ////`
51			`//// either version 2.1 of the License, or (at your option) any ////`
52			`//// later version. ////`
53			`//// ////`
54			`//// This source is distributed in the hope that it will be ////`
55			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
56			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
57			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
58			`//// details. ////`
59			`//// ////`
60			`//// You should have received a copy of the GNU Lesser General ////`
61			`//// Public License along with this source; if not, download it ////`
62			`//// from http://www.opencores.org/lgpl.shtml ////`
63			`//// ////`
64			`//////////////////////////////////////////////////////////////////////`
65			`//`
66			`// CVS Revision History`
67			`//`
68			`// $Log: generic_dpram.v,v $`
69			`// Revision 1.4 2002/09/28 08:18:52 rherveille`
70			`// Changed synthesizeable FPGA memory implementation.`
71			`// Fixed some issues with Xilinx BlockRAM`
72			`//`
73			`// Revision 1.3 2001/11/09 00:34:18 samg`
74			`// minor changes: unified with all common rams`
75			`//`
76			`// Revision 1.2 2001/11/08 19:11:31 samg`
77			`// added valid checks to behvioral model`
78			`//`
79			`// Revision 1.1.1.1 2001/09/14 09:57:10 rherveille`
80			`// Major cleanup.`
81			`// Files are now compliant to Altera & Xilinx memories.`
82			`// Memories are now compatible, i.e. drop-in replacements.`
83			`// Added synthesizeable generic FPGA description.`
84			`// Created "generic_memories" cvs entry.`
85			`//`
86			`// Revision 1.1.1.2 2001/08/21 13:09:27 damjan`
87			`// * empty log message *`
88			`//`
89			`// Revision 1.1 2001/08/20 18:23:20 damjan`
90			`// Initial revision`
91			`//`
92			`// Revision 1.1 2001/08/09 13:39:33 lampret`
93			`// Major clean-up.`
94			`//`
95			`// Revision 1.2 2001/07/30 05:38:02 lampret`
96			`// Adding empty directories required by HDL coding guidelines`
97			`//`
98			`//`
99
100			`include "timescale.v"
101
102			//`define VENDOR_FPGA
103			//`define VENDOR_XILINX
104			//`define VENDOR_ALTERA
105
106			`module generic_dpram(`
107			`// Generic synchronous dual-port RAM interface`
108			`rclk, rrst, rce, oe, raddr, do,`
109			`wclk, wrst, wce, we, waddr, di`
110			`);`
111
112			`//`
113			`// Default address and data buses width`
114			`//`
115			`parameter aw = 5; // number of bits in address-bus`
116			`parameter dw = 16; // number of bits in data-bus`
117
118			`//`
119			`// Generic synchronous double-port RAM interface`
120			`//`
121			`// read port`
122			`input rclk; // read clock, rising edge trigger`
123			`input rrst; // read port reset, active high`
124			`input rce; // read port chip enable, active high`
125			`input oe; // output enable, active high`
126			`input [aw-1:0] raddr; // read address`
127			`output [dw-1:0] do; // data output`
128
129			`// write port`
130			`input wclk; // write clock, rising edge trigger`
131			`input wrst; // write port reset, active high`
132			`input wce; // write port chip enable, active high`
133			`input we; // write enable, active high`
134			`input [aw-1:0] waddr; // write address`
135			`input [dw-1:0] di; // data input`
136
137			`//`
138			`// Module body`
139			`//`
140
141			`ifdef VENDOR_FPGA
142			`//`
143			`// Instantiation synthesizeable FPGA memory`
144			`//`
145			`// This code has been tested using LeonardoSpectrum and Synplicity.`
146			`// The code correctly instantiates Altera EABs and Xilinx BlockRAMs.`
147			`//`
148			`reg [dw-1:0] mem [(1<<aw) -1:0]; // instantiate memory`
149			`reg [aw-1:0] ra; // register read address`
150
151			`// read operation`
152			`always @(posedge rclk)`
153			`if (rce)`
154			`ra <= #1 raddr;`
155
156			`assign do = mem[ra];`
157
158			`// write operation`
159			`always@(posedge wclk)`
160			`if (we && wce)`
161			`mem[waddr] <= #1 di;`
162
163			`else
164
165			`ifdef VENDOR_XILINX
166			`//`
167			`// Instantiation of FPGA memory:`
168			`//`
169			`// Virtex/Spartan2 BlockRAMs`
170			`//`
171			`xilinx_ram_dp xilinx_ram(`
172			`// read port`
173			`.CLKA(rclk),`
174			`.RSTA(rrst),`
175			`.ENA(rce),`
176			`.ADDRA(raddr),`
177			`.DIA( {dw{1'b0}} ),`
178			`.WEA(1'b0),`
179			`.DOA(do),`
180
181			`// write port`
182			`.CLKB(wclk),`
183			`.RSTB(wrst),`
184			`.ENB(wce),`
185			`.ADDRB(waddr),`
186			`.DIB(di),`
187			`.WEB(we),`
188			`.DOB()`
189			`);`
190
191			`defparam`
192			`xilinx_ram.dwidth = dw,`
193			`xilinx_ram.awidth = aw;`
194
195			`else
196
197			`ifdef VENDOR_ALTERA
198			`//`
199			`// Instantiation of FPGA memory:`
200			`//`
201			`// Altera FLEX/APEX EABs`
202			`//`
203			`altera_ram_dp altera_ram(`
204			`// read port`
205			`.rdclock(rclk),`
206			`.rdclocken(rce),`
207			`.rdaddress(raddr),`
208			`.q(do),`
209
210			`// write port`
211			`.wrclock(wclk),`
212			`.wrclocken(wce),`
213			`.wren(we),`
214			`.wraddress(waddr),`
215			`.data(di)`
216			`);`
217
218			`defparam`
219			`altera_ram.dwidth = dw,`
220			`altera_ram.awidth = aw;`
221
222			`else
223
224			`ifdef VENDOR_ARTISAN
225
226			`//`
227			`// Instantiation of ASIC memory:`
228			`//`
229			`// Artisan Synchronous Double-Port RAM (ra2sh)`
230			`//`
231			`art_hsdp #(dw, 1<<aw, aw) artisan_sdp(`
232			`// read port`
233			`.qa(do),`
234			`.clka(rclk),`
235			`.cena(~rce),`
236			`.wena(1'b1),`
237			`.aa(raddr),`
238			`.da( {dw{1'b0}} ),`
239			`.oena(~oe),`
240
241			`// write port`
242			`.qb(),`
243			`.clkb(wclk),`
244			`.cenb(~wce),`
245			`.wenb(~we),`
246			`.ab(waddr),`
247			`.db(di),`
248			`.oenb(1'b1)`
249			`);`
250
251			`else
252
253			`ifdef VENDOR_AVANT
254
255			`//`
256			`// Instantiation of ASIC memory:`
257			`//`
258			`// Avant! Asynchronous Two-Port RAM`
259			`//`
260			`avant_atp avant_atp(`
261			`.web(~we),`
262			`.reb(),`
263			`.oeb(~oe),`
264			`.rcsb(),`
265			`.wcsb(),`
266			`.ra(raddr),`
267			`.wa(waddr),`
268			`.di(di),`
269			`.do(do)`
270			`);`
271
272			`else
273
274			`ifdef VENDOR_VIRAGE
275
276			`//`
277			`// Instantiation of ASIC memory:`
278			`//`
279			`// Virage Synchronous 2-port R/W RAM`
280			`//`
281			`virage_stp virage_stp(`
282			`// read port`
283			`.CLKA(rclk),`
284			`.MEA(rce_a),`
285			`.ADRA(raddr),`
286			`.DA( {dw{1'b0}} ),`
287			`.WEA(1'b0),`
288			`.OEA(oe),`
289			`.QA(do),`
290
291			`// write port`
292			`.CLKB(wclk),`
293			`.MEB(wce),`
294			`.ADRB(waddr),`
295			`.DB(di),`
296			`.WEB(we),`
297			`.OEB(1'b1),`
298			`.QB()`
299			`);`
300
301			`else
302
303			`//`
304			`// Generic dual-port synchronous RAM model`
305			`//`
306
307			`//`
308			`// Generic RAM's registers and wires`
309			`//`
310			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
311			`reg [dw-1:0] do_reg; // RAM data output register`
312
313			`//`
314			`// Data output drivers`
315			`//`
316			`assign do = (oe & rce) ? do_reg : {dw{1'bz}};`
317
318			`// read operation`
319			`always @(posedge rclk)`
320			`if (rce)`
321			`do_reg <= #1 (we && (waddr==raddr)) ? {dw{1'b x}} : mem[raddr];`
322
323			`// write operation`
324			`always @(posedge wclk)`
325			`if (wce && we)`
326			`mem[waddr] <= #1 di;`
327
328
329			`// Task prints range of memory`
330			`// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.`
331			`task print_ram;`
332			`input [aw-1:0] start;`
333			`input [aw-1:0] finish;`
334			`integer rnum;`
335			`begin`
336			`for (rnum=start;rnum<=finish;rnum=rnum+1)`
337			`$display("Addr %h = %h",rnum,mem[rnum]);`
338			`end`
339			`endtask`
340
341			`endif // !VENDOR_VIRAGE
342			`endif // !VENDOR_AVANT
343			`endif // !VENDOR_ARTISAN
344			`endif // !VENDOR_ALTERA
345			`endif // !VENDOR_XILINX
346			`endif // !VENDOR_FPGA
347
348			`endmodule`
349
350			`//`
351			`// Black-box modules`
352			`//`
353
354			`ifdef VENDOR_ALTERA
355			`module altera_ram_dp(`
356			`data,`
357			`wraddress,`
358			`rdaddress,`
359			`wren,`
360			`wrclock,`
361			`wrclocken,`
362			`rdclock,`
363			`rdclocken,`
364			`q) /* synthesis black_box */;`
365
366			`parameter awidth = 7;`
367			`parameter dwidth = 8;`
368
369			`input [dwidth -1:0] data;`
370			`input [awidth -1:0] wraddress;`
371			`input [awidth -1:0] rdaddress;`
372			`input wren;`
373			`input wrclock;`
374			`input wrclocken;`
375			`input rdclock;`
376			`input rdclocken;`
377			`output [dwidth -1:0] q;`
378
379			`// synopsis translate_off`
380			`// exemplar translate_off`
381
382			`syn_dpram_rowr #(`
383			`"UNUSED",`
384			`dwidth,`
385			`awidth,`
386			`1 << awidth`
387			`)`
388			`altera_dpram_model (`
389			`// read port`
390			`.RdClock(rdclock),`
391			`.RdClken(rdclocken),`
392			`.RdAddress(rdaddress),`
393			`.RdEn(1'b1),`
394			`.Q(q),`
395
396			`// write port`
397			`.WrClock(wrclock),`
398			`.WrClken(wrclocken),`
399			`.WrAddress(wraddress),`
400			`.WrEn(wren),`
401			`.Data(data)`
402			`);`
403
404			`// exemplar translate_on`
405			`// synopsis translate_on`
406
407			`endmodule`
408			`endif // VENDOR_ALTERA
409
410			`ifdef VENDOR_XILINX
411			`module xilinx_ram_dp (`
412			`ADDRA,`
413			`CLKA,`
414			`ADDRB,`
415			`CLKB,`
416			`DIA,`
417			`WEA,`
418			`DIB,`
419			`WEB,`
420			`ENA,`
421			`ENB,`
422			`RSTA,`
423			`RSTB,`
424			`DOA,`
425			`DOB) /* synthesis black_box */ ;`
426
427			`parameter awidth = 7;`
428			`parameter dwidth = 8;`
429
430			`// port_a`
431			`input CLKA;`
432			`input RSTA;`
433			`input ENA;`
434			`input [awidth-1:0] ADDRA;`
435			`input [dwidth-1:0] DIA;`
436			`input WEA;`
437			`output [dwidth-1:0] DOA;`
438
439			`// port_b`
440			`input CLKB;`
441			`input RSTB;`
442			`input ENB;`
443			`input [awidth-1:0] ADDRB;`
444			`input [dwidth-1:0] DIB;`
445			`input WEB;`
446			`output [dwidth-1:0] DOB;`
447
448			`// insert simulation model`
449
450
451			`// synopsys translate_off`
452			`// exemplar translate_off`
453
454			`C_MEM_DP_BLOCK_V1_0 #(`
455			`awidth,`
456			`awidth,`
457			`1,`
458			`1,`
459			`"0",`
460			`1 << awidth,`
461			`1 << awidth,`
462			`1,`
463			`1,`
464			`1,`
465			`1,`
466			`1,`
467			`1,`
468			`1,`
469			`1,`
470			`1,`
471			`1,`
472			`1,`
473			`1,`
474			`1,`
475			`"",`
476			`16,`
477			`0,`
478			`0,`
479			`1,`
480			`1,`
481			`1,`
482			`1,`
483			`dwidth,`
484			`dwidth)`
485			`xilinx_dpram_model (`
486			`.ADDRA(ADDRA),`
487			`.CLKA(CLKA),`
488			`.ADDRB(ADDRB),`
489			`.CLKB(CLKB),`
490			`.DIA(DIA),`
491			`.WEA(WEA),`
492			`.DIB(DIB),`
493			`.WEB(WEB),`
494			`.ENA(ENA),`
495			`.ENB(ENB),`
496			`.RSTA(RSTA),`
497			`.RSTB(RSTB),`
498			`.DOA(DOA),`
499			`.DOB(DOB));`
500
501			`// exemplar translate_on`
502			`// synopsys translate_on`
503
504			`endmodule`
505			`endif // VENDOR_XILINX