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[/] [mpeg2fpga/] [trunk/] [tools/] [ieee1180/] [ieee1180/] [tst.v] - Blame information for rev 2

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1 2 kdv
`timescale 1ns/1ps
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module tst;
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  reg signed [11:0]i;
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  reg clk;
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  reg rst;
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  wire signed [8:0]dta_out;
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  wire              dta_out_valid;
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  reg signed [11:0]dta_in;
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  reg signed [11:0]dta_in_array[0:63];
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  integer file, count, j;
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  initial clk = 0;
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  initial rst = 0;
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  initial i = 0;
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  initial j = 0;
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  initial
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    begin
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      $readmemh("idct-in", dta_in_array, 0, 63);
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    end
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initial
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  forever clk = #10 ~clk;
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always @(posedge clk)
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 rst <= 1;
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always @(posedge clk)
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 if (~rst)
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   i <= 0;
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 else
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  i <= i+1;
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wire dta_in_valid = (i != 0);
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always @(posedge clk)
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  if ( i <= 63)
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     dta_in <= dta_in_array[i];
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  else
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     dta_in <= 0;
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  idct
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                  idct(.clk(clk), .clk_en(1'b1), .rst(rst),
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                  .iquant_level(dta_in), .iquant_valid(dta_in_valid),
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                  .idct_data(dta_out), .idct_valid(dta_out_valid));
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always @(posedge clk)
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  begin
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    if (dta_out_valid)
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      begin
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        j <= j + 1;
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        #0 $display(dta_out);
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      end
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  end
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always @(posedge clk)
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  if (j == 64)
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    begin
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      $finish();
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    end
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//`define DEBUG_VCD 1
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`ifdef DEBUG_VCD
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  initial
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    begin // generate vcd dump, for instance for use with covered (covered.sourceforge.net) or dinotrace
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      $dumpfile("testbench.vcd");
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      $dumpvars;
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    end
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`endif
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endmodule

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