Subversion Repositories oc_axi_bfm

# TCL File Generated by Component Editor 19.1

# Sat Jun 06 22:05:16 EDT 2020

# DO NOT MODIFY

# 

# oc_axi_lite_bfm "oc_axi_lite_bfm" v1.0

# Jack Frye 2020.06.06.22:05:16

# Bus Functional Model AXI4-Lite for Platform Designer

# 

# 

# request TCL package from ACDS 16.1

# 

package require -exact qsys 16.1

# 

# module oc_axi_lite_bfm

# 

set_module_property DESCRIPTION "Bus Functional Model AXI4-Lite for Platform Designer"

set_module_property NAME oc_axi_lite_bfm

set_module_property VERSION 1.0

set_module_property INTERNAL false

set_module_property OPAQUE_ADDRESS_MAP true

set_module_property GROUP "Open Cores"

set_module_property AUTHOR "Jack Frye"

set_module_property DISPLAY_NAME oc_axi_lite_bfm

set_module_property INSTANTIATE_IN_SYSTEM_MODULE true

set_module_property EDITABLE true

set_module_property REPORT_TO_TALKBACK false

set_module_property ALLOW_GREYBOX_GENERATION false

set_module_property REPORT_HIERARCHY false

# 

# file sets

# 

add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""

set_fileset_property QUARTUS_SYNTH TOP_LEVEL new_component

set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false

set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false

add_fileset_file new_component.v VERILOG PATH new_component.v TOP_LEVEL_FILE

add_fileset SIM_VERILOG SIM_VERILOG "" ""

set_fileset_property SIM_VERILOG TOP_LEVEL new_component

set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false

set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false

add_fileset_file new_component.v VERILOG PATH new_component.v

# 

# parameters

# 

add_parameter IDLE INTEGER 0

set_parameter_property IDLE DEFAULT_VALUE 0

set_parameter_property IDLE DISPLAY_NAME IDLE

set_parameter_property IDLE TYPE INTEGER

set_parameter_property IDLE UNITS None

set_parameter_property IDLE HDL_PARAMETER true

add_parameter READ INTEGER 1

set_parameter_property READ DEFAULT_VALUE 1

set_parameter_property READ DISPLAY_NAME READ

set_parameter_property READ TYPE INTEGER

set_parameter_property READ UNITS None

set_parameter_property READ HDL_PARAMETER true

add_parameter WRITE INTEGER 2

set_parameter_property WRITE DEFAULT_VALUE 2

set_parameter_property WRITE DISPLAY_NAME WRITE

set_parameter_property WRITE TYPE INTEGER

set_parameter_property WRITE UNITS None

set_parameter_property WRITE HDL_PARAMETER true

add_parameter N_AW_W INTEGER 0

set_parameter_property N_AW_W DEFAULT_VALUE 0

set_parameter_property N_AW_W DISPLAY_NAME N_AW_W

set_parameter_property N_AW_W TYPE INTEGER

set_parameter_property N_AW_W UNITS None

set_parameter_property N_AW_W HDL_PARAMETER true

add_parameter AW_NW INTEGER 1

set_parameter_property AW_NW DEFAULT_VALUE 1

set_parameter_property AW_NW DISPLAY_NAME AW_NW

set_parameter_property AW_NW TYPE INTEGER

set_parameter_property AW_NW UNITS None

set_parameter_property AW_NW HDL_PARAMETER true

add_parameter NAW_W INTEGER 2

set_parameter_property NAW_W DEFAULT_VALUE 2

set_parameter_property NAW_W DISPLAY_NAME NAW_W

set_parameter_property NAW_W TYPE INTEGER

set_parameter_property NAW_W UNITS None

set_parameter_property NAW_W HDL_PARAMETER true

add_parameter B_WAIT INTEGER 3

set_parameter_property B_WAIT DEFAULT_VALUE 3

set_parameter_property B_WAIT DISPLAY_NAME B_WAIT

set_parameter_property B_WAIT TYPE INTEGER

set_parameter_property B_WAIT UNITS None

set_parameter_property B_WAIT HDL_PARAMETER true

add_parameter R_AR INTEGER 0

set_parameter_property R_AR DEFAULT_VALUE 0

set_parameter_property R_AR DISPLAY_NAME R_AR

set_parameter_property R_AR TYPE INTEGER

set_parameter_property R_AR UNITS None

set_parameter_property R_AR HDL_PARAMETER true

add_parameter R_R INTEGER 1

set_parameter_property R_R DEFAULT_VALUE 1

set_parameter_property R_R DISPLAY_NAME R_R

set_parameter_property R_R TYPE INTEGER

set_parameter_property R_R UNITS None

set_parameter_property R_R HDL_PARAMETER true

add_parameter R_RSP INTEGER 2

set_parameter_property R_RSP DEFAULT_VALUE 2

set_parameter_property R_RSP DISPLAY_NAME R_RSP

set_parameter_property R_RSP TYPE INTEGER

set_parameter_property R_RSP UNITS None

set_parameter_property R_RSP HDL_PARAMETER true

# 

# display items

# 

# 

# connection point clock

# 

add_interface clock clock end

set_interface_property clock clockRate 0

set_interface_property clock ENABLED true

set_interface_property clock EXPORT_OF ""

set_interface_property clock PORT_NAME_MAP ""

set_interface_property clock CMSIS_SVD_VARIABLES ""

set_interface_property clock SVD_ADDRESS_GROUP ""

add_interface_port clock clock_clk clk Input 1

# 

# connection point axm_m0

# 

add_interface axm_m0 axi4 start

set_interface_property axm_m0 associatedClock clock

set_interface_property axm_m0 associatedReset reset_1

set_interface_property axm_m0 readIssuingCapability 1

set_interface_property axm_m0 writeIssuingCapability 1

set_interface_property axm_m0 combinedIssuingCapability 1

set_interface_property axm_m0 ENABLED true

set_interface_property axm_m0 EXPORT_OF ""

set_interface_property axm_m0 PORT_NAME_MAP ""

set_interface_property axm_m0 CMSIS_SVD_VARIABLES ""

set_interface_property axm_m0 SVD_ADDRESS_GROUP ""

add_interface_port axm_m0 axm_m0_awaddr awaddr Output 32

add_interface_port axm_m0 axm_m0_awprot awprot Output 3

add_interface_port axm_m0 axm_m0_awvalid awvalid Output 1

add_interface_port axm_m0 axm_m0_awready awready Input 1

add_interface_port axm_m0 axm_m0_wdata wdata Output 32

add_interface_port axm_m0 axm_m0_wlast wlast Output 1

add_interface_port axm_m0 axm_m0_wvalid wvalid Output 1

add_interface_port axm_m0 axm_m0_wready wready Input 1

add_interface_port axm_m0 axm_m0_bvalid bvalid Input 1

add_interface_port axm_m0 axm_m0_bready bready Output 1

add_interface_port axm_m0 axm_m0_araddr araddr Output 32

add_interface_port axm_m0 axm_m0_arprot arprot Output 3

add_interface_port axm_m0 axm_m0_arvalid arvalid Output 1

add_interface_port axm_m0 axm_m0_arready arready Input 1

add_interface_port axm_m0 axm_m0_rdata rdata Input 32

add_interface_port axm_m0 axm_m0_rvalid rvalid Input 1

add_interface_port axm_m0 axm_m0_rready rready Output 1

# 

# connection point driver

# 

add_interface driver conduit end

set_interface_property driver associatedClock clock

set_interface_property driver associatedReset ""

set_interface_property driver ENABLED true

set_interface_property driver EXPORT_OF ""

set_interface_property driver PORT_NAME_MAP ""

set_interface_property driver CMSIS_SVD_VARIABLES ""

set_interface_property driver SVD_ADDRESS_GROUP ""

add_interface_port driver addr new_signal Input 32

add_interface_port driver r_data new_signal_1 Output 32

add_interface_port driver transaction_type new_signal_2 Input 1

add_interface_port driver w_data new_signal_3 Input 32

add_interface_port driver done new_signal_4 Output 1

add_interface_port driver start new_signal_5 Input 1

# 

# connection point reset_1

# 

add_interface reset_1 reset end

set_interface_property reset_1 associatedClock clock

set_interface_property reset_1 synchronousEdges DEASSERT

set_interface_property reset_1 ENABLED true

set_interface_property reset_1 EXPORT_OF ""

set_interface_property reset_1 PORT_NAME_MAP ""

set_interface_property reset_1 CMSIS_SVD_VARIABLES ""

set_interface_property reset_1 SVD_ADDRESS_GROUP ""

add_interface_port reset_1 reset_reset reset Input 1