1 |
207 |
jshamlet |
-- Copyright (c)2006, 2016, 2019 Jeremy Seth Henry
|
2 |
|
|
-- All rights reserved.
|
3 |
|
|
--
|
4 |
|
|
-- Redistribution and use in source and binary forms, with or without
|
5 |
|
|
-- modification, are permitted provided that the following conditions are met:
|
6 |
|
|
-- * Redistributions of source code must retain the above copyright
|
7 |
|
|
-- notice, this list of conditions and the following disclaimer.
|
8 |
|
|
-- * Redistributions in binary form must reproduce the above copyright
|
9 |
|
|
-- notice, this list of conditions and the following disclaimer in the
|
10 |
|
|
-- documentation and/or other materials provided with the distribution,
|
11 |
|
|
-- where applicable (as part of a user interface, debugging port, etc.)
|
12 |
|
|
--
|
13 |
|
|
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
|
14 |
|
|
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
15 |
|
|
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
16 |
|
|
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
|
17 |
|
|
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
18 |
|
|
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
19 |
|
|
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
20 |
|
|
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
21 |
|
|
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
22 |
|
|
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
23 |
|
|
--
|
24 |
|
|
-- VHDL Units : async_ser_tx
|
25 |
|
|
-- Description: Asynchronous transmitter wired for 8[N/E/O]1 data. Parity mode
|
26 |
|
|
-- and bit rate are set with generics.
|
27 |
209 |
jshamlet |
--
|
28 |
|
|
-- Note: The baud rate generator will produce an approximate frequency. The
|
29 |
|
|
-- final bit rate should be within +/- 1% of the true bit rate to
|
30 |
|
|
-- ensure the receiver can successfully receive. With a sufficiently
|
31 |
|
|
-- high core clock, this is generally achievable for common PC serial
|
32 |
|
|
-- data rates.
|
33 |
207 |
jshamlet |
|
34 |
|
|
library ieee;
|
35 |
|
|
use ieee.std_logic_1164.all;
|
36 |
|
|
use ieee.std_logic_unsigned.all;
|
37 |
|
|
use ieee.std_logic_arith.all;
|
38 |
|
|
use ieee.std_logic_misc.all;
|
39 |
|
|
|
40 |
|
|
entity async_ser_tx is
|
41 |
|
|
generic(
|
42 |
215 |
jshamlet |
Reset_Level : std_logic;
|
43 |
|
|
Enable_Parity : boolean;
|
44 |
|
|
Parity_Odd_Even_n : std_logic;
|
45 |
|
|
Clock_Divider : integer
|
46 |
207 |
jshamlet |
);
|
47 |
|
|
port(
|
48 |
215 |
jshamlet |
Clock : in std_logic;
|
49 |
|
|
Reset : in std_logic;
|
50 |
|
|
--
|
51 |
|
|
Tx_Data : in std_logic_vector(7 downto 0);
|
52 |
|
|
Tx_Valid : in std_logic;
|
53 |
|
|
--
|
54 |
|
|
Tx_Out : out std_logic;
|
55 |
|
|
Tx_Done : out std_logic
|
56 |
|
|
|
57 |
207 |
jshamlet |
end entity;
|
58 |
|
|
|
59 |
|
|
architecture behave of async_ser_tx is
|
60 |
|
|
|
61 |
208 |
jshamlet |
-- The ceil_log2 function returns the minimum register width required to
|
62 |
|
|
-- hold the supplied integer.
|
63 |
|
|
function ceil_log2 (x : in natural) return natural is
|
64 |
|
|
variable retval : natural;
|
65 |
|
|
begin
|
66 |
|
|
retval := 1;
|
67 |
|
|
while ((2**retval) - 1) < x loop
|
68 |
|
|
retval := retval + 1;
|
69 |
|
|
end loop;
|
70 |
|
|
return retval;
|
71 |
|
|
end ceil_log2;
|
72 |
|
|
|
73 |
207 |
jshamlet |
constant Tick_Base : integer := Clock_Divider - 1;
|
74 |
|
|
constant Tick_Bits : integer := ceil_log2(Tick_Base);
|
75 |
|
|
constant TICK_DIV : std_logic_vector(Tick_Bits - 1 downto 0) :=
|
76 |
|
|
conv_std_logic_vector(Tick_Base, Tick_Bits);
|
77 |
|
|
|
78 |
208 |
jshamlet |
signal Tick_Cntr : std_logic_vector(Tick_Bits - 1 downto 0) :=
|
79 |
|
|
(others => '0');
|
80 |
207 |
jshamlet |
|
81 |
208 |
jshamlet |
signal Tick_Trig : std_logic := '0';
|
82 |
|
|
signal Tx_Enable : std_logic := '0';
|
83 |
|
|
signal Tx_Buffer : std_logic_vector(7 downto 0) := x"00";
|
84 |
|
|
signal Tx_Parity : std_logic := '0';
|
85 |
|
|
signal Tx_State : std_logic_vector(3 downto 0) := x"0";
|
86 |
207 |
jshamlet |
alias Tx_Bit_Sel is Tx_State(2 downto 0);
|
87 |
|
|
|
88 |
|
|
-- State machine definitions
|
89 |
|
|
constant IO_RSV0 : std_logic_vector(3 downto 0) := "1011"; -- B
|
90 |
|
|
constant IO_RSV1 : std_logic_vector(3 downto 0) := "1100"; -- C
|
91 |
|
|
constant IO_RSV2 : std_logic_vector(3 downto 0) := "1101"; -- D
|
92 |
|
|
constant IO_IDLE : std_logic_vector(3 downto 0) := "1110"; -- E
|
93 |
|
|
constant IO_STRT : std_logic_vector(3 downto 0) := "1111"; -- F
|
94 |
|
|
constant IO_BIT0 : std_logic_vector(3 downto 0) := "0000"; -- 0
|
95 |
|
|
constant IO_BIT1 : std_logic_vector(3 downto 0) := "0001"; -- 1
|
96 |
|
|
constant IO_BIT2 : std_logic_vector(3 downto 0) := "0010"; -- 2
|
97 |
|
|
constant IO_BIT3 : std_logic_vector(3 downto 0) := "0011"; -- 3
|
98 |
|
|
constant IO_BIT4 : std_logic_vector(3 downto 0) := "0100"; -- 4
|
99 |
|
|
constant IO_BIT5 : std_logic_vector(3 downto 0) := "0101"; -- 5
|
100 |
|
|
constant IO_BIT6 : std_logic_vector(3 downto 0) := "0110"; -- 6
|
101 |
|
|
constant IO_BIT7 : std_logic_vector(3 downto 0) := "0111"; -- 7
|
102 |
|
|
constant IO_PARI : std_logic_vector(3 downto 0) := "1000"; -- 8
|
103 |
|
|
constant IO_STOP : std_logic_vector(3 downto 0) := "1001"; -- 9
|
104 |
|
|
constant IO_DONE : std_logic_vector(3 downto 0) := "1010"; -- A
|
105 |
|
|
|
106 |
|
|
begin
|
107 |
|
|
|
108 |
|
|
UART_Regs: process( Clock, Reset )
|
109 |
|
|
begin
|
110 |
|
|
if( Reset = Reset_Level )then
|
111 |
|
|
Tick_Cntr <= (others => '0');
|
112 |
|
|
Tick_Trig <= '0';
|
113 |
|
|
Tx_State <= IO_IDLE;
|
114 |
|
|
Tx_Enable <= '0';
|
115 |
|
|
Tx_Buffer <= (others => '0');
|
116 |
|
|
if( Enable_Parity )then
|
117 |
|
|
Tx_Parity <= '0';
|
118 |
|
|
end if;
|
119 |
|
|
Tx_Out <= '1';
|
120 |
|
|
Tx_Done <= '0';
|
121 |
|
|
elsif( rising_edge(Clock) )then
|
122 |
|
|
Tick_Cntr <= (others => '0');
|
123 |
|
|
Tick_Trig <= '0';
|
124 |
|
|
|
125 |
|
|
if( Tx_Enable = '1' )then
|
126 |
|
|
Tick_Cntr <= Tick_Cntr - 1;
|
127 |
|
|
Tick_Trig <= '0';
|
128 |
|
|
if( or_reduce(Tick_Cntr) = '0' )then
|
129 |
|
|
Tick_Cntr <= TICK_DIV;
|
130 |
|
|
Tick_Trig <= '1';
|
131 |
|
|
end if;
|
132 |
|
|
end if;
|
133 |
|
|
|
134 |
|
|
if( Tx_Valid = '1' )then
|
135 |
|
|
Tx_Buffer <= Tx_Data;
|
136 |
|
|
Tx_Enable <= '1';
|
137 |
|
|
end if;
|
138 |
|
|
|
139 |
|
|
Tx_State <= Tx_State + Tick_Trig;
|
140 |
|
|
Tx_Done <= '0';
|
141 |
|
|
Tx_Out <= '1';
|
142 |
|
|
|
143 |
|
|
case( Tx_State )is
|
144 |
|
|
when IO_IDLE =>
|
145 |
|
|
if( Enable_Parity )then
|
146 |
|
|
Tx_Parity <= Parity_Odd_Even_n;
|
147 |
|
|
end if;
|
148 |
|
|
|
149 |
|
|
when IO_STRT =>
|
150 |
|
|
Tx_Out <= '0';
|
151 |
|
|
|
152 |
|
|
when IO_BIT0 | IO_BIT1 | IO_BIT2 | IO_BIT3 |
|
153 |
|
|
IO_BIT4 | IO_BIT5 | IO_BIT6 | IO_BIT7 =>
|
154 |
|
|
Tx_Out <= Tx_Buffer(conv_integer(Tx_Bit_Sel));
|
155 |
|
|
if( Tick_Trig = '1' and Enable_Parity )then
|
156 |
|
|
Tx_Parity <= Tx_Parity xor Tx_Buffer(conv_integer(Tx_Bit_Sel));
|
157 |
|
|
end if;
|
158 |
|
|
|
159 |
|
|
when IO_PARI =>
|
160 |
|
|
if( Enable_Parity )then
|
161 |
|
|
Tx_Out <= Tx_Parity;
|
162 |
|
|
end if;
|
163 |
|
|
|
164 |
|
|
when IO_STOP =>
|
165 |
|
|
|
166 |
|
|
when IO_DONE =>
|
167 |
|
|
Tx_Done <= '1';
|
168 |
|
|
Tx_Enable <= '0';
|
169 |
|
|
Tx_State <= IO_IDLE;
|
170 |
|
|
|
171 |
|
|
when others =>
|
172 |
|
|
|
173 |
|
|
end case;
|
174 |
|
|
|
175 |
|
|
if( Tx_Enable = '0' )then
|
176 |
|
|
Tx_State <= IO_IDLE;
|
177 |
|
|
end if;
|
178 |
|
|
|
179 |
|
|
end if;
|
180 |
|
|
end process;
|
181 |
|
|
|
182 |
|
|
end architecture;
|