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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_async_serial.vhd] - Blame information for rev 244

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1 207 jshamlet
-- Copyright (c)2020 Jeremy Seth Henry
2
-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--     * Redistributions of source code must retain the above copyright
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--       notice, this list of conditions and the following disclaimer.
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--     * Redistributions in binary form must reproduce the above copyright
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--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
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--       where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 213 jshamlet
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 207 jshamlet
--
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-- VHDL Units :  o8_async_serial
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-- Description:  Provides a single 8-bit, asynchronous transceiver. While the
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--               width is fixed at 8-bits, the bit rate and parity controls
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--               are settable via generics.
28 209 jshamlet
--
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-- Register Map:
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-- Offset  Bitfield Description                        Read/Write
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--   0x00  AAAAAAAA TX Data (WR) RX Data (RD)             (RW)
32 244 jshamlet
--   0x01  EDCBA--- FIFO Status                           (RO*)
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--                  A: RX Parity Error (write to clear)
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--                  B: RX FIFO Empty
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--                  C: RX FIFO almost full (922/1024)
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--                  D: TX FIFO Empty
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--                  E: TX FIFO almost full (922/1024)
38 213 jshamlet
--
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-- Note: The baud rate generator will produce an approximate frequency. The
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--        final bit rate should be within +/- 1% of the true bit rate to
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--        ensure the receiver can successfully receive. With a sufficiently
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--        high core clock, this is generally achievable for common PC serial
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--        data rates.
44 213 jshamlet
--
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-- Revision History
46
-- Author          Date     Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry      12/20/19 Design Start
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-- Seth Henry      04/10/20 Code cleanup and register documentation
50 224 jshamlet
-- Seth Henry      04/16/20 Modified to use Open8 bus record
51 244 jshamlet
-- Seth Henry      05/18/20 Added write qualification input
52 207 jshamlet
 
53
library ieee;
54
use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_misc.all;
58
 
59
library work;
60
  use work.open8_pkg.all;
61
 
62
entity o8_async_serial is
63
generic(
64 217 jshamlet
  Disable_Transmit           : boolean := FALSE;
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  Disable_Receive            : boolean := FALSE;
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  Bit_Rate                   : real;
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  Enable_Parity              : boolean;
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  Parity_Odd_Even_n          : std_logic;
69 224 jshamlet
  Clock_Frequency            : real;
70 217 jshamlet
  Address                    : ADDRESS_TYPE
71 207 jshamlet
);
72
port(
73 223 jshamlet
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
74 244 jshamlet
  Write_Qual                 : in  std_logic := '1';
75 217 jshamlet
  Rd_Data                    : out DATA_TYPE;
76 207 jshamlet
  --
77 217 jshamlet
  TX_Out                     : out std_logic;
78 244 jshamlet
  CTS_In                     : in  std_logic := '1';
79
  RX_In                      : in  std_logic := '1';
80 217 jshamlet
  RTS_Out                    : out std_logic
81 207 jshamlet
);
82
end entity;
83
 
84
architecture behave of o8_async_serial is
85
 
86 224 jshamlet
  alias Clock                is Open8_Bus.Clock;
87
  alias Reset                is Open8_Bus.Reset;
88
  alias uSec_Tick            is Open8_Bus.uSec_Tick;
89 244 jshamlet
  alias Wr_En                is Open8_Bus.Wr_En;
90
  alias Wr_Data              is Open8_Bus.Wr_Data;
91
  alias Rd_En                is Open8_Bus.Rd_En;
92 224 jshamlet
 
93 207 jshamlet
  signal FIFO_Reset          : std_logic := '0';
94
 
95
  constant User_Addr         : std_logic_vector(15 downto 1) :=
96
                                Address(15 downto 1);
97 223 jshamlet
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 1);
98 207 jshamlet
  signal Addr_Match          : std_logic := '0';
99
 
100 244 jshamlet
  alias  Reg_Sel_d           is Open8_Bus.Address(0);
101
  signal Reg_Sel_q           : std_logic := '0';
102
  signal Wr_En_d             : std_logic := '0';
103
  signal Wr_En_q             : std_logic := '0';
104
  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
105
  signal Wr_Data_q           : DATA_TYPE := x"00";
106
  signal Rd_En_d             : std_logic := '0';
107
  signal Rd_En_q             : std_logic := '0';
108 207 jshamlet
 
109
  signal TX_FIFO_Wr_En       : std_logic := '0';
110 244 jshamlet
  signal TX_FIFO_Wr_Data     : DATA_TYPE := x"00";
111 207 jshamlet
  signal TX_FIFO_Rd_En       : std_logic := '0';
112
  signal TX_FIFO_Empty       : std_logic := '0';
113
  signal TX_FIFO_AFull       : std_logic := '0';
114
  signal TX_FIFO_Rd_Data     : DATA_TYPE := x"00";
115
 
116
  alias  Tx_Data             is TX_FIFO_Rd_Data;
117
 
118
  type TX_CTRL_STATES is (IDLE, TX_BYTE, TX_START, TX_WAIT );
119
  signal TX_Ctrl             : TX_CTRL_STATES := IDLE;
120
 
121
  signal TX_Xmit             : std_logic := '0';
122
  signal TX_Done             : std_logic := '0';
123
 
124 224 jshamlet
  constant BAUD_RATE_DIV     : integer := integer(Clock_Frequency / Bit_Rate);
125 207 jshamlet
 
126
  signal CTS_sr              : std_logic_vector(3 downto 0) := "0000";
127
  alias  CTS_Okay            is CTS_sr(3);
128
 
129
  signal RX_FIFO_Wr_En       : std_logic := '0';
130 209 jshamlet
  signal RX_FIFO_Wr_Data     : DATA_TYPE := x"00";
131
  signal RX_FIFO_Rd_En       : std_logic := '0';
132
  signal RX_FIFO_Empty       : std_logic := '0';
133
  signal RX_FIFO_AFull       : std_logic := '0';
134
  signal RX_FIFO_Rd_Data     : DATA_TYPE := x"00";
135 207 jshamlet
 
136 244 jshamlet
  signal Rx_PErr             : std_logic := '0';
137
  signal RX_Parity_Err       : std_logic := '0';
138
 
139 207 jshamlet
begin
140
 
141
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
142 244 jshamlet
  Wr_En_d                    <= Addr_Match and Open8_Bus.Wr_En;
143
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
144 207 jshamlet
 
145
  io_reg: process( Clock, Reset )
146
  begin
147
    if( Reset = Reset_Level )then
148 244 jshamlet
      Reg_Sel_q              <= '0';
149
      Wr_En_q                <= '0';
150
      Wr_Data_q              <= x"00";
151
      Rd_En_q                <= '0';
152 217 jshamlet
      Rd_Data                <= OPEN8_NULLBUS;
153
      RTS_Out                <= '0';
154 244 jshamlet
      RX_Parity_Err          <= '0';
155 207 jshamlet
    elsif( rising_edge( Clock ) )then
156 244 jshamlet
      Reg_Sel_q              <= Reg_Sel_d;
157
 
158
      Wr_En_q                <= Wr_En_d;
159
      Wr_Data_q              <= Wr_Data_d;
160
 
161
      TX_FIFO_Wr_En          <= Wr_En_q and not Reg_Sel_q;
162
      TX_FIFO_Wr_Data        <= Wr_Data_q;
163
 
164
      if( Rx_PErr = '1' )then
165
        RX_Parity_Err        <= '1';
166
      elsif( Wr_En_q = '1' and Reg_Sel_q = '1' and Write_Qual = '1' )then
167
        RX_Parity_Err        <= '0';
168
      end if;
169
 
170
      Rd_En_q                <= Rd_En_d;
171 217 jshamlet
      Rd_Data                <= OPEN8_NULLBUS;
172 244 jshamlet
      if( Rd_En_q = '1' and Reg_Sel_q = '1' )then
173
                  Rd_Data(3)           <= RX_Parity_Err;
174 217 jshamlet
        Rd_Data(4)           <= RX_FIFO_Empty;
175
        Rd_Data(5)           <= RX_FIFO_AFull;
176
        Rd_Data(6)           <= TX_FIFO_Empty;
177
        Rd_Data(7)           <= TX_FIFO_AFull;
178 207 jshamlet
      end if;
179 244 jshamlet
      if( Rd_En_q = '1' and Reg_Sel_q = '0' )then
180 217 jshamlet
        Rd_Data              <= RX_FIFO_Rd_Data;
181 207 jshamlet
      end if;
182 217 jshamlet
      RTS_Out                <= not RX_FIFO_AFull;
183 244 jshamlet
 
184 207 jshamlet
    end if;
185
  end process;
186
 
187 213 jshamlet
TX_Disabled : if( Disable_Transmit )generate
188
 
189
  TX_FIFO_Empty              <= '1';
190
  TX_FIFO_AFull              <= '0';
191
  TX_Out                     <= '1';
192
 
193
end generate;
194
 
195
TX_Enabled : if( not Disable_Transmit )generate
196
 
197 207 jshamlet
  FIFO_Reset                 <= '1' when Reset = Reset_Level else '0';
198
 
199
  U_TX_FIFO : entity work.fifo_1k_core
200
  port map(
201
    aclr                     => FIFO_Reset,
202
    clock                    => Clock,
203
    data                     => TX_FIFO_Wr_Data,
204
    rdreq                    => TX_FIFO_Rd_En,
205
    wrreq                    => TX_FIFO_Wr_En,
206
    empty                    => TX_FIFO_Empty,
207
    almost_full              => TX_FIFO_AFull,
208
    q                        => TX_FIFO_Rd_Data
209
  );
210
 
211
  tx_FSM: process( Clock, Reset )
212
  begin
213
    if( Reset = Reset_Level )then
214
      TX_Ctrl                <= IDLE;
215
      TX_Xmit                <= '0';
216
      TX_FIFO_Rd_En          <= '0';
217
      CTS_sr                 <= (others => '0');
218
    elsif( rising_edge(Clock) )then
219
      TX_Xmit                <= '0';
220
      TX_FIFO_Rd_En          <= '0';
221
      CTS_sr                 <= CTS_sr(2 downto 0) & CTS_In;
222
 
223
      case( TX_Ctrl )is
224
        when IDLE =>
225
          if( TX_FIFO_Empty = '0' and CTS_Okay = '1' )then
226
            TX_FIFO_Rd_En    <= '1';
227
            TX_Ctrl          <= TX_BYTE;
228
          end if;
229
 
230
        when TX_BYTE =>
231
          TX_Xmit            <= '1';
232
          TX_Ctrl            <= TX_START;
233
 
234
        when TX_START =>
235
          if( Tx_Done = '0' )then
236
            TX_Ctrl          <= TX_WAIT;
237
          end if;
238
 
239
        when TX_WAIT =>
240
          if( Tx_Done = '1' )then
241
            TX_Ctrl          <= IDLE;
242
          end if;
243
 
244
        when others => null;
245
      end case;
246
 
247
    end if;
248
  end process;
249
 
250
  U_TX : entity work.async_ser_tx
251
  generic map(
252
    Reset_Level              => Reset_Level,
253
    Enable_Parity            => Enable_Parity,
254
    Parity_Odd_Even_n        => Parity_Odd_Even_n,
255
    Clock_Divider            => BAUD_RATE_DIV
256
  )
257
  port map(
258
    Clock                    => Clock,
259
    Reset                    => Reset,
260
    --
261
    Tx_Data                  => Tx_Data,
262
    Tx_Valid                 => TX_Xmit,
263
    --
264
    Tx_Out                   => TX_Out,
265
    Tx_Done                  => Tx_Done
266
  );
267
 
268 213 jshamlet
end generate;
269
 
270 244 jshamlet
RX_Disabled : if( Disable_Receive )generate
271 213 jshamlet
 
272 244 jshamlet
  Rx_PErr                    <= '0';
273 213 jshamlet
  RX_FIFO_Empty              <= '1';
274
  RX_FIFO_AFull              <= '0';
275
  RX_FIFO_Rd_Data            <= x"00";
276
 
277
end generate;
278
 
279
RX_Enabled : if( not Disable_Receive )generate
280
 
281 207 jshamlet
  U_RX : entity work.async_ser_rx
282
  generic map(
283
    Reset_Level              => Reset_Level,
284
    Enable_Parity            => Enable_Parity,
285
    Parity_Odd_Even_n        => Parity_Odd_Even_n,
286
    Clock_Divider            => BAUD_RATE_DIV
287
  )
288
  port map(
289
    Clock                    => Clock,
290
    Reset                    => Reset,
291
    --
292
    Rx_In                    => RX_In,
293
    --
294
    Rx_Data                  => RX_FIFO_Wr_Data,
295
    Rx_Valid                 => RX_FIFO_Wr_En,
296 244 jshamlet
    Rx_PErr                  => Rx_PErr
297 207 jshamlet
  );
298
 
299 223 jshamlet
  RX_FIFO_Rd_En              <= Open8_Bus.Rd_En and
300
                                Addr_Match and
301 244 jshamlet
                                (not Reg_Sel_d);
302 207 jshamlet
 
303
  U_RX_FIFO : entity work.fifo_1k_core
304
  port map(
305
    aclr                     => FIFO_Reset,
306
    clock                    => Clock,
307
    data                     => RX_FIFO_Wr_Data,
308
    rdreq                    => RX_FIFO_Rd_En,
309
    wrreq                    => RX_FIFO_Wr_En,
310
    empty                    => RX_FIFO_Empty,
311
    almost_full              => RX_FIFO_AFull,
312
    q                        => RX_FIFO_Rd_Data
313
  );
314
 
315 213 jshamlet
end generate;
316
 
317 207 jshamlet
end architecture;

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