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-- Copyright (c)2006, Jeremy Seth Henry

-- All rights reserved.

--

-- Redistribution and use in source and binary forms, with or without

-- modification, are permitted provided that the following conditions are met:

--     * Redistributions of source code must retain the above copyright

--       notice, this list of conditions and the following disclaimer.

--     * Redistributions in binary form must reproduce the above copyright

--       notice, this list of conditions and the following disclaimer in the

--       documentation and/or other materials provided with the distribution,

--       where applicable (as part of a user interface, debugging port, etc.)

--

-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY

-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY

-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND

-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS

-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-- VHDL Units :  Open8_CPU

-- Description:  VHDL model of the V8 uRISC 8-bit processor core

-- Notes      :  Generic definitions

--            :  Stack_Start_Address - determines the initial (reset) value of

--            :   the stack pointer. Also used for the RSP instruction if

--            :   Allow_Stack_Address_Move is 0.

--            :

--            :  Allow_Stack_Address_Move - When set to 1, allows the RSP to be

--            :   programmed via thet RSP instruction. If enabled, the contents

--            :   of R1:R0 are used to initialize the stack pointer.

--            :

--            :  ISR_Start_Addr - determines the location of the interrupt

--            :   service vector table. There are 8 service vectors, or 16

--            :   bytes, which must be allocated to either ROM or RAM.

--            :

--            :  Program_Start_Addr - Determines the initial value of the

--            :   program counter.

--            :

--            :  Default_Interrupt_Mask - Determines the intial value of the

--            :   interrupt mask. To remain true to the original core, which

--            :   had no interrupt mask, this should be set to x"FF". Otherwise

--            :   it can be initialized to any value.

--            :

--            :  Enable_CPU_Halt - determines whether the CPU_Halt pin is

--            :   connected or not. This signal is typically used to halt the

--            :   processor for a few cycles when accessing slower peripherals,

--            :   but may also be used to single step the processor. If this

--            :   feature isn't used, it can be disabled to increase Fmax.

--            :

--            :  The CPU_Halt signal can be used to access slower peripherals

--            :   by allowing the device to "pause" the CPU. This can be used,

--            :   for example, to write to a standard LCD panel, which requires

--            :   a 4MHz interface, by halting on writes. Alternately, devices

--            :   such as SDRAM controllers, can pause the processor until the

--            :   data is ready to be presented.

--            :

--            :  The Enable_Auto_Increment generic can be used to modify the

--            :   indexed instructions such that specifying an odd register

--            :   will use the next lower register pair, post-incrementing the

--            :   value in that pair. IOW, specifying STX R1 will instead

--            :   result in STX R0++, or R0 = {R1:R0}; {R1:R0} + 1

--            :

--            : Instructions USR and USR2 have been replaced with DBNZ, and MUL

--            :  respectively. DBNZ decrements the specified register, and will

--            :  branch if the result is non-zero (Zero flag is not set). MUL

--            :  places the result of R0 * Rn into R1:R0, and executes in two

--            :  cycles. (R1:R0 = R0 * Rn)

--            :

-- Revision History

-- Author          Date     Change

------------------ -------- ---------------------------------------------------

-- Seth Henry      07/19/06 Design Start

-- Seth Henry      01/18/11 Fixed BTT instruction to match V8

-- Seth Henry      06/14/11 Fixed STO instruction to avoid register corruption

--                          Fixed interrupt logic to avoid address corruption

--                            when interrupt coincides with branch instruction

library ieee;

  use ieee.std_logic_1164.all;

  use ieee.std_logic_unsigned.all;

  use ieee.std_logic_arith.all;

library work;

use work.Open8_pkg.all;

entity Open8_CPU is

  generic(

    Stack_Start_Addr         : ADDRESS_TYPE := x"007F"; -- Top of Stack

    Allow_Stack_Address_Move : boolean      := false;   -- Use Normal v8 RSP

    ISR_Start_Addr           : ADDRESS_TYPE := x"0080"; -- Bottom of ISR vec's

    Program_Start_Addr       : ADDRESS_TYPE := x"0090"; -- Initial PC location

    Default_Interrupt_Mask   : DATA_TYPE    := x"FF";   -- Enable all Ints

    Enable_CPU_Halt          : boolean      := false;   -- Disable HALT pin

    Enable_Auto_Increment    : boolean      := false;   -- Modify indexed instr

    Reset_Level              : std_logic    := '0' );   -- Active reset level

  port(

    Clock                    : in  std_logic;

    Reset                    : in  std_logic;

    CPU_Halt                 : in  std_logic := '0';

    Interrupts               : in  INTERRUPT_BUNDLE;

    --

    Address                  : out ADDRESS_TYPE;

    Rd_Data                  : in  DATA_TYPE;

    Rd_Enable                : out std_logic;

    Wr_Data                  : out DATA_TYPE;

    Wr_Enable                : out std_logic );

end entity;

architecture rtl of Open8_CPU is

  subtype OPCODE_TYPE  is std_logic_vector(4 downto 0);

  subtype SUBOP_TYPE   is std_logic_vector(2 downto 0);

  -- Most of the ALU instructions are the same as their Opcode equivalents with

  -- three exceptions (for IDLE, UPP2, and MUL2)

  constant ALU_INC           : OPCODE_TYPE := "00000"; -- x"00"

  constant ALU_ADC           : OPCODE_TYPE := "00001"; -- x"01"

  constant ALU_TX0           : OPCODE_TYPE := "00010"; -- x"02"

  constant ALU_OR            : OPCODE_TYPE := "00011"; -- x"03"

  constant ALU_AND           : OPCODE_TYPE := "00100"; -- x"04"

  constant ALU_XOR           : OPCODE_TYPE := "00101"; -- x"05"

  constant ALU_ROL           : OPCODE_TYPE := "00110"; -- x"06"

  constant ALU_ROR           : OPCODE_TYPE := "00111"; -- x"07"

  constant ALU_DEC           : OPCODE_TYPE := "01000"; -- x"08"

  constant ALU_SBC           : OPCODE_TYPE := "01001"; -- x"09"

  constant ALU_ADD           : OPCODE_TYPE := "01010"; -- x"0A"

  constant ALU_STP           : OPCODE_TYPE := "01011"; -- x"0B"

  constant ALU_BTT           : OPCODE_TYPE := "01100"; -- x"0C"

  constant ALU_CLP           : OPCODE_TYPE := "01101"; -- x"0D"

  constant ALU_T0X           : OPCODE_TYPE := "01110"; -- x"0E"

  constant ALU_CMP           : OPCODE_TYPE := "01111"; -- x"0F"

  constant ALU_POP           : OPCODE_TYPE := "10001"; -- x"11"

  constant ALU_MUL           : OPCODE_TYPE := "10110"; -- x"16"

  constant ALU_UPP           : OPCODE_TYPE := "11000"; -- x"18"

  constant ALU_LDI           : OPCODE_TYPE := "11100"; -- x"1C"

  constant ALU_LDX           : OPCODE_TYPE := "11110"; -- x"1E"

  constant ALU_IDLE          : OPCODE_TYPE := "10000"; -- x"10"

  constant ALU_UPP2          : OPCODE_TYPE := "10010"; -- x"12"

  constant ALU_RFLG          : OPCODE_TYPE := "10011"; -- x"13"

  constant FL_ZERO           : integer := 0;

  constant FL_CARRY          : integer := 1;

  constant FL_NEG            : integer := 2;

  constant FL_INT_EN         : integer := 3;

  constant FL_GP1            : integer := 4;

  constant FL_GP2            : integer := 5;

  constant FL_GP3            : integer := 6;

  constant FL_GP4            : integer := 7;

  type ALU_CTRL_TYPE is record

    Oper                     : OPCODE_TYPE;

    Reg                      : SUBOP_TYPE;

    Data                     : DATA_TYPE;

  end record;

  constant ACCUM             : SUBOP_TYPE := "000";

  constant INT_FLAG          : SUBOP_TYPE := "011";

  -- There are only 8 byte-wide registers - and the write register is always 0,

  --  so there is little point in making a RAM out of this

  type REGFILE_TYPE is array (0 to 7) of DATA_TYPE;

  subtype FLAG_TYPE is DATA_TYPE;

  type PC_MODES is ( PC_IDLE, PC_REV1, PC_REV2, PC_INCR, PC_LOAD );

  type PC_CTRL_TYPE is record

    Oper                     : PC_MODES;

    Offset                   : DATA_TYPE;

    Addr                     : ADDRESS_TYPE;

  end record;

  type SP_MODES is ( SP_IDLE, SP_RSET, SP_POP, SP_PUSH );

  type SP_CTRL_TYPE is record

    Oper                     : SP_MODES;

    Addr                     : ADDRESS_TYPE;

  end record;

  type INT_CTRL_TYPE is record

    Mask_Set                 : std_logic;

    Mask_Data                : DATA_TYPE;

    Soft_Ints                : INTERRUPT_BUNDLE;

    Incr_ISR                 : std_logic;

  end record;

  type AS_MODES is ( ADDR_PC, ADDR_SP, ADDR_IMM, ADDR_ISR);

  type ADDR_CTRL_TYPE is record

    Src                      : AS_MODES;

  end record;

  type DP_MODES is ( DATA_IDLE, DATA_REG, DATA_FLAG, DATA_PC );

  type DATA_CTRL_TYPE is record

    Src                      : DP_MODES;

    Reg                      : SUBOP_TYPE;

  end record;

  signal Halt                : std_logic;

  signal ALU_Ctrl            : ALU_CTRL_TYPE;

  signal ALU_Regs            : REGFILE_TYPE;

  signal ALU_Flags           : FLAG_TYPE;

  signal PC_Ctrl             : PC_CTRL_TYPE;

  signal SP_Ctrl             : SP_CTRL_TYPE;

  signal AS_Ctrl             : ADDR_CTRL_TYPE;

  signal DP_Ctrl             : DATA_CTRL_TYPE;

  signal INT_Ctrl            : INT_CTRL_TYPE;

  signal Int_Req, Int_Ack    : std_logic;

  signal Int_RTI             : std_logic;

  signal Int_Mask            : DATA_TYPE;

  signal PC                  : ADDRESS_TYPE;

  signal SP                  : ADDRESS_TYPE;

  signal ISR                 : ADDRESS_TYPE;

  signal IMM                 : ADDRESS_TYPE;

begin

Halt_Disabled_fn: if( not Enable_CPU_Halt )generate

  Halt                       <= '0';

end generate;

Halt_Enabled_fn: if( Enable_CPU_Halt )generate

  Halt                       <= CPU_Halt;

end generate;

-------------------------------------------------------------------------------

-- ALU (Arithmetic / Logic Unit

-- Notes:

-- 1) Infers a multiplier in Xilinx/Altera parts - should be checked in others

-------------------------------------------------------------------------------

Open8_ALU : block is

  -- Preinitialization is for simulation only - check actual reset conditions

  signal Regfile_D, Regfile  : REGFILE_TYPE := (others => (others => '0') );

  signal Flags_D, Flags      : FLAG_TYPE    := (others => '0');

  signal Mult                : ADDRESS_TYPE := (others => '0');

  signal Sum                 : std_logic_vector(8 downto 0) := (others => '0');

  signal Addend_A, Addend_B  : DATA_TYPE    := (others => '0');

  signal Carry               : std_logic    := '0';

begin

  ALU_Regs                   <= Regfile;

  ALU_Flags                  <= Flags;

  ALU_proc: process( ALU_Ctrl, Regfile, Flags, Mult, Sum )

    variable Index             : integer range 0 to 7 := 0;

    variable Temp              : std_logic_vector(8 downto 0);

  begin

    Regfile_D                <= Regfile;

    Flags_D                  <= Flags;

    Addend_A                 <= x"00";

    Addend_B                 <= x"00";

    Carry                    <= '0';

    Temp                     := (others => '0');

    Index                    := conv_integer(ALU_Ctrl.Reg);

    case ALU_Ctrl.Oper is

      when ALU_INC | ALU_UPP => -- Rn = Rn + 1 : Flags N,C,Z

        Addend_A             <= x"01";

        Addend_B             <= Regfile(Index);

        Flags_D(FL_CARRY)    <= Sum(8);

        Regfile_D(Index)     <= Sum(7 downto 0);

        -- ALU_INC and ALU_UPP are essentially the same, except that ALU_UPP

        --  doesn't set the N or Z flags. Note that the MSB can be used to

        --  distinguish between the two ALU modes.

        if( ALU_Ctrl.Oper(4) = '0' )then

          Flags_D(FL_ZERO)   <= '0';

          if( Sum(7 downto 0) = 0 )then

            Flags_D(FL_ZERO) <= '1';

          end if;

          Flags_D(FL_NEG)    <= Sum(7);

        end if;

      when ALU_UPP2 => -- Rn = Rn + C

        Addend_A             <= x"00";

        Addend_B             <= Regfile(Index);

        Carry                <= Flags(FL_CARRY);

        Flags_D(FL_CARRY)    <= Sum(8);

        Regfile_D(Index)     <= Sum(7 downto 0);

      when ALU_ADC => -- R0 = R0 + Rn + C : Flags N,C,Z

        Addend_A             <= Regfile(0);

        Addend_B             <= Regfile(Index);

        Carry                <= Flags(FL_CARRY);

        Flags_D(FL_ZERO)     <= '0';

        if( Sum(7 downto 0) = 0 )then

          Flags_D(FL_ZERO)   <= '1';

        end if;

        Flags_D(FL_CARRY)    <= Sum(8);

        Flags_D(FL_NEG)      <= Sum(7);

        Regfile_D(0)         <= Sum(7 downto 0);

      when ALU_TX0 => -- R0 = Rn : Flags N,Z

        Temp                 := "0" & Regfile(Index);

        Flags_D(FL_ZERO)     <= '0';

        if( Temp(7 downto 0) = 0 )then

          Flags_D(FL_ZERO)   <= '1';

        end if;

        Flags_D(FL_NEG)      <= Temp(7);

        Regfile_D(0)         <= Temp(7 downto 0);

      when ALU_OR  => -- R0 = R0 | Rn : Flags N,Z

        Temp(7 downto 0)     := Regfile(0) or Regfile(Index);

        Flags_D(FL_ZERO)     <= '0';

        if( Temp(7 downto 0) = 0 )then

          Flags_D(FL_ZERO)   <= '1';

        end if;

        Flags_D(FL_NEG)      <= Temp(7);

        Regfile_D(0)         <= Temp(7 downto 0);

      when ALU_AND => -- R0 = R0 & Rn : Flags N,Z

        Temp(7 downto 0)     := Regfile(0) and Regfile(Index);

        Flags_D(FL_ZERO)     <= '0';

        if( Temp(7 downto 0) = 0 )then

          Flags_D(FL_ZERO)   <= '1';

        end if;

        Flags_D(FL_NEG)      <= Temp(7);

        Regfile_D(0)         <= Temp(7 downto 0);

      when ALU_XOR => -- R0 = R0 ^ Rn : Flags N,Z

        Temp(7 downto 0)     := Regfile(0) xor Regfile(Index);

        Flags_D(FL_ZERO)     <= '0';

        if( Temp(7 downto 0) = 0 )then

          Flags_D(FL_ZERO)   <= '1';

        end if;

        Flags_D(FL_NEG)      <= Temp(7);

        Regfile_D(0)         <= Temp(7 downto 0);

      when ALU_ROL => -- Rn = Rn<<1,C : Flags N,C,Z

        Temp                 := Regfile(Index) & Flags(FL_CARRY);

        Flags_D(FL_ZERO)     <= '0';

        if( Temp(7 downto 0) = 0 )then

          Flags_D(FL_ZERO)   <= '1';

        end if;

        Flags_D(FL_CARRY)    <= Temp(8);

        Flags_D(FL_NEG)      <= Temp(7);

        Regfile_D(Index)     <= Temp(7 downto 0);

      when ALU_ROR => -- Rn = C,Rn>>1 : Flags N,C,Z

        Temp                 := Regfile(Index)(0) & Flags(FL_CARRY) &

                                Regfile(Index)(7 downto 1);

        Flags_D(FL_ZERO)     <= '0';

        if( Temp(7 downto 0) = 0 )then

          Flags_D(FL_ZERO)   <= '1';

        end if;

        Flags_D(FL_CARRY)    <= Temp(8);

        Flags_D(FL_NEG)      <= Temp(7);

        Regfile_D(Index)     <= Temp(7 downto 0);

      when ALU_DEC => -- Rn = Rn - 1 : Flags N,C,Z

        Addend_A             <= Regfile(Index);

        Addend_B             <= x"FF";

        Flags_D(FL_ZERO)     <= '0';

        if( Sum(7 downto 0) = 0 )then

          Flags_D(FL_ZERO)   <= '1';

        end if;

        Flags_D(FL_CARRY)    <= Sum(8);

        Flags_D(FL_NEG)      <= Sum(7);

        Regfile_D(Index)     <= Sum(7 downto 0);

      when ALU_SBC => -- Rn = R0 - Rn - C : Flags N,C,Z

        Addend_A             <= Regfile(0);

        Addend_B             <= not Regfile(Index);

        Carry                <= Flags(FL_CARRY);

        Flags_D(FL_ZERO)     <= '0';

        if( Sum(7 downto 0) = 0 )then

          Flags_D(FL_ZERO)   <= '1';

        end if;

        Flags_D(FL_CARRY)    <= Sum(8);

        Flags_D(FL_NEG)      <= Sum(7);

        Regfile_D(0)         <= Sum(7 downto 0);

      when ALU_ADD => -- R0 = R0 + Rn : Flags N,C,Z

        Addend_A             <= Regfile(0);

        Addend_B             <= Regfile(Index);

        Flags_D(FL_CARRY)    <= Sum(8);

        Regfile_D(0)         <= Sum(7 downto 0);

        Flags_D(FL_ZERO)     <= '0';

        if( Sum(7 downto 0) = 0 )then

          Flags_D(FL_ZERO)   <= '1';

        end if;

        Flags_D(FL_NEG)      <= Sum(7);

      when ALU_STP => -- Sets bit(n) in the Flags register

        Flags_D(Index)       <= '1';

      when ALU_BTT => -- Z = !R0(N), N = R0(7)

        Flags_D(FL_ZERO)     <= not Regfile(0)(Index);

        Flags_D(FL_NEG)      <= Regfile(0)(7);

--        Temp                 := "0" & Regfile(Index);

--        Flags_D(FL_ZERO)     <= '0';

--        if( Temp(7 downto 0) = 0 )then

--          Flags_D(FL_ZERO)   <= '1';

--        end if;

--        Flags_D(FL_NEG)      <= Temp(7);

      when ALU_CLP => -- Clears bit(n) in the Flags register

        Flags_D(Index)         <= '0';

      when ALU_T0X => -- Rn = R0 : Flags N,Z

        Temp                 := "0" & Regfile(0);

        Flags_D(FL_ZERO)     <= '0';

        if( Temp(7 downto 0) = 0 )then

          Flags_D(FL_ZERO)   <= '1';

        end if;

        Flags_D(FL_NEG)      <= Temp(7);

        Regfile_D(Index)     <= Temp(7 downto 0);

      when ALU_CMP => -- Sets Flags on R0 - Rn : Flags N,C,Z

        Addend_A             <= Regfile(0);

        Addend_B             <= not Regfile(Index);

        Carry                <= '1';

        Flags_D(FL_ZERO)     <= '0';

        if( Sum(7 downto 0) = 0 )then

          Flags_D(FL_ZERO)   <= '1';

        end if;

        Flags_D(FL_CARRY)    <= Sum(8);

        Flags_D(FL_NEG)      <= Sum(7);

      when ALU_MUL => -- Stage 1 of 2 {R1:R0} = R0 * Rn : Flags Z

        Regfile_D(0)         <= Mult(7 downto 0);

        Regfile_D(1)         <= Mult(15 downto 8);

        Flags_D(FL_ZERO)     <= '0';

        if( Mult = 0 )then

          Flags_D(FL_ZERO)   <= '1';

        end if;

      when ALU_LDI | ALU_POP => -- Rn <= Data : Flags N,Z

        -- The POP instruction doesn't alter the flags, so we need to check

        if( ALU_Ctrl.Oper = ALU_LDI )then

          Flags_D(FL_ZERO)   <= '0';

          if( ALU_Ctrl.Data = 0 )then

            Flags_D(FL_ZERO) <= '1';

          end if;

          Flags_D(FL_NEG)    <= ALU_Ctrl.Data(7);

        end if;

        Regfile_D(Index)     <= ALU_Ctrl.Data;

      when ALU_LDX => -- R0 <= Data : Flags N,Z

        Flags_D(FL_ZERO)     <= '0';

        if( ALU_Ctrl.Data = 0 )then

          Flags_D(FL_ZERO)   <= '1';

        end if;

        Flags_D(FL_NEG)      <= ALU_Ctrl.Data(7);

        Regfile_D(0)         <= ALU_Ctrl.Data;

      when ALU_RFLG =>

        Flags_D              <= ALU_Ctrl.Data;

      when others => null;

    end case;

  end process;

  -- 8-bit Adder with carry

  Sum                        <= ("0" & Addend_A) + ("0" & Addend_B) + Carry;

  -- We need to infer a hardware multipler, so we create a special clocked

  --  process with no reset or clock enable

  M_Reg: process( Clock )

  begin

    if( rising_edge(Clock) )then

      Mult                   <= Regfile(0) *

                                Regfile(conv_integer(ALU_Ctrl.Reg));

    end if;

  end process;

  S_Regs: process( Reset, Clock )

  begin

    if( Reset = Reset_Level )then

      for i in 0 to 7 loop

        Regfile(i)           <= (others => '0');

      end loop;

      Flags                  <= x"00";

    elsif( rising_edge(Clock) )then

      if( Halt = '0' )then

        Regfile              <= Regfile_D;

        Flags                <= Flags_D;

      end if;

    end if;

  end process;

end block;

-------------------------------------------------------------------------------

-- Program Counter

-------------------------------------------------------------------------------

Open8_PC : block is

  -- Preinitialization is for simulation only - check actual reset conditions

  signal PC_Q                : ADDRESS_TYPE := (others => '0');

  signal Rewind_1_2n         : std_logic    := '0';

begin

  PC                         <= PC_Q;

  -- This sets the carry input on the "rewind" adder. If the rewind command is

  --  PC_REV2, then we clear the carry. Otherwise, we leave it high.

  Rewind_PC_Calc: process( PC_Ctrl )

  begin

    Rewind_1_2n              <= '1';

    if( PC_Ctrl.Oper = PC_REV2 )then

      Rewind_1_2n            <= '0';

    end if;

  end process;

  Program_Counter: process( Reset, Clock, PC_Ctrl )

    variable PC_Offset_SX    : ADDRESS_TYPE := x"0000";

  begin

    PC_Offset_SX(15 downto 8):= (others => PC_Ctrl.Offset(7));

    PC_Offset_SX(7 downto 0) := PC_Ctrl.Offset;

    if( Reset = Reset_Level )then

      PC_Q                   <= Program_Start_Addr;

    elsif( rising_edge(Clock) )then

      if( Halt = '0' )then

        case PC_Ctrl.Oper is

          when PC_IDLE =>

            null;

          when PC_REV1 | PC_REV2 =>

            PC_Q             <= PC_Q - 2 + Rewind_1_2n;

          when PC_INCR =>

            PC_Q             <= PC_Q + PC_Offset_SX - 2;

          when PC_LOAD =>

            PC_Q             <= PC_Ctrl.Addr;

        end case;

      end if;

    end if;

  end process;

end block;

-------------------------------------------------------------------------------

-- Stack Pointer

-------------------------------------------------------------------------------

Open8_SP : block is

  -- Preinitialization is for simulation only - check actual reset conditions

  signal SP_Q                : ADDRESS_TYPE := (others => '0');

begin

  SP                         <= SP_Q;

  Stack_Pointer: process( Reset, Clock )

  begin

    if( Reset = Reset_Level )then

      SP_Q                   <= Stack_Start_Addr;

    elsif( rising_edge(Clock) )then

      if( Halt = '0' )then

        case SP_Ctrl.Oper is

          when SP_IDLE => null;

          when SP_RSET => SP_Q <= SP_Ctrl.Addr;

          when SP_POP  => SP_Q <= SP_Q + 1;

          when SP_PUSH => SP_Q <= SP_Q - 1;

        end case;

      end if;

    end if;

  end process;

end block;

-------------------------------------------------------------------------------

-- Interrupt Controller

-------------------------------------------------------------------------------

Open8_INT : block is

  -- Preinitialization is for simulation only - check actual reset conditions

  constant INT_VECTOR_0      : ADDRESS_TYPE := ISR_Start_Addr;

  constant INT_VECTOR_1      : ADDRESS_TYPE := ISR_Start_Addr+2;

  constant INT_VECTOR_2      : ADDRESS_TYPE := ISR_Start_Addr+4;

  constant INT_VECTOR_3      : ADDRESS_TYPE := ISR_Start_Addr+6;

  constant INT_VECTOR_4      : ADDRESS_TYPE := ISR_Start_Addr+8;

  constant INT_VECTOR_5      : ADDRESS_TYPE := ISR_Start_Addr+10;

  constant INT_VECTOR_6      : ADDRESS_TYPE := ISR_Start_Addr+12;

  constant INT_VECTOR_7      : ADDRESS_TYPE := ISR_Start_Addr+14;

  signal i_Ints              : INTERRUPT_BUNDLE             := (others => '0');

  signal Pending_D           : INTERRUPT_BUNDLE             := (others => '0');

  signal Pending             : INTERRUPT_BUNDLE             := (others => '0');

  signal Wait_for_FSM        : std_logic := '0';

  signal Mask                : std_logic_vector(6 downto 0) := (others => '0');

  signal ISR_D, ISR_Q        : ADDRESS_TYPE                 := (others => '0');

  type INT_HIST is array (0 to 8) of integer range 0 to 7;

  signal History             : INT_HIST                     := (others => 0);

  signal Int_Trig            : std_logic                    := '0';

  signal Hist_Level          : integer range 0 to 7         := 0;

  signal Hist_Ptr            : integer range 0 to 8         := 0;

begin

  Int_Mask                   <= Mask & '1';

  ISR                        <= ISR_Q;

  Int_Mask_proc: process( Mask, Interrupts, INT_Ctrl )

    variable S_Mask          : std_logic_vector(7 downto 0);

  begin

    S_Mask                   := Mask & '1';

    for i in 0 to 7 loop

      i_Ints(i)              <= (Interrupts(i) or INT_Ctrl.Soft_Ints(i))

                                and S_Mask(i);

    end loop;

  end process;

  Int_Ctrl_proc: process( i_Ints, Pending, Wait_for_FSM, ISR_Q, INT_Ctrl,

                          History, Hist_Ptr )

  begin

    ISR_D                    <= ISR_Q;

    Pending_D                <= Pending;

    Int_Trig                 <= '0';

    Hist_Level               <= 0;

    -- Record any incoming interrupts to the pending buffer

    if( i_Ints > 0 )then

      Pending_D              <= i_Ints;

    end if;