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1 185 jshamlet
-- Copyright (c)2006, 2011, 2012, 2013, 2015, 2019, 2020 Jeremy Seth Henry
2 169 jshamlet
-- All rights reserved.
3
--
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-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
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--       notice, this list of conditions and the following disclaimer.
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--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
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--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 194 jshamlet
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 169 jshamlet
--
24 181 jshamlet
-- VHDL Units :  o8_cpu
25 169 jshamlet
-- Description:  VHDL model of a RISC 8-bit processor core loosely based on the
26
--            :   V8/ARC uRISC instruction set. Requires Open8_pkg.vhd
27
--            :
28
-- Notes      :  Generic definitions
29
--            :
30
--            :  Program_Start_Addr sets the initial value of the program
31
--            :   counter.
32
--            :
33
--            :  ISR_Start_Addr sets the location of the interrupt service
34
--            :   vector table. There are 8 service vectors, or 16 bytes, which
35
--            :   must be allocated to either ROM or RAM.
36
--            :
37
--            :  Stack_Start_Address sets the initial (reset) value of the
38
--            :   stack pointer. Also used for the RSP instruction if
39
--            :   Allow_Stack_Address_Move is false.
40
--            :
41
--            :  Allow_Stack_Address_Move, when set true, allows the RSP to be
42 181 jshamlet
--            :   programmed via thet RSP instruction. If enabled, the
43
--            :   instruction changes into TSX or TXS based on the flag
44
--            :   specified by Stack_Xfer_Flag. If the flag is '0', RSP will
45
--            :   copy the current stack pointer to R1:R0 (TSX). If the flag
46
--            :   is '1', RSP will copy R1:R0 to the stack pointer (TXS). This
47
--            :   allows the processor to backup and restore stack pointers
48
--            :   in a multi-process environment. Note that no flags are
49
--            :   modified by either form of this instruction.
50 169 jshamlet
--            :
51 181 jshamlet
--            :  Stack_Xfer_Flag instructs the core to use the specified ALU
52
--            :   flag to alter the behavior of the RSP instruction when
53
--            :   Allow_Stack_Address_Move is set TRUE, otherwise it is ignored.
54
--            :   While technically any of the status bits may be used, the
55
--            :   intent was to use FL_GP[1,2,3,4], as these are not modified
56
--            :   by ordinary ALU operations.
57
--            :
58 169 jshamlet
--            :  The Enable_Auto_Increment generic can be used to modify the
59
--            :   indexed instructions such that specifying an odd register
60
--            :   will use the next lower register pair, post-incrementing the
61
--            :   value in that pair. IOW, specifying STX R1 will instead
62
--            :   result in STX R0++, or R0 = {R1:R0}; {R1:R0} + 1
63
--            :
64
--            :  BRK_Implements_WAI modifies the BRK instruction such that it
65
--            :   triggers the wait for interrupt state, but without triggering
66
--            :   a soft interrupt in lieu of its normal behavior, which is to
67
--            :   insert several dead clock cycles - essentially a long NOP
68
--            :
69
--            :  Enable_NMI overrides the mask bit for interrupt 0, creating a
70
--            :   non-maskable interrupt at the highest priority. To remain
71
--            :   true to the original core, this should be set false.
72
--            :
73 188 jshamlet
--            :  RTI_Ignores_GP_Flags alters the set of flag bits restored
74
--            :   after an interrupt. By default, all of the flag bits are put
75
--            :   back to their original state. If this flag is set true, only
76
--            :   the lower four bits are restored, allowing ISR code to alter
77
--            :   the GP flags persistently.
78
--            :
79 244 jshamlet
--            :  Supervisor_Mode, when set, disables the STP PSR_I instruction
80
--            :   preventing code from setting the I bit. When enabled, only
81
--            :   interrupts can set the I bit, allowing for more robust memory
82
--            :   protection by preventing errant code execution from
83
--            :   inadvertently entering an interrupt state.
84
--            :
85
--            :  Default_Int_Flag allows the initial state of the I bit to be
86
--            :   set at startup. If set, initialization code may be run in an
87
--            :   ISR context, disabling memory protection initially. Init code
88
--            :   should clear the I bit when done;
89
--            :
90 169 jshamlet
--            :  Default_Interrupt_Mask sets the intial/reset value of the
91
--            :   interrupt mask. To remain true to the original core, which
92
--            :   had no interrupt mask, this should be set to x"FF". Otherwise
93
--            :   it can be initialized to any value. Note that Enable_NMI
94
--            :   will logically force the LSB high.
95 172 jshamlet
--            :
96 169 jshamlet
--            :  Reset_Level determines whether the processor registers reset
97
--            :   on a high or low level from higher logic.
98
--            :
99
--            : Architecture notes
100
--            :  This model deviates from the original ISA in a few important
101
--            :   ways.
102
--            :
103
--            :  First, there is only one set of registers. Interrupt service
104
--            :   routines must explicitely preserve context since the the
105
--            :   hardware doesn't. This was done to decrease size and code
106
--            :   complexity. Older code that assumes this behavior will not
107
--            :   execute correctly on this processor model.
108
--            :
109
--            :  Second, this model adds an additional pipeline stage between
110
--            :   the instruction decoder and the ALU. Unfortunately, this
111
--            :   means that the instruction stream has to be restarted after
112
--            :   any math instruction is executed, implying that any ALU
113
--            :   instruction now has a latency of 2 instead of 0. The
114
--            :   advantage is that the maximum frequency has gone up
115
--            :   significantly, as the ALU code is vastly more efficient.
116
--            :   As an aside, this now means that all math instructions,
117
--            :   including MUL (see below) and UPP have the same instruction
118
--            :   latency.
119
--            :
120
--            :  Third, the original ISA, also a soft core, had two reserved
121
--            :   instructions, USR and USR2. These have been implemented as
122
--            :   DBNZ, and MUL respectively.
123
--            :
124
--            :  DBNZ decrements the specified register and branches if the
125
--            :   result is non-zero. The instruction effectively executes a
126
--            :   DEC Rn instruction prior to branching, so the same flags will
127
--            :   be set.
128
--            :
129
--            :  MUL places the result of R0 * Rn into R1:R0. Instruction
130
--            :   latency is identical to other ALU instructions. Only the Z
131
--            :   flag is set, since there is no defined overflow or "negative
132
--            :   16-bit values"
133
--            :
134
--            :  Fourth, indexed load/store instructions now have an (optional)
135
--            :   ability to post-increment their index registers. If enabled,
136
--            :   using an odd operand for LDO,LDX, STO, STX will cause the
137
--            :   register pair to be incremented after the storage access.
138
--            :
139
--            :  Fifth, the RSP instruction has been (optionally) altered to
140
--            :   allow the stack pointer to be sourced from R1:R0.
141
--            :
142
--            :  Sixth, the BRK instruction can optionally implement a WAI,
143
--            :   which is the same as the INT instruction without the soft
144
--            :   interrupt, as a way to put the processor to "sleep" until the
145
--            :   next external interrupt.
146
--            :
147
--            :  Seventh, the original CPU model had 8 non-maskable interrupts
148
--            :   with priority. This model has the same 8 interrupts, but
149 172 jshamlet
--            :   allows software to mask them (with an additional option to
150 169 jshamlet
--            :   override the highest priority interrupt, making it the NMI.)
151
--            :
152
--            :  Lastly, previous unmapped instructions in the OP_STK opcode
153
--            :   were repurposed to support a new interrupt mask.
154
--            :   SMSK and GMSK transfer the contents of R0 (accumulator)
155
--            :   to/from the interrupt mask register. SMSK is immediate, while
156
--            :   GMSK has the same overhead as a math instruction.
157
--
158
-- Revision History
159
-- Author          Date     Change
160
------------------ -------- ---------------------------------------------------
161
-- Seth Henry      07/19/06 Design Start
162
-- Seth Henry      01/18/11 Fixed BTT instruction to match V8
163
-- Seth Henry      07/22/11 Fixed interrupt transition logic to avoid data
164
--                           corruption issues.
165
-- Seth Henry      07/26/11 Optimized logic in ALU, stack pointer, and data
166
--                           path sections.
167
-- Seth Henry      07/27/11 Optimized logic for timing, merged blocks into
168
--                           single entity.
169
-- Seth Henry      09/20/11 Added BRK_Implements_WAI option, allowing the
170
--                           processor to wait for an interrupt instead of the
171
--                           normal BRK behavior.
172 187 jshamlet
-- Seth Henry      12/20/11 Modified core to allow WAI_Cx state to idle
173 169 jshamlet
--                           the bus entirely (Rd_Enable is low)
174
-- Seth Henry      02/03/12 Replaced complex interrupt controller with simpler,
175
--                           faster logic that simply does priority encoding.
176
-- Seth Henry      08/06/13 Removed HALT functionality
177
-- Seth Henry      10/29/15 Fixed inverted carry logic in CMP and SBC instrs
178 182 jshamlet
-- Seth Henry      12/19/19 Renamed to o8_cpu to fit "theme"
179 181 jshamlet
-- Seth Henry      03/09/20 Modified RSP instruction to work with a CPU flag
180
--                           allowing true backup/restore of the stack pointer
181 182 jshamlet
-- Seth Henry      03/11/20 Split the address logic from the main state machine
182
--                           in order to simplify things and eliminate
183
--                           redundancies. Came across and fixed a problem with
184
--                           the STO instruction when Enable_Auto_Increment is
185
--                           NOT set.
186 185 jshamlet
-- Seth Henry      03/12/20 Rationalized the naming of the CPU flags to match
187
--                           the assembler names. Also fixed an issue where
188
--                           the I bit wasn't being cleared after interrupts.
189
--                          Simplified the program counter logic to only use
190
--                           the offset for increments, redefining the
191
--                           original modes as fixed offset values.
192
--                          Modified the ALU section with a new ALU operation
193
--                           for GMSK. This allowed the .data field to be
194
--                           removed and Operand1 used in its place, which
195
--                           simplified the logic a great deal.
196 187 jshamlet
-- Seth Henry      03/16/20 Added CPU_Halt input back, only now as an input to
197
--                           the instruction decode state, where it acts as a
198
--                           modified form of the BRK instruction that holds
199
--                           state until CPU_Halt is deasserted. This has a
200
--                           much smaller impact on Fmax/complexity than the
201
--                           original clock enable, but imposes a mild impact
202
--                           due to the need to reset the instruction pipeline
203 188 jshamlet
-- Seth Henry      03/17/20 Added generic to control whether RTI full restores
204
--                           the flags, including the general purpose ones, or
205
--                           only the core ALU flags (Z, N, and C). Also
206
--                           brought out copies of the GP flags for external
207
--                           connection.
208 210 jshamlet
-- Seth Henry      04/09/20 Added a compile time setting to block interrupts
209
--                           while the I bit is set to avoid reentering ISRs
210
--                           This may slightly affect timing, as this will
211
--                           potentially block higher priority interrupts
212
--                           until the lower priority ISR returns or clears
213
--                           the I bit.
214
--                          Also added the I bit to the exported flags for
215
--                           use in memory protection schemes.
216 224 jshamlet
-- Seth Henry      04/16/20 Modified to use new Open8 bus record. Also added
217 225 jshamlet
--                           reset and usec_tick logic to drive utility
218
--                           signals. Also added Halt_Ack output.
219 244 jshamlet
-- Seth Henry      05/20/20 Added two new generics to alter the way the I bit
220
--                           is handled. The Supervisor_Mode setting disables
221
--                           STP PSR_I from being executed, preventing it
222
--                           from being set outside of an ISR. The
223
--                           Default_Int_Flag setting allows the I bit to
224
--                           start set so that initialization code can run,
225
--                           but not be hijacked later to corrupt any memory
226
--                           write protection later.
227 169 jshamlet
 
228
library ieee;
229
  use ieee.std_logic_1164.all;
230
  use ieee.std_logic_unsigned.all;
231
  use ieee.std_logic_arith.all;
232
  use ieee.std_logic_misc.all;
233
 
234
library work;
235 227 jshamlet
  use work.Open8_pkg.all;
236 169 jshamlet
 
237 183 jshamlet
entity o8_cpu is
238 169 jshamlet
  generic(
239
    Program_Start_Addr       : ADDRESS_TYPE := x"0000"; -- Initial PC location
240
    ISR_Start_Addr           : ADDRESS_TYPE := x"FFF0"; -- Bottom of ISR vec's
241
    Stack_Start_Addr         : ADDRESS_TYPE := x"03FF"; -- Top of Stack
242
    Allow_Stack_Address_Move : boolean      := false;   -- Use Normal v8 RSP
243 188 jshamlet
    Stack_Xfer_Flag          : integer      := PSR_GP4; -- GP4 modifies RSP
244 169 jshamlet
    Enable_Auto_Increment    : boolean      := false;   -- Modify indexed instr
245
    BRK_Implements_WAI       : boolean      := false;   -- BRK -> Wait for Int
246
    Enable_NMI               : boolean      := true;    -- Force INTR0 enabled
247 210 jshamlet
    Sequential_Interrupts    : boolean      := false;   -- Interruptable ISRs
248 224 jshamlet
    RTI_Ignores_GP_Flags     : boolean      := false;   -- RTI sets all flags
249 244 jshamlet
    Supervisor_Mode          : boolean      := false;   -- I bit is restricted
250
    Default_Int_Flag         : boolean      := false;   -- Start with I bit set
251 169 jshamlet
    Default_Interrupt_Mask   : DATA_TYPE    := x"FF";   -- Enable all Ints
252 224 jshamlet
    Clock_Frequency          : real                     -- Clock Frequency
253
);
254 169 jshamlet
  port(
255
    Clock                    : in  std_logic;
256 224 jshamlet
    PLL_Locked               : in  std_logic;
257 169 jshamlet
    --
258 225 jshamlet
    Halt_Req                 : in  std_logic := '0';
259
    Halt_Ack                 : out std_logic;
260
    --
261 223 jshamlet
    Open8_Bus                : out OPEN8_BUS_TYPE;
262 169 jshamlet
    Rd_Data                  : in  DATA_TYPE;
263 223 jshamlet
    Interrupts               : in  INTERRUPT_BUNDLE := x"00"
264
);
265 169 jshamlet
end entity;
266
 
267 183 jshamlet
architecture behave of o8_cpu is
268 169 jshamlet
 
269 224 jshamlet
  signal Reset_q             : std_logic := Reset_Level;
270
  signal Reset               : std_logic := Reset_Level;
271
 
272
  constant USEC_VAL          : integer := integer(Clock_Frequency / 1000000.0);
273
  constant USEC_WDT          : integer := ceil_log2(USEC_VAL - 1);
274
  constant USEC_DLY          : std_logic_vector :=
275
                                conv_std_logic_vector(USEC_VAL - 1, USEC_WDT);
276
  signal uSec_Cntr           : std_logic_vector( USEC_WDT - 1 downto 0 );
277
  signal uSec_Tick           : std_logic;
278
 
279 169 jshamlet
  constant INT_VECTOR_0      : ADDRESS_TYPE := ISR_Start_Addr;
280
  constant INT_VECTOR_1      : ADDRESS_TYPE := ISR_Start_Addr+2;
281
  constant INT_VECTOR_2      : ADDRESS_TYPE := ISR_Start_Addr+4;
282
  constant INT_VECTOR_3      : ADDRESS_TYPE := ISR_Start_Addr+6;
283
  constant INT_VECTOR_4      : ADDRESS_TYPE := ISR_Start_Addr+8;
284
  constant INT_VECTOR_5      : ADDRESS_TYPE := ISR_Start_Addr+10;
285
  constant INT_VECTOR_6      : ADDRESS_TYPE := ISR_Start_Addr+12;
286
  constant INT_VECTOR_7      : ADDRESS_TYPE := ISR_Start_Addr+14;
287
 
288 187 jshamlet
  signal CPU_Next_State      : CPU_STATES := IPF_C0;
289
  signal CPU_State           : CPU_STATES := IPF_C0;
290 169 jshamlet
 
291 225 jshamlet
  signal CPU_Halt_Req        : std_logic := '0';
292
  signal CPU_Halt_Ack        : std_logic := '0';
293 187 jshamlet
 
294 169 jshamlet
  signal Cache_Ctrl          : CACHE_MODES := CACHE_IDLE;
295
 
296
  signal Opcode              : OPCODE_TYPE := (others => '0');
297
  signal SubOp, SubOp_p1     : SUBOP_TYPE  := (others => '0');
298
 
299
  signal Prefetch            : DATA_TYPE   := x"00";
300
  signal Operand1, Operand2  : DATA_TYPE   := x"00";
301
 
302
  signal Instr_Prefetch      : std_logic   := '0';
303
 
304
  signal PC_Ctrl             : PC_CTRL_TYPE;
305
  signal Program_Ctr         : ADDRESS_TYPE := x"0000";
306
 
307 182 jshamlet
  signal ALU_Ctrl            : ALU_CTRL_TYPE;
308
  signal Regfile             : REGFILE_TYPE;
309
  signal Flags               : FLAG_TYPE;
310
  signal Mult                : ADDRESS_TYPE := x"0000";
311
 
312 169 jshamlet
  signal SP_Ctrl             : SP_CTRL_TYPE;
313
  signal Stack_Ptr           : ADDRESS_TYPE := x"0000";
314
 
315
  signal DP_Ctrl             : DATA_CTRL_TYPE;
316
 
317
  signal INT_Ctrl            : INT_CTRL_TYPE;
318
  signal Ack_D, Ack_Q, Ack_Q1: std_logic   := '0';
319
  signal Int_Req, Int_Ack    : std_logic   := '0';
320
  signal Int_Mask            : DATA_TYPE   := x"00";
321
  signal ISR_Addr            : ADDRESS_TYPE := x"0000";
322
  signal i_Ints              : INTERRUPT_BUNDLE := x"00";
323
  signal Pending             : INTERRUPT_BUNDLE := x"00";
324
  signal Wait_for_FSM        : std_logic := '0';
325 210 jshamlet
  signal Wait_for_ISR        : std_logic := '0';
326 169 jshamlet
 
327
begin
328
 
329 224 jshamlet
-------------------------------------------------------------------------------
330
-- Reset & uSec Tick
331
-------------------------------------------------------------------------------
332 185 jshamlet
 
333 224 jshamlet
  CPU_Reset_Sync: process( Clock, PLL_Locked )
334
  begin
335
    if( PLL_Locked = '0' )then
336
      Reset_q                <= Reset_Level;
337
      Reset                  <= Reset_Level;
338
    elsif( rising_edge(Clock) )then
339
      Reset_q                <= not Reset_Level;
340
      Reset                  <= Reset_q;
341
    end if;
342
  end process;
343
 
344
  uSec_Tick_proc: process( Clock, Reset )
345
  begin
346
    if( Reset = Reset_Level )then
347
      uSec_Cntr              <= USEC_DLY;
348
      uSec_Tick              <= '0';
349
    elsif( rising_edge( Clock ) )then
350
      uSec_Cntr              <= uSec_Cntr - 1;
351
      if( or_reduce(uSec_Cntr) = '0' )then
352
        uSec_Cntr            <= USEC_DLY;
353
      end if;
354
      uSec_Tick              <= nor_reduce(uSec_Cntr);
355
    end if;
356
  end process;
357
 
358
  Open8_Bus.Clock            <= Clock;
359
  Open8_Bus.Reset            <= Reset;
360
  Open8_Bus.uSec_Tick        <= uSec_Tick;
361
 
362 169 jshamlet
-------------------------------------------------------------------------------
363 182 jshamlet
-- Address bus selection/generation logic
364 169 jshamlet
-------------------------------------------------------------------------------
365
 
366 185 jshamlet
  Address_Logic: process(CPU_State, Regfile, SubOp, SubOp_p1, Operand1,
367
                         Operand2, Program_Ctr, Stack_Ptr, ISR_Addr )
368 169 jshamlet
    variable Reg, Reg_1      : integer range 0 to 7 := 0;
369
    variable Offset_SX       : ADDRESS_TYPE;
370
  begin
371 182 jshamlet
 
372
    if( Enable_Auto_Increment )then
373
      Reg                    := conv_integer(SubOp(2 downto 1) & '0');
374
      Reg_1                  := conv_integer(SubOp(2 downto 1) & '1');
375
    else
376
      Reg                    := conv_integer(SubOp);
377
      Reg_1                  := conv_integer(SubOp_p1);
378
    end if;
379
 
380
    Offset_SX(15 downto 0)   := (others => Operand1(7));
381
    Offset_SX(7 downto 0)    := Operand1;
382
 
383
    case( CPU_State )is
384
 
385
      when LDA_C2 | STA_C2 =>
386 223 jshamlet
        Open8_Bus.Address    <= Operand2 & Operand1;
387 182 jshamlet
 
388
      when LDX_C1 | STX_C1 =>
389 223 jshamlet
        Open8_Bus.Address    <= (Regfile(Reg_1) & Regfile(Reg));
390 182 jshamlet
 
391
      when LDO_C1 | STO_C1 =>
392 223 jshamlet
        Open8_Bus.Address    <= (Regfile(Reg_1) & Regfile(Reg)) + Offset_SX;
393 182 jshamlet
 
394
      when ISR_C1 | ISR_C2 =>
395 223 jshamlet
        Open8_Bus.Address    <= ISR_Addr;
396 182 jshamlet
 
397
      when PSH_C1 | POP_C1 | ISR_C3 | JSR_C1 | JSR_C2 | RTS_C1 | RTS_C2 | RTS_C3 =>
398 223 jshamlet
        Open8_Bus.Address    <= Stack_Ptr;
399 182 jshamlet
 
400
      when others =>
401 223 jshamlet
        Open8_Bus.Address    <= Program_Ctr;
402 182 jshamlet
 
403
    end case;
404
 
405
  end process;
406
 
407
-------------------------------------------------------------------------------
408
-- Combinatorial portion of CPU finite state machine
409
-- State Logic / Instruction Decoding & Execution
410
-------------------------------------------------------------------------------
411
 
412 187 jshamlet
  State_Logic: process(CPU_State, Flags, Int_Mask, CPU_Halt_Req, Opcode,
413 182 jshamlet
                       SubOp , SubOp_p1, Operand1, Operand2, Int_Req )
414
    variable Reg             : integer range 0 to 7 := 0;
415
  begin
416 169 jshamlet
    CPU_Next_State           <= CPU_State;
417
    Cache_Ctrl               <= CACHE_IDLE;
418
    --
419 185 jshamlet
    PC_Ctrl.Oper             <= PC_INCR;
420
    PC_Ctrl.Offset           <= PC_IDLE;
421 182 jshamlet
    --
422 169 jshamlet
    ALU_Ctrl.Oper            <= ALU_IDLE;
423
    ALU_Ctrl.Reg             <= ACCUM;
424
    --
425
    SP_Ctrl.Oper             <= SP_IDLE;
426
    --
427
    DP_Ctrl.Src              <= DATA_RD_MEM;
428
    DP_Ctrl.Reg              <= ACCUM;
429
    --
430
    INT_Ctrl.Mask_Set        <= '0';
431
    INT_Ctrl.Soft_Ints       <= x"00";
432
    INT_Ctrl.Incr_ISR        <= '0';
433
    Ack_D                    <= '0';
434 225 jshamlet
    --
435 182 jshamlet
    Reg                     := conv_integer(SubOp);
436 225 jshamlet
    --
437
    CPU_Halt_Ack             <= '0';
438 169 jshamlet
 
439
    case CPU_State is
440
-------------------------------------------------------------------------------
441
-- Initial Instruction fetch & decode
442
-------------------------------------------------------------------------------
443 187 jshamlet
      when IPF_C0 =>
444
        CPU_Next_State       <= IPF_C1;
445 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
446 169 jshamlet
 
447 187 jshamlet
      when IPF_C1 =>
448
        CPU_Next_State       <= IPF_C2;
449 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
450 169 jshamlet
 
451 187 jshamlet
      when IPF_C2 =>
452
        CPU_Next_State       <= IDC_C0;
453 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
454 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
455 169 jshamlet
 
456 187 jshamlet
      when IDC_C0 =>
457
        CPU_Next_State       <= IDC_C0;
458 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
459
 
460
        case Opcode is
461
          when OP_PSH =>
462
            CPU_Next_State   <= PSH_C1;
463
            Cache_Ctrl       <= CACHE_PREFETCH;
464 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
465 169 jshamlet
            DP_Ctrl.Src      <= DATA_WR_REG;
466
            DP_Ctrl.Reg      <= SubOp;
467
 
468
          when OP_POP =>
469
            CPU_Next_State   <= POP_C1;
470
            Cache_Ctrl       <= CACHE_PREFETCH;
471 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
472 169 jshamlet
            SP_Ctrl.Oper     <= SP_POP;
473
 
474
          when OP_BR0 | OP_BR1 =>
475
            CPU_Next_State   <= BRN_C1;
476
            Cache_Ctrl       <= CACHE_OPER1;
477 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
478 169 jshamlet
 
479 185 jshamlet
 
480 169 jshamlet
          when OP_DBNZ =>
481
            CPU_Next_State   <= DBNZ_C1;
482
            Cache_Ctrl       <= CACHE_OPER1;
483 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
484 169 jshamlet
            ALU_Ctrl.Oper    <= ALU_DEC;
485
            ALU_Ctrl.Reg     <= SubOp;
486
 
487
          when OP_INT =>
488 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
489 187 jshamlet
            -- Make sure the requested interrupt is actually enabled first.
490
            --  Also, unlike CPU_Halt, the INT instruction is actually being
491
            --  executed, so go ahead and increment the program counter before
492
            --  pausing so the CPU restarts on the next instruction.
493 169 jshamlet
            if( Int_Mask(Reg) = '1' )then
494 187 jshamlet
              CPU_Next_State <= WAI_Cx;
495 169 jshamlet
              INT_Ctrl.Soft_Ints(Reg) <= '1';
496
            end if;
497
 
498
          when OP_STK =>
499
            case SubOp is
500
              when SOP_RSP  =>
501 185 jshamlet
                PC_Ctrl.Offset <= PC_NEXT;
502 181 jshamlet
                if( not Allow_Stack_Address_Move )then
503 187 jshamlet
                  -- The default behavior for this instruction is to simply
504
                  --  repoint the SP to the HDL default
505 185 jshamlet
                  SP_Ctrl.Oper    <= SP_CLR;
506 181 jshamlet
                end if;
507 187 jshamlet
                if( Allow_Stack_Address_Move and
508
                    Flags(Stack_Xfer_Flag) = '1' )then
509
                  -- If RSP is set to allow SP moves, and the specified flag
510
                  --  is true, then signal the stack pointer logic to load
511
                  --  from R1:R0
512 185 jshamlet
                  SP_Ctrl.Oper    <= SP_SET;
513 181 jshamlet
                end if;
514 187 jshamlet
                if( Allow_Stack_Address_Move and
515
                    Flags(Stack_Xfer_Flag) = '0')then
516
                  -- If RSP is set to allow SP moves, and the specified flag
517
                  --  is false, then signal the ALU to copy the stack pointer
518
                  --  to R1:R0
519 185 jshamlet
                  ALU_Ctrl.Oper   <= ALU_RSP;
520 181 jshamlet
                end if;
521 169 jshamlet
 
522
              when SOP_RTS | SOP_RTI =>
523 185 jshamlet
                CPU_Next_State    <= RTS_C1;
524 190 jshamlet
                Cache_Ctrl        <= CACHE_IDLE;
525 185 jshamlet
                SP_Ctrl.Oper      <= SP_POP;
526 169 jshamlet
 
527
              when SOP_BRK  =>
528
                if( BRK_Implements_WAI )then
529 187 jshamlet
                  -- If BRK_Implements_WAI, then jump to the WAI_Cx and
530
                  --  increment the PC similar to an ISR flow.
531
                  CPU_Next_State  <= WAI_Cx;
532 185 jshamlet
                  PC_Ctrl.Offset  <= PC_NEXT;
533 187 jshamlet
                else
534
                -- If Break is implemented normally, back the PC up by
535
                --  2 and return through IPF_C0 in order to execute a 5
536
                --  clock cycle delay
537
                  CPU_Next_State  <= BRK_C1;
538
                  PC_Ctrl.Offset  <= PC_REV2;
539 169 jshamlet
                end if;
540
 
541
              when SOP_JMP  =>
542 185 jshamlet
                CPU_Next_State    <= JMP_C1;
543
                Cache_Ctrl        <= CACHE_OPER1;
544 169 jshamlet
 
545
              when SOP_SMSK =>
546 185 jshamlet
                PC_Ctrl.Offset    <= PC_NEXT;
547 169 jshamlet
                INT_Ctrl.Mask_Set <= '1';
548
 
549
              when SOP_GMSK =>
550 185 jshamlet
                PC_Ctrl.Offset    <= PC_NEXT;
551
                ALU_Ctrl.Oper     <= ALU_GMSK;
552 169 jshamlet
 
553
              when SOP_JSR =>
554
                CPU_Next_State <= JSR_C1;
555 185 jshamlet
                Cache_Ctrl        <= CACHE_OPER1;
556
                DP_Ctrl.Src       <= DATA_WR_PC;
557
                DP_Ctrl.Reg       <= PC_MSB;
558 169 jshamlet
 
559
              when others => null;
560
            end case;
561
 
562
          when OP_MUL =>
563
            CPU_Next_State   <= MUL_C1;
564 181 jshamlet
            -- Multiplication requires a single clock cycle to calculate PRIOR
565
            --  to the ALU writing the result to registers. As a result, this
566
            --  state needs to idle the ALU initially, and back the PC up by 1
567
            -- We can get away with only 1 extra clock by pre-fetching the
568
            --  next instruction, though.
569 169 jshamlet
            Cache_Ctrl       <= CACHE_PREFETCH;
570 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
571 181 jshamlet
            -- Note that both the multiply process AND ALU process need the
572
            --  source register for Rn (R1:R0 = R0 * Rn). Assert ALU_Ctrl.reg
573
            --  now, but hold off on the ALU command until the next state.
574 169 jshamlet
            ALU_Ctrl.Oper    <= ALU_IDLE;
575
            ALU_Ctrl.Reg     <= SubOp;
576
 
577
          when OP_UPP =>
578
            CPU_Next_State   <= UPP_C1;
579
            Cache_Ctrl       <= CACHE_PREFETCH;
580 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
581 169 jshamlet
            ALU_Ctrl.Oper    <= Opcode;
582
            ALU_Ctrl.Reg     <= SubOp;
583
 
584
          when OP_LDA =>
585
            CPU_Next_State   <= LDA_C1;
586
            Cache_Ctrl       <= CACHE_OPER1;
587
 
588
          when OP_LDI =>
589
            CPU_Next_State   <= LDI_C1;
590
            Cache_Ctrl       <= CACHE_OPER1;
591 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
592 169 jshamlet
 
593
          when OP_LDO =>
594
            CPU_Next_State   <= LDO_C1;
595
            Cache_Ctrl       <= CACHE_OPER1;
596 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
597 169 jshamlet
 
598
          when OP_LDX =>
599
            CPU_Next_State   <= LDX_C1;
600 181 jshamlet
            Cache_Ctrl       <= CACHE_PREFETCH;
601 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
602 169 jshamlet
 
603
          when OP_STA =>
604
            CPU_Next_State   <= STA_C1;
605
            Cache_Ctrl       <= CACHE_OPER1;
606
 
607
          when OP_STO =>
608
            CPU_Next_State   <= STO_C1;
609
            Cache_Ctrl       <= CACHE_OPER1;
610 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
611 169 jshamlet
            DP_Ctrl.Src      <= DATA_WR_REG;
612
            DP_Ctrl.Reg      <= ACCUM;
613
 
614
          when OP_STX =>
615
            CPU_Next_State   <= STX_C1;
616
            Cache_Ctrl       <= CACHE_PREFETCH;
617 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
618 169 jshamlet
            DP_Ctrl.Src      <= DATA_WR_REG;
619
            DP_Ctrl.Reg      <= ACCUM;
620
 
621 244 jshamlet
          when OP_STP =>
622
            PC_Ctrl.Offset   <= PC_NEXT;
623
            if( Supervisor_Mode )then
624
              if( SubOp /= PSR_I )then
625
                ALU_Ctrl.Oper  <= Opcode;
626
                ALU_Ctrl.Reg   <= SubOp;
627
              end if;
628
            else
629
              ALU_Ctrl.Oper  <= Opcode;
630
              ALU_Ctrl.Reg   <= SubOp;
631
            end if;
632
 
633 169 jshamlet
          when others =>
634 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
635 169 jshamlet
            ALU_Ctrl.Oper    <= Opcode;
636
            ALU_Ctrl.Reg     <= SubOp;
637
 
638
        end case;
639
 
640 186 jshamlet
        if( Int_Req = '1' )then
641
          CPU_Next_State     <= ISR_C1;
642 187 jshamlet
        end if;
643
 
644
        if( CPU_Halt_Req = '1' )then
645
          CPU_Next_State     <= WAH_Cx;
646
        end if;
647
 
648
        -- If either of these override conditions are true, the decoder needs
649
        --  to undo everything it just setup, since even "single-cycle"
650
        --  instructions will be executed again upon return.
651
        if( Int_Req = '1' or CPU_Halt_Req = '1' )then
652
          -- In either case, we want to skip loading the cache, as the cache
653
          --  will be invalid by the time we get back.
654 186 jshamlet
          Cache_Ctrl         <= CACHE_IDLE;
655 187 jshamlet
          -- Rewind the PC by 3 to put the PC back to the current instruction,
656
          -- compensating for the pipeline registers.
657 186 jshamlet
          PC_Ctrl.Offset     <= PC_REV3;
658
          -- Reset all of the sub-block controls to IDLE, to avoid unintended
659 187 jshamlet
          --  operation due to the current instruction.
660 186 jshamlet
          ALU_Ctrl.Oper      <= ALU_IDLE;
661
          SP_Ctrl.Oper       <= SP_IDLE;
662 187 jshamlet
          -- Interrupt logic outside of the state machine needs this to be set
663
          --  to DATA_RD_MEM, while CPU_Halt considers this a "don't care".
664 186 jshamlet
          DP_Ctrl.Src        <= DATA_RD_MEM;
665 187 jshamlet
          -- If an INT/SMSK instruction was going to be executed, it will get
666
          --  executed again when normal processing resumes, so axe their
667
          --  requests for now.
668
          INT_Ctrl.Mask_Set       <= '0';
669
          INT_Ctrl.Soft_Ints(Reg) <= '0';
670 186 jshamlet
        end if;
671
 
672 169 jshamlet
-------------------------------------------------------------------------------
673
-- Program Control (BR0_C1, BR1_C1, DBNZ_C1, JMP )
674
-------------------------------------------------------------------------------
675
 
676
      when BRN_C1 =>
677 187 jshamlet
        CPU_Next_State       <= IDC_C0;
678 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
679 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
680 169 jshamlet
        if( Flags(Reg) = Opcode(0) )then
681 187 jshamlet
          CPU_Next_State     <= IPF_C0;
682 169 jshamlet
          Cache_Ctrl         <= CACHE_IDLE;
683
          PC_Ctrl.Offset     <= Operand1;
684
        end if;
685
 
686
      when DBNZ_C1 =>
687 187 jshamlet
        CPU_Next_State       <= IDC_C0;
688 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
689 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
690
        if( Flags(PSR_Z) = '0' )then
691 187 jshamlet
          CPU_Next_State     <= IPF_C0;
692 169 jshamlet
          Cache_Ctrl         <= CACHE_IDLE;
693
          PC_Ctrl.Offset     <= Operand1;
694
        end if;
695
 
696
      when JMP_C1 =>
697
        CPU_Next_State       <= JMP_C2;
698
        Cache_Ctrl           <= CACHE_OPER2;
699
 
700
      when JMP_C2 =>
701 187 jshamlet
        CPU_Next_State       <= IPF_C0;
702 169 jshamlet
        PC_Ctrl.Oper         <= PC_LOAD;
703
 
704
-------------------------------------------------------------------------------
705
-- Data Storage - Load from memory (LDA, LDI, LDO, LDX)
706
-------------------------------------------------------------------------------
707
 
708
      when LDA_C1 =>
709
        CPU_Next_State       <= LDA_C2;
710
        Cache_Ctrl           <= CACHE_OPER2;
711
 
712
      when LDA_C2 =>
713
        CPU_Next_State       <= LDA_C3;
714
 
715
      when LDA_C3 =>
716
        CPU_Next_State       <= LDA_C4;
717 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
718 169 jshamlet
 
719
      when LDA_C4 =>
720
        CPU_Next_State       <= LDI_C1;
721
        Cache_Ctrl           <= CACHE_OPER1;
722 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
723 169 jshamlet
 
724
      when LDI_C1 =>
725 187 jshamlet
        CPU_Next_State       <= IDC_C0;
726 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
727 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
728 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_LDI;
729
        ALU_Ctrl.Reg         <= SubOp;
730
 
731
      when LDO_C1 =>
732 181 jshamlet
        CPU_Next_State       <= LDX_C2;
733 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
734 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
735
          ALU_Ctrl.Oper      <= ALU_UPP;
736
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
737 169 jshamlet
        end if;
738
 
739
      when LDX_C1 =>
740
        CPU_Next_State       <= LDX_C2;
741 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
742
          ALU_Ctrl.Oper      <= ALU_UPP;
743
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
744 181 jshamlet
        end if;
745 169 jshamlet
 
746
      when LDX_C2 =>
747
        CPU_Next_State       <= LDX_C3;
748 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
749 181 jshamlet
 
750
      when LDX_C3 =>
751
        CPU_Next_State       <= LDX_C4;
752 182 jshamlet
        Cache_Ctrl           <= CACHE_OPER1;
753 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
754 169 jshamlet
 
755 181 jshamlet
      when LDX_C4 =>
756 187 jshamlet
        CPU_Next_State       <= IDC_C0;
757 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
758 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
759 181 jshamlet
        ALU_Ctrl.Oper        <= ALU_LDI;
760 169 jshamlet
        ALU_Ctrl.Reg         <= ACCUM;
761
 
762
-------------------------------------------------------------------------------
763
-- Data Storage - Store to memory (STA, STO, STX)
764
-------------------------------------------------------------------------------
765
      when STA_C1 =>
766
        CPU_Next_State       <= STA_C2;
767
        Cache_Ctrl           <= CACHE_OPER2;
768
        DP_Ctrl.Src          <= DATA_WR_REG;
769
        DP_Ctrl.Reg          <= SubOp;
770
 
771
      when STA_C2 =>
772
        CPU_Next_State       <= STA_C3;
773 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
774 169 jshamlet
 
775
      when STA_C3 =>
776 187 jshamlet
        CPU_Next_State       <= IPF_C2;
777 169 jshamlet
        Cache_Ctrl           <= CACHE_PREFETCH;
778 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
779 169 jshamlet
 
780
      when STO_C1 =>
781 187 jshamlet
        CPU_Next_State       <= IPF_C0;
782 169 jshamlet
        Cache_Ctrl           <= CACHE_PREFETCH;
783 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
784 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
785
          CPU_Next_State     <= STO_C2;
786
          ALU_Ctrl.Oper      <= ALU_UPP;
787
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
788 169 jshamlet
        end if;
789
 
790
      when STO_C2 =>
791 187 jshamlet
        CPU_Next_State       <= IPF_C1;
792 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
793 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_UPP2;
794
        ALU_Ctrl.Reg         <= SubOp(2 downto 1) & '1';
795
 
796
      when STX_C1 =>
797 187 jshamlet
        CPU_Next_State       <= IPF_C1;
798 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
799 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
800
          CPU_Next_State     <= STX_C2;
801
          ALU_Ctrl.Oper      <= ALU_UPP;
802
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
803 169 jshamlet
        end if;
804
 
805
      when STX_C2 =>
806 187 jshamlet
        CPU_Next_State       <= IPF_C2;
807 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
808 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_UPP2;
809
        ALU_Ctrl.Reg         <= SubOp(2 downto 1) & '1';
810
 
811
-------------------------------------------------------------------------------
812
-- Multi-Cycle Math Operations (UPP, MUL)
813
-------------------------------------------------------------------------------
814
 
815
      -- Because we have to backup the pipeline by 1 to refetch the 2nd
816 181 jshamlet
      --  instruction/first operand, we have to return through PF2. Also, we
817
      --  need to tell the ALU to store the results to R1:R0 here. Note that
818
      --  there is no ALU_Ctrl.Reg, as this is implied in the ALU instruction
819 169 jshamlet
      when MUL_C1 =>
820 187 jshamlet
        CPU_Next_State       <= IPF_C2;
821 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
822 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_MUL;
823
 
824
      when UPP_C1 =>
825 187 jshamlet
        CPU_Next_State       <= IPF_C2;
826 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
827 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_UPP2;
828
        ALU_Ctrl.Reg         <= SubOp_p1;
829
 
830
-------------------------------------------------------------------------------
831
-- Basic Stack Manipulation (PSH, POP, RSP)
832
-------------------------------------------------------------------------------
833
      when PSH_C1 =>
834 187 jshamlet
        CPU_Next_State       <= IPF_C1;
835 169 jshamlet
        SP_Ctrl.Oper         <= SP_PUSH;
836
 
837
      when POP_C1 =>
838
        CPU_Next_State       <= POP_C2;
839
 
840
      when POP_C2 =>
841
        CPU_Next_State       <= POP_C3;
842 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
843 169 jshamlet
 
844
      when POP_C3 =>
845
        CPU_Next_State       <= POP_C4;
846
        Cache_Ctrl           <= CACHE_OPER1;
847 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
848 169 jshamlet
 
849
      when POP_C4 =>
850 187 jshamlet
        CPU_Next_State       <= IDC_C0;
851 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
852 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
853 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_POP;
854
        ALU_Ctrl.Reg         <= SubOp;
855 172 jshamlet
 
856 169 jshamlet
-------------------------------------------------------------------------------
857
-- Subroutines & Interrupts (RTS, JSR)
858
-------------------------------------------------------------------------------
859 187 jshamlet
      when WAI_Cx => -- For soft interrupts only, halt the Program_Ctr
860 169 jshamlet
        DP_Ctrl.Src          <= DATA_BUS_IDLE;
861 186 jshamlet
        if( Int_Req = '1' )then
862
          CPU_Next_State     <= ISR_C1;
863 187 jshamlet
          -- Rewind the PC by 3 to put the PC back to would have been the next
864
          --  instruction, compensating for the pipeline registers.
865 186 jshamlet
          PC_Ctrl.Offset     <= PC_REV3;
866
          -- Reset all of the sub-block controls to IDLE, to avoid unintended
867
          --  operation due to the current instruction
868
          DP_Ctrl.Src        <= DATA_RD_MEM;
869
        end if;
870 169 jshamlet
 
871 187 jshamlet
      when WAH_Cx => -- Holds until CPU_Halt_Req is deasserted.
872 225 jshamlet
        CPU_Halt_Ack         <= '1';
873 187 jshamlet
        DP_Ctrl.Src          <= DATA_BUS_IDLE;
874
        if( CPU_Halt_Req = '0' )then
875
          CPU_Next_State     <= IPF_C0;
876
          DP_Ctrl.Src        <= DATA_RD_MEM;
877
        end if;
878
 
879
      when BRK_C1 => -- Debugging (BRK) Performs a 5-clock NOP.
880
        CPU_Next_State       <= IPF_C0;
881
 
882 169 jshamlet
      when ISR_C1 =>
883
        CPU_Next_State       <= ISR_C2;
884
        INT_Ctrl.Incr_ISR    <= '1';
885
 
886
      when ISR_C2 =>
887
        CPU_Next_State       <= ISR_C3;
888
        DP_Ctrl.Src          <= DATA_WR_FLAG;
889
 
890
      when ISR_C3 =>
891
        CPU_Next_State       <= JSR_C1;
892
        Cache_Ctrl           <= CACHE_OPER1;
893 182 jshamlet
        ALU_Ctrl.Oper        <= ALU_STP;
894 185 jshamlet
        ALU_Ctrl.Reg         <= conv_std_logic_vector(PSR_I,3);
895 169 jshamlet
        SP_Ctrl.Oper         <= SP_PUSH;
896
        DP_Ctrl.Src          <= DATA_WR_PC;
897 182 jshamlet
        DP_Ctrl.Reg          <= PC_MSB;
898 169 jshamlet
        Ack_D                <= '1';
899
 
900
      when JSR_C1 =>
901
        CPU_Next_State       <= JSR_C2;
902
        Cache_Ctrl           <= CACHE_OPER2;
903
        SP_Ctrl.Oper         <= SP_PUSH;
904
        DP_Ctrl.Src          <= DATA_WR_PC;
905 182 jshamlet
        DP_Ctrl.Reg          <= PC_LSB;
906 169 jshamlet
 
907
      when JSR_C2 =>
908 187 jshamlet
        CPU_Next_State       <= IPF_C0;
909 169 jshamlet
        PC_Ctrl.Oper         <= PC_LOAD;
910 182 jshamlet
        SP_Ctrl.Oper         <= SP_PUSH;
911 169 jshamlet
 
912
      when RTS_C1 =>
913
        CPU_Next_State       <= RTS_C2;
914
        SP_Ctrl.Oper         <= SP_POP;
915
 
916
      when RTS_C2 =>
917
        CPU_Next_State       <= RTS_C3;
918
        -- if this is an RTI, then we need to POP the flags
919
        if( SubOp = SOP_RTI )then
920
          SP_Ctrl.Oper       <= SP_POP;
921
        end if;
922
 
923
      when RTS_C3 =>
924
        CPU_Next_State       <= RTS_C4;
925
        Cache_Ctrl           <= CACHE_OPER1;
926
 
927
      when RTS_C4 =>
928
        CPU_Next_State       <= RTS_C5;
929
        Cache_Ctrl           <= CACHE_OPER2;
930
 
931
      when RTS_C5 =>
932 187 jshamlet
        CPU_Next_State       <= IPF_C0;
933 169 jshamlet
        PC_Ctrl.Oper         <= PC_LOAD;
934 185 jshamlet
        -- if this is an RTI, then we need to clear the I bit
935 169 jshamlet
        if( SubOp = SOP_RTI )then
936
          CPU_Next_State     <= RTI_C6;
937
          Cache_Ctrl         <= CACHE_OPER1;
938 185 jshamlet
          ALU_Ctrl.Oper      <= ALU_CLP;
939
          ALU_Ctrl.Reg       <= conv_std_logic_vector(PSR_I,3);
940 169 jshamlet
        end if;
941
 
942
      when RTI_C6 =>
943 187 jshamlet
        CPU_Next_State       <= IPF_C1;
944 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
945 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_RFLG;
946
 
947
      when others =>
948
        null;
949
    end case;
950
 
951
  end process;
952
 
953
-------------------------------------------------------------------------------
954
-- Registered portion of CPU finite state machine
955
-------------------------------------------------------------------------------
956 182 jshamlet
 
957 169 jshamlet
  CPU_Regs: process( Reset, Clock )
958
    variable Offset_SX       : ADDRESS_TYPE;
959 188 jshamlet
    variable i_Ints          : INTERRUPT_BUNDLE := x"00";
960 169 jshamlet
    variable Index           : integer range 0 to 7         := 0;
961
    variable Sum             : std_logic_vector(8 downto 0) := "000000000";
962
    variable Temp            : std_logic_vector(8 downto 0) := "000000000";
963
  begin
964
    if( Reset = Reset_Level )then
965 187 jshamlet
      CPU_State              <= IPF_C0;
966 169 jshamlet
      Opcode                 <= OP_INC;
967
      SubOp                  <= ACCUM;
968
      SubOp_p1               <= ACCUM;
969
      Operand1               <= x"00";
970
      Operand2               <= x"00";
971
      Instr_Prefetch         <= '0';
972
      Prefetch               <= x"00";
973
 
974 187 jshamlet
      CPU_Halt_Req           <= '0';
975 225 jshamlet
      Halt_Ack               <= '0';
976 187 jshamlet
 
977 223 jshamlet
      Open8_Bus.Wr_En        <= '0';
978
      Open8_Bus.Wr_Data      <= OPEN8_NULLBUS;
979
      Open8_Bus.Rd_En        <= '1';
980 169 jshamlet
 
981
      Program_Ctr            <= Program_Start_Addr;
982
      Stack_Ptr              <= Stack_Start_Addr;
983
 
984
      Ack_Q                  <= '0';
985
      Ack_Q1                 <= '0';
986
      Int_Ack                <= '0';
987
 
988
      Int_Req                <= '0';
989
      Pending                <= x"00";
990
      Wait_for_FSM           <= '0';
991 210 jshamlet
      Wait_for_ISR           <= '0';
992 169 jshamlet
      if( Enable_NMI )then
993
        Int_Mask             <= Default_Interrupt_Mask(7 downto 1) & '1';
994
      else
995
        Int_Mask             <= Default_Interrupt_Mask;
996
      end if;
997
      ISR_Addr               <= INT_VECTOR_0;
998
 
999
      for i in 0 to 7 loop
1000 188 jshamlet
        Regfile(i)           <= x"00";
1001 169 jshamlet
      end loop;
1002
      Flags                  <= x"00";
1003 244 jshamlet
      if( Default_Int_Flag )then
1004
        Flags(PSR_I)         <= '1';
1005
      end if;
1006 169 jshamlet
 
1007 224 jshamlet
      Open8_Bus.GP_Flags     <= (others => '0');
1008 188 jshamlet
 
1009 169 jshamlet
    elsif( rising_edge(Clock) )then
1010 187 jshamlet
 
1011 225 jshamlet
      CPU_Halt_Req           <= Halt_Req;
1012
      Halt_Ack               <= CPU_Halt_Ack;
1013 187 jshamlet
 
1014 223 jshamlet
      Open8_Bus.Wr_En        <= '0';
1015
      Open8_Bus.Wr_Data      <= OPEN8_NULLBUS;
1016
      Open8_Bus.Rd_En        <= '0';
1017 169 jshamlet
 
1018
-------------------------------------------------------------------------------
1019
-- Instruction/Operand caching for pipelined memory access
1020
-------------------------------------------------------------------------------
1021
      CPU_State              <= CPU_Next_State;
1022
      case Cache_Ctrl is
1023
        when CACHE_INSTR =>
1024
          Opcode             <= Rd_Data(7 downto 3);
1025
          SubOp              <= Rd_Data(2 downto 0);
1026
          SubOp_p1           <= Rd_Data(2 downto 0) + 1;
1027
          if( Instr_Prefetch = '1' )then
1028
            Opcode           <= Prefetch(7 downto 3);
1029
            SubOp            <= Prefetch(2 downto 0);
1030
            SubOp_p1         <= Prefetch(2 downto 0) + 1;
1031
            Instr_Prefetch   <= '0';
1032
          end if;
1033
 
1034
        when CACHE_OPER1 =>
1035
          Operand1           <= Rd_Data;
1036
 
1037
        when CACHE_OPER2 =>
1038
          Operand2           <= Rd_Data;
1039
 
1040
        when CACHE_PREFETCH =>
1041
          Prefetch           <= Rd_Data;
1042
          Instr_Prefetch     <= '1';
1043
 
1044
        when CACHE_IDLE =>
1045
          null;
1046
      end case;
1047
 
1048
-------------------------------------------------------------------------------
1049
-- Program Counter
1050
-------------------------------------------------------------------------------
1051
      Offset_SX(15 downto 8) := (others => PC_Ctrl.Offset(7));
1052
      Offset_SX(7 downto 0)  := PC_Ctrl.Offset;
1053
 
1054
      case PC_Ctrl.Oper is
1055
        when PC_INCR =>
1056
          Program_Ctr        <= Program_Ctr + Offset_SX - 2;
1057
 
1058
        when PC_LOAD =>
1059 185 jshamlet
          Program_Ctr        <= Operand2 & Operand1;
1060 169 jshamlet
 
1061
        when others =>
1062
          null;
1063
      end case;
1064
 
1065
-------------------------------------------------------------------------------
1066
-- (Write) Data Path
1067
-------------------------------------------------------------------------------
1068
      case DP_Ctrl.Src is
1069
        when DATA_BUS_IDLE =>
1070
          null;
1071
 
1072
        when DATA_RD_MEM =>
1073 223 jshamlet
          Open8_Bus.Rd_En    <= '1';
1074 169 jshamlet
 
1075
        when DATA_WR_REG =>
1076 223 jshamlet
          Open8_Bus.Wr_En    <= '1';
1077
          Open8_Bus.Wr_Data  <= Regfile(conv_integer(DP_Ctrl.Reg));
1078 169 jshamlet
 
1079
        when DATA_WR_FLAG =>
1080 223 jshamlet
          Open8_Bus.Wr_En    <= '1';
1081
          Open8_Bus.Wr_Data  <= Flags;
1082 169 jshamlet
 
1083
        when DATA_WR_PC =>
1084 223 jshamlet
          Open8_Bus.Wr_En    <= '1';
1085
          Open8_Bus.Wr_Data  <= Program_Ctr(15 downto 8);
1086 182 jshamlet
          if( DP_Ctrl.Reg = PC_LSB )then
1087 223 jshamlet
            Open8_Bus.Wr_Data <= Program_Ctr(7 downto 0);
1088 169 jshamlet
          end if;
1089
 
1090
        when others =>
1091
          null;
1092
      end case;
1093
 
1094
-------------------------------------------------------------------------------
1095
-- Stack Pointer
1096
-------------------------------------------------------------------------------
1097
      case SP_Ctrl.Oper is
1098
        when SP_IDLE =>
1099
          null;
1100
 
1101 181 jshamlet
        when SP_CLR =>
1102 169 jshamlet
          Stack_Ptr          <= Stack_Start_Addr;
1103
 
1104 181 jshamlet
        when SP_SET =>
1105
          Stack_Ptr          <= Regfile(1) & Regfile(0);
1106
 
1107 169 jshamlet
        when SP_POP  =>
1108
          Stack_Ptr          <= Stack_Ptr + 1;
1109
 
1110
        when SP_PUSH =>
1111
          Stack_Ptr          <= Stack_Ptr - 1;
1112
 
1113
        when others =>
1114
          null;
1115
 
1116
      end case;
1117
 
1118
-------------------------------------------------------------------------------
1119
-- Interrupt Controller
1120
-------------------------------------------------------------------------------
1121
      -- The interrupt control mask is always sourced out of R0
1122
      if( INT_Ctrl.Mask_Set = '1' )then
1123
        if( Enable_NMI )then
1124
          Int_Mask           <= Regfile(conv_integer(ACCUM))(7 downto 1) & '1';
1125
        else
1126
          Int_Mask           <= Regfile(conv_integer(ACCUM));
1127
        end if;
1128
      end if;
1129
 
1130
      -- Combine external and internal interrupts, and mask the OR of the two
1131
      --  with the mask. Record any incoming interrupts to the pending buffer
1132
      i_Ints                 := (Interrupts or INT_Ctrl.Soft_Ints) and
1133
                                Int_Mask;
1134 172 jshamlet
 
1135 169 jshamlet
      Pending                <= i_Ints or Pending;
1136
 
1137 210 jshamlet
      if( Sequential_Interrupts )then
1138
        Wait_for_ISR         <= Flags(PSR_I);
1139
      else
1140
        Wait_for_ISR         <= '0';
1141
      end if;
1142
 
1143
      if( Wait_for_FSM = '0' and Wait_for_ISR = '0' )then
1144 169 jshamlet
        if(    Pending(0) = '1' )then
1145
          ISR_Addr           <= INT_VECTOR_0;
1146
          Pending(0)         <= '0';
1147
        elsif( Pending(1) = '1' )then
1148
          ISR_Addr           <= INT_VECTOR_1;
1149
          Pending(1)         <= '0';
1150
        elsif( Pending(2) = '1' )then
1151
          ISR_Addr           <= INT_VECTOR_2;
1152
          Pending(2)         <= '0';
1153
        elsif( Pending(3) = '1' )then
1154
          ISR_Addr           <= INT_VECTOR_3;
1155
          Pending(3)         <= '0';
1156
        elsif( Pending(4) = '1' )then
1157
          ISR_Addr           <= INT_VECTOR_4;
1158
          Pending(4)         <= '0';
1159
        elsif( Pending(5) = '1' )then
1160
          ISR_Addr           <= INT_VECTOR_5;
1161
          Pending(5)         <= '0';
1162
        elsif( Pending(6) = '1' )then
1163
          ISR_Addr           <= INT_VECTOR_6;
1164
          Pending(6)         <= '0';
1165
        elsif( Pending(7) = '1' )then
1166
          ISR_Addr           <= INT_VECTOR_7;
1167
          Pending(7)         <= '0';
1168
        end if;
1169 185 jshamlet
        Wait_for_FSM         <= or_reduce(Pending);
1170 169 jshamlet
      end if;
1171
 
1172
      -- Reset the Wait_for_FSM flag on Int_Ack
1173
      Ack_Q                  <= Ack_D;
1174
      Ack_Q1                 <= Ack_Q;
1175
      Int_Ack                <= Ack_Q1;
1176
      if( Int_Ack = '1' )then
1177
        Wait_for_FSM         <= '0';
1178
      end if;
1179
 
1180
      Int_Req                <= Wait_for_FSM and (not Int_Ack);
1181
 
1182
      -- Incr_ISR allows the CPU Core to advance the vector address to pop the
1183
      --  lower half of the address.
1184
      if( INT_Ctrl.Incr_ISR = '1' )then
1185
        ISR_Addr             <= ISR_Addr + 1;
1186
      end if;
1187
 
1188
-------------------------------------------------------------------------------
1189
-- ALU (Arithmetic / Logic Unit)
1190
-------------------------------------------------------------------------------
1191
      Index                  := conv_integer(ALU_Ctrl.Reg);
1192
      Sum                    := (others => '0');
1193
      Temp                   := (others => '0');
1194
 
1195
      case ALU_Ctrl.Oper is
1196
        when ALU_INC => -- Rn = Rn + 1 : Flags N,C,Z
1197
          Sum                := ("0" & x"01") +
1198
                                ("0" & Regfile(Index));
1199 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1200
          Flags(PSR_C)       <= Sum(8);
1201 209 jshamlet
          Flags(PSR_N)       <= Sum(7);
1202 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1203
 
1204
        when ALU_UPP => -- Rn = Rn + 1
1205
          Sum                := ("0" & x"01") +
1206
                                ("0" & Regfile(Index));
1207 185 jshamlet
          Flags(PSR_C)       <= Sum(8);
1208 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1209
 
1210
        when ALU_UPP2 => -- Rn = Rn + C
1211
          Sum                := ("0" & x"00") +
1212
                                ("0" & Regfile(Index)) +
1213 185 jshamlet
                                Flags(PSR_C);
1214
          Flags(PSR_C)       <= Sum(8);
1215 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1216
 
1217
        when ALU_ADC => -- R0 = R0 + Rn + C : Flags N,C,Z
1218
          Sum                := ("0" & Regfile(0)) +
1219
                                ("0" & Regfile(Index)) +
1220 185 jshamlet
                                Flags(PSR_C);
1221
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1222
          Flags(PSR_C)       <= Sum(8);
1223
          Flags(PSR_N)       <= Sum(7);
1224 169 jshamlet
          Regfile(0)         <= Sum(7 downto 0);
1225
 
1226
        when ALU_TX0 => -- R0 = Rn : Flags N,Z
1227
          Temp               := "0" & Regfile(Index);
1228 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1229
          Flags(PSR_N)       <= Temp(7);
1230 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1231
 
1232
        when ALU_OR  => -- R0 = R0 | Rn : Flags N,Z
1233
          Temp(7 downto 0)   := Regfile(0) or Regfile(Index);
1234 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1235
          Flags(PSR_N)       <= Temp(7);
1236 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1237
 
1238
        when ALU_AND => -- R0 = R0 & Rn : Flags N,Z
1239
          Temp(7 downto 0)   := Regfile(0) and Regfile(Index);
1240 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1241
          Flags(PSR_N)       <= Temp(7);
1242 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1243
 
1244
        when ALU_XOR => -- R0 = R0 ^ Rn : Flags N,Z
1245
          Temp(7 downto 0)   := Regfile(0) xor Regfile(Index);
1246 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1247
          Flags(PSR_N)       <= Temp(7);
1248 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1249
 
1250
        when ALU_ROL => -- Rn = Rn<<1,C : Flags N,C,Z
1251 185 jshamlet
          Temp               := Regfile(Index) & Flags(PSR_C);
1252
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1253
          Flags(PSR_C)       <= Temp(8);
1254
          Flags(PSR_N)       <= Temp(7);
1255 169 jshamlet
          Regfile(Index)     <= Temp(7 downto 0);
1256
 
1257
        when ALU_ROR => -- Rn = C,Rn>>1 : Flags N,C,Z
1258 185 jshamlet
          Temp               := Regfile(Index)(0) & Flags(PSR_C) &
1259 169 jshamlet
                                Regfile(Index)(7 downto 1);
1260 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1261
          Flags(PSR_C)       <= Temp(8);
1262
          Flags(PSR_N)       <= Temp(7);
1263 169 jshamlet
          Regfile(Index)     <= Temp(7 downto 0);
1264
 
1265
        when ALU_DEC => -- Rn = Rn - 1 : Flags N,C,Z
1266
          Sum                := ("0" & Regfile(Index)) +
1267
                                ("0" & x"FF");
1268 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1269
          Flags(PSR_C)       <= Sum(8);
1270
          Flags(PSR_N)       <= Sum(7);
1271 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1272
 
1273
        when ALU_SBC => -- Rn = R0 - Rn - C : Flags N,C,Z
1274
          Sum                := ("0" & Regfile(0)) +
1275
                                ("1" & (not Regfile(Index))) +
1276 185 jshamlet
                                Flags(PSR_C);
1277
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1278
          Flags(PSR_C)       <= Sum(8);
1279
          Flags(PSR_N)       <= Sum(7);
1280 169 jshamlet
          Regfile(0)         <= Sum(7 downto 0);
1281
 
1282
        when ALU_ADD => -- R0 = R0 + Rn : Flags N,C,Z
1283
          Sum                := ("0" & Regfile(0)) +
1284
                                ("0" & Regfile(Index));
1285 185 jshamlet
          Flags(PSR_C)       <= Sum(8);
1286 169 jshamlet
          Regfile(0)         <= Sum(7 downto 0);
1287 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1288
          Flags(PSR_N)       <= Sum(7);
1289 169 jshamlet
 
1290
        when ALU_STP => -- Sets bit(n) in the Flags register
1291
          Flags(Index)       <= '1';
1292
 
1293
        when ALU_BTT => -- Z = !R0(N), N = R0(7)
1294 185 jshamlet
          Flags(PSR_Z)       <= not Regfile(0)(Index);
1295
          Flags(PSR_N)       <= Regfile(0)(7);
1296 169 jshamlet
 
1297
        when ALU_CLP => -- Clears bit(n) in the Flags register
1298
          Flags(Index)       <= '0';
1299
 
1300
        when ALU_T0X => -- Rn = R0 : Flags N,Z
1301
          Temp               := "0" & Regfile(0);
1302 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1303
          Flags(PSR_N)       <= Temp(7);
1304 169 jshamlet
          Regfile(Index)     <= Temp(7 downto 0);
1305
 
1306
        when ALU_CMP => -- Sets Flags on R0 - Rn : Flags N,C,Z
1307
          Sum                := ("0" & Regfile(0)) +
1308
                                ("1" & (not Regfile(Index))) +
1309
                                '1';
1310 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1311
          Flags(PSR_C)       <= Sum(8);
1312
          Flags(PSR_N)       <= Sum(7);
1313 169 jshamlet
 
1314
        when ALU_MUL => -- Stage 1 of 2 {R1:R0} = R0 * Rn : Flags Z
1315
          Regfile(0)         <= Mult(7 downto 0);
1316
          Regfile(1)         <= Mult(15 downto 8);
1317 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Mult);
1318 169 jshamlet
 
1319
        when ALU_LDI => -- Rn <= Data : Flags N,Z
1320 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Operand1);
1321
          Flags(PSR_N)       <= Operand1(7);
1322
          Regfile(Index)     <= Operand1;
1323 169 jshamlet
 
1324
        when ALU_POP => -- Rn <= Data
1325 185 jshamlet
          Regfile(Index)     <= Operand1;
1326 169 jshamlet
 
1327
        when ALU_RFLG =>
1328 188 jshamlet
          Flags(3 downto 0)  <= Operand1(3 downto 0);
1329
          if( not RTI_Ignores_GP_Flags )then
1330
            Flags(7 downto 4)<= Operand1(7 downto 4);
1331
          end if;
1332 169 jshamlet
 
1333 185 jshamlet
        when ALU_RSP =>
1334 181 jshamlet
          Regfile(0)         <= Stack_Ptr(7 downto 0);
1335
          Regfile(1)         <= Stack_Ptr(15 downto 8);
1336
 
1337 185 jshamlet
        when ALU_GMSK =>
1338
          Flags(PSR_Z)       <= nor_reduce(Int_Mask);
1339
          Regfile(0)         <= Int_Mask;
1340
 
1341 169 jshamlet
        when others =>
1342
          null;
1343
      end case;
1344
 
1345 224 jshamlet
      Open8_Bus.GP_Flags     <= Flags(7 downto 3);
1346 188 jshamlet
 
1347 169 jshamlet
    end if;
1348
  end process;
1349
 
1350 182 jshamlet
-------------------------------------------------------------------------------
1351
-- Multiplier Logic
1352
--
1353
-- We need to infer a hardware multipler, so we create a special clocked
1354
--  process with no reset or clock enable
1355
-------------------------------------------------------------------------------
1356
 
1357
  Multiplier_proc: process( Clock )
1358
  begin
1359
    if( rising_edge(Clock) )then
1360
      Mult                   <= Regfile(0) *
1361 186 jshamlet
                                Regfile(conv_integer(ALU_Ctrl.Reg));
1362
    end if;
1363
  end process;
1364
 
1365
end architecture;

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