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Line No. Rev Author Line
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-- Copyright (c)2006, 2011, 2012, 2013, 2015, 2019, 2020 Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--     * Redistributions of source code must retain the above copyright
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--       notice, this list of conditions and the following disclaimer.
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--     * Redistributions in binary form must reproduce the above copyright
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--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
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--       where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 169 jshamlet
--
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-- VHDL Units :  o8_cpu
25 169 jshamlet
-- Description:  VHDL model of a RISC 8-bit processor core loosely based on the
26
--            :   V8/ARC uRISC instruction set. Requires Open8_pkg.vhd
27
--            :
28
-- Notes      :  Generic definitions
29
--            :
30
--            :  Program_Start_Addr sets the initial value of the program
31
--            :   counter.
32
--            :
33
--            :  ISR_Start_Addr sets the location of the interrupt service
34
--            :   vector table. There are 8 service vectors, or 16 bytes, which
35
--            :   must be allocated to either ROM or RAM.
36
--            :
37
--            :  Stack_Start_Address sets the initial (reset) value of the
38
--            :   stack pointer. Also used for the RSP instruction if
39
--            :   Allow_Stack_Address_Move is false.
40
--            :
41
--            :  Allow_Stack_Address_Move, when set true, allows the RSP to be
42 181 jshamlet
--            :   programmed via thet RSP instruction. If enabled, the
43
--            :   instruction changes into TSX or TXS based on the flag
44
--            :   specified by Stack_Xfer_Flag. If the flag is '0', RSP will
45
--            :   copy the current stack pointer to R1:R0 (TSX). If the flag
46
--            :   is '1', RSP will copy R1:R0 to the stack pointer (TXS). This
47
--            :   allows the processor to backup and restore stack pointers
48
--            :   in a multi-process environment. Note that no flags are
49
--            :   modified by either form of this instruction.
50 169 jshamlet
--            :
51 181 jshamlet
--            :  Stack_Xfer_Flag instructs the core to use the specified ALU
52
--            :   flag to alter the behavior of the RSP instruction when
53 256 jshamlet
--            :   Allow_Stack_Address_Move is set TRUE, otherwise it's ignored.
54 181 jshamlet
--            :   While technically any of the status bits may be used, the
55
--            :   intent was to use FL_GP[1,2,3,4], as these are not modified
56
--            :   by ordinary ALU operations.
57
--            :
58 169 jshamlet
--            :  The Enable_Auto_Increment generic can be used to modify the
59
--            :   indexed instructions such that specifying an odd register
60
--            :   will use the next lower register pair, post-incrementing the
61
--            :   value in that pair. IOW, specifying STX R1 will instead
62
--            :   result in STX R0++, or R0 = {R1:R0}; {R1:R0} + 1
63
--            :
64
--            :  BRK_Implements_WAI modifies the BRK instruction such that it
65
--            :   triggers the wait for interrupt state, but without triggering
66
--            :   a soft interrupt in lieu of its normal behavior, which is to
67
--            :   insert several dead clock cycles - essentially a long NOP
68
--            :
69
--            :  Enable_NMI overrides the mask bit for interrupt 0, creating a
70
--            :   non-maskable interrupt at the highest priority. To remain
71
--            :   true to the original core, this should be set false.
72
--            :
73 260 jshamlet
--            :  Sequential_Interrupts, when set, prevents interrupt service
74
--            :   routines from  being interrupted by postponing an later
75
--            :   interrupts until the I bit is cleared (usually with an RTI,
76
--            :   but a CLP PSR_I will also work). This is potentially
77
--            :   dangerous, as it means a lower-priority ISR can "hog" the CPU
78
--            :   by failing to return. However, it can also prevent the
79
--            :   condition of an ISR interrupting itself until it causes a
80
--            :   memory fault. (For example, an interrupt source that whose
81
--            :   period is shorter than the ISR service time) Note that this
82
--            :   setting alters the way the pending logic works, so it affects
83
--            :   all interrupts, including the NMI. If this is set, special
84
--            :   care should be taken to make sure ISRs are short and always
85
--            :   execute an RTI at the end.
86
--            :
87 188 jshamlet
--            :  RTI_Ignores_GP_Flags alters the set of flag bits restored
88
--            :   after an interrupt. By default, all of the flag bits are put
89
--            :   back to their original state. If this flag is set true, only
90
--            :   the lower four bits are restored, allowing ISR code to alter
91
--            :   the GP flags persistently.
92
--            :
93 244 jshamlet
--            :  Supervisor_Mode, when set, disables the STP PSR_I instruction
94
--            :   preventing code from setting the I bit. When enabled, only
95
--            :   interrupts can set the I bit, allowing for more robust memory
96
--            :   protection by preventing errant code execution from
97
--            :   inadvertently entering an interrupt state.
98
--            :
99 248 jshamlet
--            :   This setting also sets I bit at startup so that any
100
--            :   initialization code may be run in an ISR context, initially
101
--            :   bypassing memory protection. Init code should clear the I bit
102
--            :   when done;
103 244 jshamlet
--            :
104 255 jshamlet
--            :  Unsigned_Index_Offsets alters the way offsets are added to
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--            :   [Rn+1:Rn] during LDO/STO instructions. The original, default
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--            :   behavior treats these offsets as signed values, allowing
107
--            :   instructions to offset by -128 to +127 from [Rn+1:Rn].
108
--            :   Setting this generic to TRUE will switch to unsigned offsets,
109
--            :   switching the range to 0 to 255 instead.
110
--            :
111 169 jshamlet
--            :  Default_Interrupt_Mask sets the intial/reset value of the
112
--            :   interrupt mask. To remain true to the original core, which
113
--            :   had no interrupt mask, this should be set to x"FF". Otherwise
114
--            :   it can be initialized to any value. Note that Enable_NMI
115
--            :   will logically force the LSB high.
116 172 jshamlet
--            :
117 169 jshamlet
--            :  Reset_Level determines whether the processor registers reset
118
--            :   on a high or low level from higher logic.
119
--            :
120
--            : Architecture notes
121
--            :  This model deviates from the original ISA in a few important
122
--            :   ways.
123
--            :
124
--            :  First, there is only one set of registers. Interrupt service
125
--            :   routines must explicitely preserve context since the the
126
--            :   hardware doesn't. This was done to decrease size and code
127
--            :   complexity. Older code that assumes this behavior will not
128
--            :   execute correctly on this processor model.
129
--            :
130
--            :  Second, this model adds an additional pipeline stage between
131
--            :   the instruction decoder and the ALU. Unfortunately, this
132
--            :   means that the instruction stream has to be restarted after
133
--            :   any math instruction is executed, implying that any ALU
134
--            :   instruction now has a latency of 2 instead of 0. The
135
--            :   advantage is that the maximum frequency has gone up
136
--            :   significantly, as the ALU code is vastly more efficient.
137
--            :   As an aside, this now means that all math instructions,
138
--            :   including MUL (see below) and UPP have the same instruction
139
--            :   latency.
140
--            :
141
--            :  Third, the original ISA, also a soft core, had two reserved
142
--            :   instructions, USR and USR2. These have been implemented as
143
--            :   DBNZ, and MUL respectively.
144
--            :
145
--            :  DBNZ decrements the specified register and branches if the
146
--            :   result is non-zero. The instruction effectively executes a
147
--            :   DEC Rn instruction prior to branching, so the same flags will
148
--            :   be set.
149
--            :
150
--            :  MUL places the result of R0 * Rn into R1:R0. Instruction
151
--            :   latency is identical to other ALU instructions. Only the Z
152
--            :   flag is set, since there is no defined overflow or "negative
153
--            :   16-bit values"
154
--            :
155
--            :  Fourth, indexed load/store instructions now have an (optional)
156
--            :   ability to post-increment their index registers. If enabled,
157
--            :   using an odd operand for LDO,LDX, STO, STX will cause the
158
--            :   register pair to be incremented after the storage access.
159
--            :
160
--            :  Fifth, the RSP instruction has been (optionally) altered to
161
--            :   allow the stack pointer to be sourced from R1:R0.
162
--            :
163
--            :  Sixth, the BRK instruction can optionally implement a WAI,
164
--            :   which is the same as the INT instruction without the soft
165
--            :   interrupt, as a way to put the processor to "sleep" until the
166
--            :   next external interrupt.
167
--            :
168
--            :  Seventh, the original CPU model had 8 non-maskable interrupts
169
--            :   with priority. This model has the same 8 interrupts, but
170 172 jshamlet
--            :   allows software to mask them (with an additional option to
171 169 jshamlet
--            :   override the highest priority interrupt, making it the NMI.)
172
--            :
173
--            :  Lastly, previous unmapped instructions in the OP_STK opcode
174
--            :   were repurposed to support a new interrupt mask.
175
--            :   SMSK and GMSK transfer the contents of R0 (accumulator)
176
--            :   to/from the interrupt mask register. SMSK is immediate, while
177
--            :   GMSK has the same overhead as a math instruction.
178
--
179
-- Revision History
180
-- Author          Date     Change
181
------------------ -------- ---------------------------------------------------
182
-- Seth Henry      07/19/06 Design Start
183
-- Seth Henry      01/18/11 Fixed BTT instruction to match V8
184
-- Seth Henry      07/22/11 Fixed interrupt transition logic to avoid data
185
--                           corruption issues.
186
-- Seth Henry      07/26/11 Optimized logic in ALU, stack pointer, and data
187
--                           path sections.
188
-- Seth Henry      07/27/11 Optimized logic for timing, merged blocks into
189
--                           single entity.
190
-- Seth Henry      09/20/11 Added BRK_Implements_WAI option, allowing the
191
--                           processor to wait for an interrupt instead of the
192
--                           normal BRK behavior.
193 187 jshamlet
-- Seth Henry      12/20/11 Modified core to allow WAI_Cx state to idle
194 169 jshamlet
--                           the bus entirely (Rd_Enable is low)
195
-- Seth Henry      02/03/12 Replaced complex interrupt controller with simpler,
196
--                           faster logic that simply does priority encoding.
197
-- Seth Henry      08/06/13 Removed HALT functionality
198
-- Seth Henry      10/29/15 Fixed inverted carry logic in CMP and SBC instrs
199 182 jshamlet
-- Seth Henry      12/19/19 Renamed to o8_cpu to fit "theme"
200 181 jshamlet
-- Seth Henry      03/09/20 Modified RSP instruction to work with a CPU flag
201
--                           allowing true backup/restore of the stack pointer
202 182 jshamlet
-- Seth Henry      03/11/20 Split the address logic from the main state machine
203
--                           in order to simplify things and eliminate
204
--                           redundancies. Came across and fixed a problem with
205
--                           the STO instruction when Enable_Auto_Increment is
206
--                           NOT set.
207 185 jshamlet
-- Seth Henry      03/12/20 Rationalized the naming of the CPU flags to match
208
--                           the assembler names. Also fixed an issue where
209
--                           the I bit wasn't being cleared after interrupts.
210
--                          Simplified the program counter logic to only use
211
--                           the offset for increments, redefining the
212
--                           original modes as fixed offset values.
213
--                          Modified the ALU section with a new ALU operation
214
--                           for GMSK. This allowed the .data field to be
215
--                           removed and Operand1 used in its place, which
216
--                           simplified the logic a great deal.
217 187 jshamlet
-- Seth Henry      03/16/20 Added CPU_Halt input back, only now as an input to
218
--                           the instruction decode state, where it acts as a
219
--                           modified form of the BRK instruction that holds
220
--                           state until CPU_Halt is deasserted. This has a
221
--                           much smaller impact on Fmax/complexity than the
222
--                           original clock enable, but imposes a mild impact
223
--                           due to the need to reset the instruction pipeline
224 188 jshamlet
-- Seth Henry      03/17/20 Added generic to control whether RTI full restores
225
--                           the flags, including the general purpose ones, or
226
--                           only the core ALU flags (Z, N, and C). Also
227
--                           brought out copies of the GP flags for external
228
--                           connection.
229 210 jshamlet
-- Seth Henry      04/09/20 Added a compile time setting to block interrupts
230
--                           while the I bit is set to avoid reentering ISRs
231
--                           This may slightly affect timing, as this will
232
--                           potentially block higher priority interrupts
233
--                           until the lower priority ISR returns or clears
234
--                           the I bit.
235
--                          Also added the I bit to the exported flags for
236
--                           use in memory protection schemes.
237 224 jshamlet
-- Seth Henry      04/16/20 Modified to use new Open8 bus record. Also added
238 225 jshamlet
--                           reset and usec_tick logic to drive utility
239
--                           signals. Also added Halt_Ack output.
240 244 jshamlet
-- Seth Henry      05/20/20 Added two new generics to alter the way the I bit
241
--                           is handled. The Supervisor_Mode setting disables
242
--                           STP PSR_I from being executed, preventing it
243
--                           from being set outside of an ISR. The
244
--                           Default_Int_Flag setting allows the I bit to
245
--                           start set so that initialization code can run,
246
--                           but not be hijacked later to corrupt any memory
247
--                           write protection later.
248 245 jshamlet
-- Seth Henry      05/21/20 Supervisor_Mode now protects the interrupt mask
249
--                           and stack pointer as well.
250 248 jshamlet
-- Seth Henry      05/24/20 Removed the Default_Int_Flag, as it is covered by
251
--                           Supervisor_Mode. If Supervisor_Mode isn't set,
252
--                           code can simply use STP to set the bit
253 252 jshamlet
-- Seth Henry      06/09/20 Added ability to use unsigned index offsets for
254 253 jshamlet
--                           LDO/STO. Also pipelined the address calculation
255 252 jshamlet
--                           for indexed instructions, reducing the final
256
--                           address generator to a multiplexor fed only by
257
--                           registers.
258 264 jshamlet
-- Seth Henry      07/10/20 Fixed a bug in the LDO/LDX logic where the register
259
--                           pair wasn't being incremented properly due to a
260
--                           missing UPP2 signal to the ALU.
261 169 jshamlet
 
262
library ieee;
263
  use ieee.std_logic_1164.all;
264
  use ieee.std_logic_unsigned.all;
265
  use ieee.std_logic_arith.all;
266
  use ieee.std_logic_misc.all;
267
 
268
library work;
269 227 jshamlet
  use work.Open8_pkg.all;
270 169 jshamlet
 
271 183 jshamlet
entity o8_cpu is
272 169 jshamlet
  generic(
273
    Program_Start_Addr       : ADDRESS_TYPE := x"0000"; -- Initial PC location
274
    ISR_Start_Addr           : ADDRESS_TYPE := x"FFF0"; -- Bottom of ISR vec's
275
    Stack_Start_Addr         : ADDRESS_TYPE := x"03FF"; -- Top of Stack
276
    Allow_Stack_Address_Move : boolean      := false;   -- Use Normal v8 RSP
277 188 jshamlet
    Stack_Xfer_Flag          : integer      := PSR_GP4; -- GP4 modifies RSP
278 169 jshamlet
    Enable_Auto_Increment    : boolean      := false;   -- Modify indexed instr
279
    BRK_Implements_WAI       : boolean      := false;   -- BRK -> Wait for Int
280
    Enable_NMI               : boolean      := true;    -- Force INTR0 enabled
281 210 jshamlet
    Sequential_Interrupts    : boolean      := false;   -- Interruptable ISRs
282 224 jshamlet
    RTI_Ignores_GP_Flags     : boolean      := false;   -- RTI sets all flags
283 244 jshamlet
    Supervisor_Mode          : boolean      := false;   -- I bit is restricted
284 252 jshamlet
    Unsigned_Index_Offsets   : boolean      := false;   -- Offsets are signed
285 169 jshamlet
    Default_Interrupt_Mask   : DATA_TYPE    := x"FF";   -- Enable all Ints
286 224 jshamlet
    Clock_Frequency          : real                     -- Clock Frequency
287
);
288 169 jshamlet
  port(
289
    Clock                    : in  std_logic;
290 224 jshamlet
    PLL_Locked               : in  std_logic;
291 169 jshamlet
    --
292 225 jshamlet
    Halt_Req                 : in  std_logic := '0';
293
    Halt_Ack                 : out std_logic;
294
    --
295 223 jshamlet
    Open8_Bus                : out OPEN8_BUS_TYPE;
296 169 jshamlet
    Rd_Data                  : in  DATA_TYPE;
297 223 jshamlet
    Interrupts               : in  INTERRUPT_BUNDLE := x"00"
298
);
299 169 jshamlet
end entity;
300
 
301 183 jshamlet
architecture behave of o8_cpu is
302 169 jshamlet
 
303 224 jshamlet
  signal Reset_q             : std_logic := Reset_Level;
304
  signal Reset               : std_logic := Reset_Level;
305
 
306
  constant USEC_VAL          : integer := integer(Clock_Frequency / 1000000.0);
307
  constant USEC_WDT          : integer := ceil_log2(USEC_VAL - 1);
308
  constant USEC_DLY          : std_logic_vector :=
309
                                conv_std_logic_vector(USEC_VAL - 1, USEC_WDT);
310
  signal uSec_Cntr           : std_logic_vector( USEC_WDT - 1 downto 0 );
311
  signal uSec_Tick           : std_logic;
312
 
313 187 jshamlet
  signal CPU_Next_State      : CPU_STATES := IPF_C0;
314
  signal CPU_State           : CPU_STATES := IPF_C0;
315 169 jshamlet
 
316 225 jshamlet
  signal CPU_Halt_Req        : std_logic := '0';
317
  signal CPU_Halt_Ack        : std_logic := '0';
318 187 jshamlet
 
319 169 jshamlet
  signal Cache_Ctrl          : CACHE_MODES := CACHE_IDLE;
320
 
321
  signal Opcode              : OPCODE_TYPE := (others => '0');
322
  signal SubOp, SubOp_p1     : SUBOP_TYPE  := (others => '0');
323
 
324
  signal Prefetch            : DATA_TYPE   := x"00";
325
  signal Operand1, Operand2  : DATA_TYPE   := x"00";
326
 
327
  signal Instr_Prefetch      : std_logic   := '0';
328
 
329
  signal PC_Ctrl             : PC_CTRL_TYPE;
330
  signal Program_Ctr         : ADDRESS_TYPE := x"0000";
331
 
332 182 jshamlet
  signal ALU_Ctrl            : ALU_CTRL_TYPE;
333
  signal Regfile             : REGFILE_TYPE;
334
  signal Flags               : FLAG_TYPE;
335
  signal Mult                : ADDRESS_TYPE := x"0000";
336
 
337 169 jshamlet
  signal SP_Ctrl             : SP_CTRL_TYPE;
338
  signal Stack_Ptr           : ADDRESS_TYPE := x"0000";
339
 
340
  signal DP_Ctrl             : DATA_CTRL_TYPE;
341
 
342
  signal INT_Ctrl            : INT_CTRL_TYPE;
343
  signal Ack_D, Ack_Q, Ack_Q1: std_logic   := '0';
344
  signal Int_Req, Int_Ack    : std_logic   := '0';
345 245 jshamlet
  signal Set_Mask            : std_logic   := '0';
346 169 jshamlet
  signal Int_Mask            : DATA_TYPE   := x"00";
347
  signal i_Ints              : INTERRUPT_BUNDLE := x"00";
348
  signal Pending             : INTERRUPT_BUNDLE := x"00";
349
  signal Wait_for_FSM        : std_logic := '0';
350 210 jshamlet
  signal Wait_for_ISR        : std_logic := '0';
351 169 jshamlet
 
352 254 jshamlet
  alias  ISR_Addr_Base       is ISR_Start_Addr(15 downto 4);
353
  signal ISR_Addr_Offset     : std_logic_vector(3 downto 0) := x"0";
354
 
355
  constant INT_VECTOR_0      : std_logic_vector(3 downto 0) := x"0";
356
  constant INT_VECTOR_1      : std_logic_vector(3 downto 0) := x"2";
357
  constant INT_VECTOR_2      : std_logic_vector(3 downto 0) := x"4";
358
  constant INT_VECTOR_3      : std_logic_vector(3 downto 0) := x"6";
359
  constant INT_VECTOR_4      : std_logic_vector(3 downto 0) := x"8";
360
  constant INT_VECTOR_5      : std_logic_vector(3 downto 0) := x"A";
361
  constant INT_VECTOR_6      : std_logic_vector(3 downto 0) := x"C";
362
  constant INT_VECTOR_7      : std_logic_vector(3 downto 0) := x"E";
363
 
364 255 jshamlet
  signal IDX_Offset_SX       : std_logic := '0';
365
 
366 252 jshamlet
  signal IDX_Offset          : ADDRESS_TYPE := x"0000";
367
 
368 255 jshamlet
  signal IDX_Sel_l           : std_logic_vector(2 downto 0) := "000";
369
  signal IDX_Sel_h           : std_logic_vector(2 downto 0) := "000";
370
 
371 252 jshamlet
  signal IDX_Reg_l           : integer := 0;
372
  signal IDX_Reg_h           : integer := 0;
373
 
374
  signal IDX_NoOffset_Calc   : ADDRESS_TYPE := x"0000";
375
  signal IDX_Offset_Calc     : ADDRESS_TYPE := x"0000";
376
 
377 169 jshamlet
begin
378
 
379 224 jshamlet
-------------------------------------------------------------------------------
380
-- Reset & uSec Tick
381
-------------------------------------------------------------------------------
382 185 jshamlet
 
383 224 jshamlet
  CPU_Reset_Sync: process( Clock, PLL_Locked )
384
  begin
385
    if( PLL_Locked = '0' )then
386
      Reset_q                <= Reset_Level;
387
      Reset                  <= Reset_Level;
388
    elsif( rising_edge(Clock) )then
389
      Reset_q                <= not Reset_Level;
390
      Reset                  <= Reset_q;
391
    end if;
392
  end process;
393
 
394
  uSec_Tick_proc: process( Clock, Reset )
395
  begin
396
    if( Reset = Reset_Level )then
397
      uSec_Cntr              <= USEC_DLY;
398
      uSec_Tick              <= '0';
399
    elsif( rising_edge( Clock ) )then
400
      uSec_Cntr              <= uSec_Cntr - 1;
401
      if( or_reduce(uSec_Cntr) = '0' )then
402
        uSec_Cntr            <= USEC_DLY;
403
      end if;
404
      uSec_Tick              <= nor_reduce(uSec_Cntr);
405
    end if;
406
  end process;
407
 
408
  Open8_Bus.Clock            <= Clock;
409
  Open8_Bus.Reset            <= Reset;
410
  Open8_Bus.uSec_Tick        <= uSec_Tick;
411
 
412 169 jshamlet
-------------------------------------------------------------------------------
413 182 jshamlet
-- Address bus selection/generation logic
414 169 jshamlet
-------------------------------------------------------------------------------
415
 
416 254 jshamlet
  -- Address selection logic based on current CPU state. This is combinatorial,
417
  --  as adding pipeline registration would add a clock cycle to every instr,
418
  --  without really adding the Fmax to compensate.
419
  Address_Logic: process(CPU_State, Operand1, Operand2, IDX_NoOffset_Calc,
420 255 jshamlet
                         IDX_Offset_Calc, ISR_Addr_Offset, Stack_Ptr,
421
                         Program_Ctr )
422 254 jshamlet
  begin
423
    case( CPU_State )is
424
 
425
      when LDA_C2 | STA_C2 =>
426
        Open8_Bus.Address    <= Operand2 & Operand1;
427
 
428
      when LDX_C1 | STX_C1 =>
429
        Open8_Bus.Address    <= IDX_NoOffset_Calc;
430
 
431
      when LDO_C2 | STO_C2 =>
432
        Open8_Bus.Address    <= IDX_Offset_Calc;
433
 
434
      when ISR_C1 | ISR_C2 =>
435
        Open8_Bus.Address    <= ISR_Addr_Base & ISR_Addr_Offset;
436
 
437 255 jshamlet
      when PSH_C1 | POP_C1 |
438
           ISR_C3 | JSR_C1 | JSR_C2 |
439
           RTS_C1 | RTS_C2 | RTS_C3 =>
440 254 jshamlet
        Open8_Bus.Address    <= Stack_Ptr;
441
 
442
      when others =>
443
        Open8_Bus.Address    <= Program_Ctr;
444
 
445
    end case;
446
  end process;
447
 
448 252 jshamlet
  -- The original model treated the offset to LDO/STO as a signed value
449
  --  allowing access to locations -128 to +127 from [Rn+1:Rn]. This isn't
450
  --  always helpful, so the generic allows the CPU to use unsigned math
451
  --  for the offsets. This makes the range 0 to +255 instead.
452 253 jshamlet
 
453 255 jshamlet
  IDX_Offset_SX <= '0' when Unsigned_Index_Offsets else Operand1(7);
454 252 jshamlet
 
455 255 jshamlet
  IDX_Offset(15 downto 8)    <= (others => IDX_Offset_SX);
456 252 jshamlet
  IDX_Offset(7 downto 0)     <= Operand1;
457
 
458
  -- Enable_Auto_Increment uses the LSB to determine whether or not to
459
  --  do the auto-increment, so we need to lock the LSB for each operand
460
  --  if it is enabled. This forces [ODD:EVEN] pairing.
461
 
462 255 jshamlet
  IDX_Sel_l <= (SubOp(2 downto 1) & '0') when Enable_Auto_Increment else
463
               SubOp;
464 252 jshamlet
 
465 255 jshamlet
  IDX_Sel_h <= (SubOp(2 downto 1) & '1') when Enable_Auto_Increment else
466
               SubOp_p1;
467 252 jshamlet
 
468 255 jshamlet
  IDX_Reg_l <= conv_integer(IDX_Sel_l);
469
  IDX_Reg_h <= conv_integer(IDX_Sel_h);
470
 
471 252 jshamlet
  -- Pipeline registers for the indexed and indexed with offset addresses.
472
  Idx_Addr_Calc_proc: process( Clock, Reset )
473 169 jshamlet
    variable Reg, Reg_1      : integer range 0 to 7 := 0;
474
  begin
475 252 jshamlet
    if( Reset = Reset_Level )then
476
      IDX_NoOffset_Calc      <= x"0000";
477
      IDX_Offset_Calc        <= x"0000";
478
    elsif( rising_edge(Clock))then
479
      IDX_NoOffset_Calc      <= (Regfile(IDX_Reg_h) & Regfile(IDX_Reg_l));
480
      IDX_Offset_Calc        <= (Regfile(IDX_Reg_h) & Regfile(IDX_Reg_l)) +
481
                                IDX_Offset;
482 182 jshamlet
    end if;
483 252 jshamlet
  end process;
484 182 jshamlet
 
485
-------------------------------------------------------------------------------
486
-- Combinatorial portion of CPU finite state machine
487
-- State Logic / Instruction Decoding & Execution
488
-------------------------------------------------------------------------------
489
 
490 187 jshamlet
  State_Logic: process(CPU_State, Flags, Int_Mask, CPU_Halt_Req, Opcode,
491 182 jshamlet
                       SubOp , SubOp_p1, Operand1, Operand2, Int_Req )
492
    variable Reg             : integer range 0 to 7 := 0;
493
  begin
494 169 jshamlet
    CPU_Next_State           <= CPU_State;
495
    Cache_Ctrl               <= CACHE_IDLE;
496
    --
497 185 jshamlet
    PC_Ctrl.Oper             <= PC_INCR;
498
    PC_Ctrl.Offset           <= PC_IDLE;
499 182 jshamlet
    --
500 169 jshamlet
    ALU_Ctrl.Oper            <= ALU_IDLE;
501
    ALU_Ctrl.Reg             <= ACCUM;
502
    --
503
    SP_Ctrl.Oper             <= SP_IDLE;
504
    --
505
    DP_Ctrl.Src              <= DATA_RD_MEM;
506
    DP_Ctrl.Reg              <= ACCUM;
507
    --
508
    INT_Ctrl.Mask_Set        <= '0';
509
    INT_Ctrl.Soft_Ints       <= x"00";
510
    INT_Ctrl.Incr_ISR        <= '0';
511
    Ack_D                    <= '0';
512 225 jshamlet
    --
513 182 jshamlet
    Reg                     := conv_integer(SubOp);
514 225 jshamlet
    --
515
    CPU_Halt_Ack             <= '0';
516 169 jshamlet
 
517
    case CPU_State is
518
-------------------------------------------------------------------------------
519
-- Initial Instruction fetch & decode
520
-------------------------------------------------------------------------------
521 187 jshamlet
      when IPF_C0 =>
522
        CPU_Next_State       <= IPF_C1;
523 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
524 169 jshamlet
 
525 187 jshamlet
      when IPF_C1 =>
526
        CPU_Next_State       <= IPF_C2;
527 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
528 169 jshamlet
 
529 187 jshamlet
      when IPF_C2 =>
530
        CPU_Next_State       <= IDC_C0;
531 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
532 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
533 169 jshamlet
 
534 187 jshamlet
      when IDC_C0 =>
535
        CPU_Next_State       <= IDC_C0;
536 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
537
 
538
        case Opcode is
539
          when OP_PSH =>
540
            CPU_Next_State   <= PSH_C1;
541
            Cache_Ctrl       <= CACHE_PREFETCH;
542 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
543 169 jshamlet
            DP_Ctrl.Src      <= DATA_WR_REG;
544
            DP_Ctrl.Reg      <= SubOp;
545
 
546
          when OP_POP =>
547
            CPU_Next_State   <= POP_C1;
548
            Cache_Ctrl       <= CACHE_PREFETCH;
549 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
550 169 jshamlet
            SP_Ctrl.Oper     <= SP_POP;
551
 
552
          when OP_BR0 | OP_BR1 =>
553
            CPU_Next_State   <= BRN_C1;
554
            Cache_Ctrl       <= CACHE_OPER1;
555 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
556 169 jshamlet
 
557 185 jshamlet
 
558 169 jshamlet
          when OP_DBNZ =>
559
            CPU_Next_State   <= DBNZ_C1;
560
            Cache_Ctrl       <= CACHE_OPER1;
561 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
562 169 jshamlet
            ALU_Ctrl.Oper    <= ALU_DEC;
563
            ALU_Ctrl.Reg     <= SubOp;
564
 
565
          when OP_INT =>
566 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
567 187 jshamlet
            -- Make sure the requested interrupt is actually enabled first.
568
            --  Also, unlike CPU_Halt, the INT instruction is actually being
569
            --  executed, so go ahead and increment the program counter before
570
            --  pausing so the CPU restarts on the next instruction.
571 169 jshamlet
            if( Int_Mask(Reg) = '1' )then
572 187 jshamlet
              CPU_Next_State <= WAI_Cx;
573 169 jshamlet
              INT_Ctrl.Soft_Ints(Reg) <= '1';
574
            end if;
575
 
576
          when OP_STK =>
577
            case SubOp is
578
              when SOP_RSP  =>
579 185 jshamlet
                PC_Ctrl.Offset <= PC_NEXT;
580 181 jshamlet
                if( not Allow_Stack_Address_Move )then
581 187 jshamlet
                  -- The default behavior for this instruction is to simply
582
                  --  repoint the SP to the HDL default
583 185 jshamlet
                  SP_Ctrl.Oper    <= SP_CLR;
584 181 jshamlet
                end if;
585 187 jshamlet
                if( Allow_Stack_Address_Move and
586
                    Flags(Stack_Xfer_Flag) = '1' )then
587
                  -- If RSP is set to allow SP moves, and the specified flag
588
                  --  is true, then signal the stack pointer logic to load
589
                  --  from R1:R0
590 185 jshamlet
                  SP_Ctrl.Oper    <= SP_SET;
591 181 jshamlet
                end if;
592 187 jshamlet
                if( Allow_Stack_Address_Move and
593
                    Flags(Stack_Xfer_Flag) = '0')then
594
                  -- If RSP is set to allow SP moves, and the specified flag
595
                  --  is false, then signal the ALU to copy the stack pointer
596
                  --  to R1:R0
597 185 jshamlet
                  ALU_Ctrl.Oper   <= ALU_RSP;
598 181 jshamlet
                end if;
599 169 jshamlet
 
600
              when SOP_RTS | SOP_RTI =>
601 185 jshamlet
                CPU_Next_State    <= RTS_C1;
602 190 jshamlet
                Cache_Ctrl        <= CACHE_IDLE;
603 185 jshamlet
                SP_Ctrl.Oper      <= SP_POP;
604 169 jshamlet
 
605
              when SOP_BRK  =>
606
                if( BRK_Implements_WAI )then
607 187 jshamlet
                  -- If BRK_Implements_WAI, then jump to the WAI_Cx and
608
                  --  increment the PC similar to an ISR flow.
609
                  CPU_Next_State  <= WAI_Cx;
610 185 jshamlet
                  PC_Ctrl.Offset  <= PC_NEXT;
611 187 jshamlet
                else
612
                -- If Break is implemented normally, back the PC up by
613 260 jshamlet
                --  2 and return through IPF_C0 in order to execute a 3
614 187 jshamlet
                --  clock cycle delay
615
                  CPU_Next_State  <= BRK_C1;
616
                  PC_Ctrl.Offset  <= PC_REV2;
617 169 jshamlet
                end if;
618
 
619
              when SOP_JMP  =>
620 185 jshamlet
                CPU_Next_State    <= JMP_C1;
621
                Cache_Ctrl        <= CACHE_OPER1;
622 169 jshamlet
 
623
              when SOP_SMSK =>
624 185 jshamlet
                PC_Ctrl.Offset    <= PC_NEXT;
625 169 jshamlet
                INT_Ctrl.Mask_Set <= '1';
626
 
627
              when SOP_GMSK =>
628 185 jshamlet
                PC_Ctrl.Offset    <= PC_NEXT;
629
                ALU_Ctrl.Oper     <= ALU_GMSK;
630 169 jshamlet
 
631
              when SOP_JSR =>
632
                CPU_Next_State <= JSR_C1;
633 185 jshamlet
                Cache_Ctrl        <= CACHE_OPER1;
634
                DP_Ctrl.Src       <= DATA_WR_PC;
635
                DP_Ctrl.Reg       <= PC_MSB;
636 169 jshamlet
 
637
              when others => null;
638
            end case;
639
 
640
          when OP_MUL =>
641
            CPU_Next_State   <= MUL_C1;
642 181 jshamlet
            -- Multiplication requires a single clock cycle to calculate PRIOR
643
            --  to the ALU writing the result to registers. As a result, this
644
            --  state needs to idle the ALU initially, and back the PC up by 1
645
            -- We can get away with only 1 extra clock by pre-fetching the
646
            --  next instruction, though.
647 169 jshamlet
            Cache_Ctrl       <= CACHE_PREFETCH;
648 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
649 181 jshamlet
            -- Note that both the multiply process AND ALU process need the
650
            --  source register for Rn (R1:R0 = R0 * Rn). Assert ALU_Ctrl.reg
651
            --  now, but hold off on the ALU command until the next state.
652 169 jshamlet
            ALU_Ctrl.Oper    <= ALU_IDLE;
653
            ALU_Ctrl.Reg     <= SubOp;
654
 
655
          when OP_UPP =>
656
            CPU_Next_State   <= UPP_C1;
657
            Cache_Ctrl       <= CACHE_PREFETCH;
658 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
659 169 jshamlet
            ALU_Ctrl.Oper    <= Opcode;
660
            ALU_Ctrl.Reg     <= SubOp;
661
 
662
          when OP_LDA =>
663
            CPU_Next_State   <= LDA_C1;
664
            Cache_Ctrl       <= CACHE_OPER1;
665
 
666
          when OP_LDI =>
667
            CPU_Next_State   <= LDI_C1;
668
            Cache_Ctrl       <= CACHE_OPER1;
669 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
670 169 jshamlet
 
671
          when OP_LDO =>
672
            CPU_Next_State   <= LDO_C1;
673
            Cache_Ctrl       <= CACHE_OPER1;
674 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
675 169 jshamlet
 
676
          when OP_LDX =>
677
            CPU_Next_State   <= LDX_C1;
678 181 jshamlet
            Cache_Ctrl       <= CACHE_PREFETCH;
679 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
680 169 jshamlet
 
681
          when OP_STA =>
682
            CPU_Next_State   <= STA_C1;
683
            Cache_Ctrl       <= CACHE_OPER1;
684
 
685
          when OP_STO =>
686
            CPU_Next_State   <= STO_C1;
687
            Cache_Ctrl       <= CACHE_OPER1;
688 252 jshamlet
            PC_Ctrl.Offset   <= PC_REV1;
689 169 jshamlet
 
690
          when OP_STX =>
691
            CPU_Next_State   <= STX_C1;
692
            Cache_Ctrl       <= CACHE_PREFETCH;
693 185 jshamlet
            PC_Ctrl.Offset   <= PC_REV2;
694 169 jshamlet
            DP_Ctrl.Src      <= DATA_WR_REG;
695
            DP_Ctrl.Reg      <= ACCUM;
696
 
697 244 jshamlet
          when OP_STP =>
698
            PC_Ctrl.Offset   <= PC_NEXT;
699
            if( Supervisor_Mode )then
700
              if( SubOp /= PSR_I )then
701
                ALU_Ctrl.Oper  <= Opcode;
702
                ALU_Ctrl.Reg   <= SubOp;
703
              end if;
704
            else
705
              ALU_Ctrl.Oper  <= Opcode;
706
              ALU_Ctrl.Reg   <= SubOp;
707
            end if;
708
 
709 169 jshamlet
          when others =>
710 185 jshamlet
            PC_Ctrl.Offset   <= PC_NEXT;
711 169 jshamlet
            ALU_Ctrl.Oper    <= Opcode;
712
            ALU_Ctrl.Reg     <= SubOp;
713
 
714
        end case;
715
 
716 186 jshamlet
        if( Int_Req = '1' )then
717
          CPU_Next_State     <= ISR_C1;
718 187 jshamlet
        end if;
719
 
720
        if( CPU_Halt_Req = '1' )then
721
          CPU_Next_State     <= WAH_Cx;
722
        end if;
723
 
724
        -- If either of these override conditions are true, the decoder needs
725
        --  to undo everything it just setup, since even "single-cycle"
726
        --  instructions will be executed again upon return.
727
        if( Int_Req = '1' or CPU_Halt_Req = '1' )then
728
          -- In either case, we want to skip loading the cache, as the cache
729
          --  will be invalid by the time we get back.
730 186 jshamlet
          Cache_Ctrl         <= CACHE_IDLE;
731 187 jshamlet
          -- Rewind the PC by 3 to put the PC back to the current instruction,
732
          -- compensating for the pipeline registers.
733 186 jshamlet
          PC_Ctrl.Offset     <= PC_REV3;
734
          -- Reset all of the sub-block controls to IDLE, to avoid unintended
735 187 jshamlet
          --  operation due to the current instruction.
736 186 jshamlet
          ALU_Ctrl.Oper      <= ALU_IDLE;
737
          SP_Ctrl.Oper       <= SP_IDLE;
738 187 jshamlet
          -- Interrupt logic outside of the state machine needs this to be set
739
          --  to DATA_RD_MEM, while CPU_Halt considers this a "don't care".
740 186 jshamlet
          DP_Ctrl.Src        <= DATA_RD_MEM;
741 187 jshamlet
          -- If an INT/SMSK instruction was going to be executed, it will get
742
          --  executed again when normal processing resumes, so axe their
743
          --  requests for now.
744
          INT_Ctrl.Mask_Set       <= '0';
745
          INT_Ctrl.Soft_Ints(Reg) <= '0';
746 186 jshamlet
        end if;
747
 
748 169 jshamlet
-------------------------------------------------------------------------------
749
-- Program Control (BR0_C1, BR1_C1, DBNZ_C1, JMP )
750
-------------------------------------------------------------------------------
751
 
752
      when BRN_C1 =>
753 187 jshamlet
        CPU_Next_State       <= IDC_C0;
754 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
755 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
756 169 jshamlet
        if( Flags(Reg) = Opcode(0) )then
757 187 jshamlet
          CPU_Next_State     <= IPF_C0;
758 169 jshamlet
          Cache_Ctrl         <= CACHE_IDLE;
759
          PC_Ctrl.Offset     <= Operand1;
760
        end if;
761
 
762
      when DBNZ_C1 =>
763 187 jshamlet
        CPU_Next_State       <= IDC_C0;
764 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
765 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
766
        if( Flags(PSR_Z) = '0' )then
767 187 jshamlet
          CPU_Next_State     <= IPF_C0;
768 169 jshamlet
          Cache_Ctrl         <= CACHE_IDLE;
769
          PC_Ctrl.Offset     <= Operand1;
770
        end if;
771
 
772
      when JMP_C1 =>
773
        CPU_Next_State       <= JMP_C2;
774
        Cache_Ctrl           <= CACHE_OPER2;
775
 
776
      when JMP_C2 =>
777 187 jshamlet
        CPU_Next_State       <= IPF_C0;
778 169 jshamlet
        PC_Ctrl.Oper         <= PC_LOAD;
779
 
780
-------------------------------------------------------------------------------
781
-- Data Storage - Load from memory (LDA, LDI, LDO, LDX)
782
-------------------------------------------------------------------------------
783
 
784
      when LDA_C1 =>
785
        CPU_Next_State       <= LDA_C2;
786
        Cache_Ctrl           <= CACHE_OPER2;
787
 
788
      when LDA_C2 =>
789
        CPU_Next_State       <= LDA_C3;
790
 
791
      when LDA_C3 =>
792
        CPU_Next_State       <= LDA_C4;
793 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
794 169 jshamlet
 
795
      when LDA_C4 =>
796
        CPU_Next_State       <= LDI_C1;
797
        Cache_Ctrl           <= CACHE_OPER1;
798 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
799 169 jshamlet
 
800
      when LDI_C1 =>
801 187 jshamlet
        CPU_Next_State       <= IDC_C0;
802 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
803 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
804 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_LDI;
805
        ALU_Ctrl.Reg         <= SubOp;
806
 
807
      when LDO_C1 =>
808 252 jshamlet
        CPU_Next_State       <= LDO_C2;
809
 
810
      when LDO_C2 =>
811 181 jshamlet
        CPU_Next_State       <= LDX_C2;
812 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
813 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
814
          ALU_Ctrl.Oper      <= ALU_UPP;
815
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
816 169 jshamlet
        end if;
817
 
818
      when LDX_C1 =>
819
        CPU_Next_State       <= LDX_C2;
820 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
821
          ALU_Ctrl.Oper      <= ALU_UPP;
822
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
823 181 jshamlet
        end if;
824 169 jshamlet
 
825
      when LDX_C2 =>
826
        CPU_Next_State       <= LDX_C3;
827 263 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
828
          ALU_Ctrl.Oper      <= ALU_UPP2;
829
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '1';
830
        end if;
831 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
832 181 jshamlet
 
833
      when LDX_C3 =>
834
        CPU_Next_State       <= LDX_C4;
835 182 jshamlet
        Cache_Ctrl           <= CACHE_OPER1;
836 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
837 169 jshamlet
 
838 181 jshamlet
      when LDX_C4 =>
839 187 jshamlet
        CPU_Next_State       <= IDC_C0;
840 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
841 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
842 181 jshamlet
        ALU_Ctrl.Oper        <= ALU_LDI;
843 169 jshamlet
        ALU_Ctrl.Reg         <= ACCUM;
844
 
845
-------------------------------------------------------------------------------
846
-- Data Storage - Store to memory (STA, STO, STX)
847
-------------------------------------------------------------------------------
848
      when STA_C1 =>
849
        CPU_Next_State       <= STA_C2;
850
        Cache_Ctrl           <= CACHE_OPER2;
851
        DP_Ctrl.Src          <= DATA_WR_REG;
852
        DP_Ctrl.Reg          <= SubOp;
853
 
854
      when STA_C2 =>
855
        CPU_Next_State       <= STA_C3;
856 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
857 169 jshamlet
 
858
      when STA_C3 =>
859 187 jshamlet
        CPU_Next_State       <= IPF_C2;
860 169 jshamlet
        Cache_Ctrl           <= CACHE_PREFETCH;
861 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
862 169 jshamlet
 
863
      when STO_C1 =>
864 252 jshamlet
        CPU_Next_State       <= STO_C2;
865 169 jshamlet
        Cache_Ctrl           <= CACHE_PREFETCH;
866 252 jshamlet
        DP_Ctrl.Src          <= DATA_WR_REG;
867
        DP_Ctrl.Reg          <= ACCUM;
868
 
869
      when STO_C2 =>
870
        CPU_Next_State       <= IPF_C1;
871 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
872 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
873 252 jshamlet
          CPU_Next_State     <= STO_C3;
874 182 jshamlet
          ALU_Ctrl.Oper      <= ALU_UPP;
875
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
876 169 jshamlet
        end if;
877
 
878 252 jshamlet
      when STO_C3 =>
879
        CPU_Next_State       <= IPF_C2;
880 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
881 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_UPP2;
882
        ALU_Ctrl.Reg         <= SubOp(2 downto 1) & '1';
883
 
884
      when STX_C1 =>
885 187 jshamlet
        CPU_Next_State       <= IPF_C1;
886 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
887 182 jshamlet
        if( Enable_Auto_Increment and SubOp(0) = '1' )then
888
          CPU_Next_State     <= STX_C2;
889
          ALU_Ctrl.Oper      <= ALU_UPP;
890
          ALU_Ctrl.Reg       <= SubOp(2 downto 1) & '0';
891 169 jshamlet
        end if;
892
 
893
      when STX_C2 =>
894 187 jshamlet
        CPU_Next_State       <= IPF_C2;
895 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
896 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_UPP2;
897
        ALU_Ctrl.Reg         <= SubOp(2 downto 1) & '1';
898
 
899
-------------------------------------------------------------------------------
900
-- Multi-Cycle Math Operations (UPP, MUL)
901
-------------------------------------------------------------------------------
902
 
903
      -- Because we have to backup the pipeline by 1 to refetch the 2nd
904 181 jshamlet
      --  instruction/first operand, we have to return through PF2. Also, we
905
      --  need to tell the ALU to store the results to R1:R0 here. Note that
906
      --  there is no ALU_Ctrl.Reg, as this is implied in the ALU instruction
907 169 jshamlet
      when MUL_C1 =>
908 187 jshamlet
        CPU_Next_State       <= IPF_C2;
909 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
910 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_MUL;
911
 
912
      when UPP_C1 =>
913 187 jshamlet
        CPU_Next_State       <= IPF_C2;
914 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
915 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_UPP2;
916
        ALU_Ctrl.Reg         <= SubOp_p1;
917
 
918
-------------------------------------------------------------------------------
919
-- Basic Stack Manipulation (PSH, POP, RSP)
920
-------------------------------------------------------------------------------
921
      when PSH_C1 =>
922 187 jshamlet
        CPU_Next_State       <= IPF_C1;
923 169 jshamlet
        SP_Ctrl.Oper         <= SP_PUSH;
924
 
925
      when POP_C1 =>
926
        CPU_Next_State       <= POP_C2;
927
 
928
      when POP_C2 =>
929
        CPU_Next_State       <= POP_C3;
930 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
931 169 jshamlet
 
932
      when POP_C3 =>
933
        CPU_Next_State       <= POP_C4;
934
        Cache_Ctrl           <= CACHE_OPER1;
935 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
936 169 jshamlet
 
937
      when POP_C4 =>
938 187 jshamlet
        CPU_Next_State       <= IDC_C0;
939 169 jshamlet
        Cache_Ctrl           <= CACHE_INSTR;
940 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
941 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_POP;
942
        ALU_Ctrl.Reg         <= SubOp;
943 172 jshamlet
 
944 169 jshamlet
-------------------------------------------------------------------------------
945
-- Subroutines & Interrupts (RTS, JSR)
946
-------------------------------------------------------------------------------
947 187 jshamlet
      when WAI_Cx => -- For soft interrupts only, halt the Program_Ctr
948 169 jshamlet
        DP_Ctrl.Src          <= DATA_BUS_IDLE;
949 186 jshamlet
        if( Int_Req = '1' )then
950
          CPU_Next_State     <= ISR_C1;
951 187 jshamlet
          -- Rewind the PC by 3 to put the PC back to would have been the next
952
          --  instruction, compensating for the pipeline registers.
953 186 jshamlet
          PC_Ctrl.Offset     <= PC_REV3;
954
          DP_Ctrl.Src        <= DATA_RD_MEM;
955
        end if;
956 169 jshamlet
 
957 187 jshamlet
      when WAH_Cx => -- Holds until CPU_Halt_Req is deasserted.
958 225 jshamlet
        CPU_Halt_Ack         <= '1';
959 187 jshamlet
        DP_Ctrl.Src          <= DATA_BUS_IDLE;
960
        if( CPU_Halt_Req = '0' )then
961
          CPU_Next_State     <= IPF_C0;
962
          DP_Ctrl.Src        <= DATA_RD_MEM;
963
        end if;
964
 
965
      when BRK_C1 => -- Debugging (BRK) Performs a 5-clock NOP.
966
        CPU_Next_State       <= IPF_C0;
967
 
968 169 jshamlet
      when ISR_C1 =>
969
        CPU_Next_State       <= ISR_C2;
970
        INT_Ctrl.Incr_ISR    <= '1';
971
 
972
      when ISR_C2 =>
973
        CPU_Next_State       <= ISR_C3;
974
        DP_Ctrl.Src          <= DATA_WR_FLAG;
975
 
976
      when ISR_C3 =>
977
        CPU_Next_State       <= JSR_C1;
978
        Cache_Ctrl           <= CACHE_OPER1;
979 182 jshamlet
        ALU_Ctrl.Oper        <= ALU_STP;
980 185 jshamlet
        ALU_Ctrl.Reg         <= conv_std_logic_vector(PSR_I,3);
981 169 jshamlet
        SP_Ctrl.Oper         <= SP_PUSH;
982
        DP_Ctrl.Src          <= DATA_WR_PC;
983 182 jshamlet
        DP_Ctrl.Reg          <= PC_MSB;
984 169 jshamlet
        Ack_D                <= '1';
985
 
986
      when JSR_C1 =>
987
        CPU_Next_State       <= JSR_C2;
988
        Cache_Ctrl           <= CACHE_OPER2;
989
        SP_Ctrl.Oper         <= SP_PUSH;
990
        DP_Ctrl.Src          <= DATA_WR_PC;
991 182 jshamlet
        DP_Ctrl.Reg          <= PC_LSB;
992 169 jshamlet
 
993
      when JSR_C2 =>
994 187 jshamlet
        CPU_Next_State       <= IPF_C0;
995 169 jshamlet
        PC_Ctrl.Oper         <= PC_LOAD;
996 182 jshamlet
        SP_Ctrl.Oper         <= SP_PUSH;
997 169 jshamlet
 
998
      when RTS_C1 =>
999
        CPU_Next_State       <= RTS_C2;
1000
        SP_Ctrl.Oper         <= SP_POP;
1001
 
1002
      when RTS_C2 =>
1003
        CPU_Next_State       <= RTS_C3;
1004
        -- if this is an RTI, then we need to POP the flags
1005
        if( SubOp = SOP_RTI )then
1006
          SP_Ctrl.Oper       <= SP_POP;
1007
        end if;
1008
 
1009
      when RTS_C3 =>
1010
        CPU_Next_State       <= RTS_C4;
1011
        Cache_Ctrl           <= CACHE_OPER1;
1012
 
1013
      when RTS_C4 =>
1014
        CPU_Next_State       <= RTS_C5;
1015
        Cache_Ctrl           <= CACHE_OPER2;
1016
 
1017
      when RTS_C5 =>
1018 187 jshamlet
        CPU_Next_State       <= IPF_C0;
1019 169 jshamlet
        PC_Ctrl.Oper         <= PC_LOAD;
1020 185 jshamlet
        -- if this is an RTI, then we need to clear the I bit
1021 169 jshamlet
        if( SubOp = SOP_RTI )then
1022
          CPU_Next_State     <= RTI_C6;
1023
          Cache_Ctrl         <= CACHE_OPER1;
1024 185 jshamlet
          ALU_Ctrl.Oper      <= ALU_CLP;
1025
          ALU_Ctrl.Reg       <= conv_std_logic_vector(PSR_I,3);
1026 169 jshamlet
        end if;
1027
 
1028
      when RTI_C6 =>
1029 187 jshamlet
        CPU_Next_State       <= IPF_C1;
1030 185 jshamlet
        PC_Ctrl.Offset       <= PC_NEXT;
1031 169 jshamlet
        ALU_Ctrl.Oper        <= ALU_RFLG;
1032
 
1033
      when others =>
1034
        null;
1035
    end case;
1036
 
1037
  end process;
1038
 
1039
-------------------------------------------------------------------------------
1040
-- Registered portion of CPU finite state machine
1041
-------------------------------------------------------------------------------
1042 182 jshamlet
 
1043 169 jshamlet
  CPU_Regs: process( Reset, Clock )
1044
    variable Offset_SX       : ADDRESS_TYPE;
1045 188 jshamlet
    variable i_Ints          : INTERRUPT_BUNDLE := x"00";
1046 169 jshamlet
    variable Index           : integer range 0 to 7         := 0;
1047
    variable Sum             : std_logic_vector(8 downto 0) := "000000000";
1048
    variable Temp            : std_logic_vector(8 downto 0) := "000000000";
1049
  begin
1050
    if( Reset = Reset_Level )then
1051 187 jshamlet
      CPU_State              <= IPF_C0;
1052 260 jshamlet
 
1053
      CPU_Halt_Req           <= '0';
1054
      Halt_Ack               <= '0';
1055
 
1056 169 jshamlet
      Opcode                 <= OP_INC;
1057
      SubOp                  <= ACCUM;
1058
      SubOp_p1               <= ACCUM;
1059
      Operand1               <= x"00";
1060
      Operand2               <= x"00";
1061
      Instr_Prefetch         <= '0';
1062
      Prefetch               <= x"00";
1063
 
1064 223 jshamlet
      Open8_Bus.Wr_En        <= '0';
1065
      Open8_Bus.Wr_Data      <= OPEN8_NULLBUS;
1066
      Open8_Bus.Rd_En        <= '1';
1067 169 jshamlet
 
1068
      Program_Ctr            <= Program_Start_Addr;
1069
      Stack_Ptr              <= Stack_Start_Addr;
1070
 
1071
      Ack_Q                  <= '0';
1072
      Ack_Q1                 <= '0';
1073
      Int_Ack                <= '0';
1074
 
1075
      Int_Req                <= '0';
1076
      Pending                <= x"00";
1077
      Wait_for_FSM           <= '0';
1078 210 jshamlet
      Wait_for_ISR           <= '0';
1079 245 jshamlet
      Set_Mask               <= '0';
1080 169 jshamlet
      if( Enable_NMI )then
1081
        Int_Mask             <= Default_Interrupt_Mask(7 downto 1) & '1';
1082
      else
1083
        Int_Mask             <= Default_Interrupt_Mask;
1084
      end if;
1085 254 jshamlet
      ISR_Addr_Offset        <= INT_VECTOR_0;
1086 169 jshamlet
 
1087
      for i in 0 to 7 loop
1088 188 jshamlet
        Regfile(i)           <= x"00";
1089 169 jshamlet
      end loop;
1090
      Flags                  <= x"00";
1091 248 jshamlet
      if( Supervisor_Mode )then
1092 244 jshamlet
        Flags(PSR_I)         <= '1';
1093
      end if;
1094 169 jshamlet
 
1095 224 jshamlet
      Open8_Bus.GP_Flags     <= (others => '0');
1096 188 jshamlet
 
1097 169 jshamlet
    elsif( rising_edge(Clock) )then
1098 187 jshamlet
 
1099 260 jshamlet
      CPU_State              <= CPU_Next_State;
1100
 
1101
-- Register the halt request and acknowledge lines
1102
 
1103 225 jshamlet
      CPU_Halt_Req           <= Halt_Req;
1104
      Halt_Ack               <= CPU_Halt_Ack;
1105 187 jshamlet
 
1106 169 jshamlet
-------------------------------------------------------------------------------
1107
-- Instruction/Operand caching for pipelined memory access
1108
-------------------------------------------------------------------------------
1109 260 jshamlet
 
1110
      -- To avoid putting too much load on the (usually massive) wire-OR'd bus,
1111
      --  the CPU loads Rd_Data into one of four registers - instruction,
1112
      --  operand 1 or 2, or the instruction prefetch registers. The first is
1113
      --  used to decode an instruction when the prefetch isn't valid, while
1114
      --  the two operand registers are used to hold any additional argument
1115
      --  for multi-byte instructions. Because of the memory pipelining, some
1116
      --  longer instructions can cache the next instruction as part of their
1117
      --  execution in a prefetch register, allowing the CPU to skip loading
1118
      --  it again later. Unfortunate, because instructions aren't all the same
1119
      --  length, it is not feasible to cache their operands without adding a
1120
      --  second partial decode stage that would obviate any savings.
1121
 
1122 169 jshamlet
      case Cache_Ctrl is
1123
        when CACHE_INSTR =>
1124
          Opcode             <= Rd_Data(7 downto 3);
1125
          SubOp              <= Rd_Data(2 downto 0);
1126
          SubOp_p1           <= Rd_Data(2 downto 0) + 1;
1127
          if( Instr_Prefetch = '1' )then
1128
            Opcode           <= Prefetch(7 downto 3);
1129
            SubOp            <= Prefetch(2 downto 0);
1130
            SubOp_p1         <= Prefetch(2 downto 0) + 1;
1131
            Instr_Prefetch   <= '0';
1132
          end if;
1133
 
1134
        when CACHE_OPER1 =>
1135
          Operand1           <= Rd_Data;
1136
 
1137
        when CACHE_OPER2 =>
1138
          Operand2           <= Rd_Data;
1139
 
1140
        when CACHE_PREFETCH =>
1141
          Prefetch           <= Rd_Data;
1142
          Instr_Prefetch     <= '1';
1143
 
1144
        when CACHE_IDLE =>
1145
          null;
1146
      end case;
1147
 
1148
-------------------------------------------------------------------------------
1149
-- Program Counter
1150
-------------------------------------------------------------------------------
1151 260 jshamlet
 
1152
      -- The program counter is a bit unusual in that it always subtracts two
1153
      --  from itself plus the signed offset. This is because of the way the
1154
      --  assembler works when computing branches. Thus, to "IDLE" the counter,
1155
      --  the offset is set to 2, while "NEXT" sets the offset to 3. Depending
1156
      --  on how an instruction interacts with memory, or is pipelined,  the
1157
      --  offset can vary from -1 to 3
1158
 
1159 169 jshamlet
      Offset_SX(15 downto 8) := (others => PC_Ctrl.Offset(7));
1160
      Offset_SX(7 downto 0)  := PC_Ctrl.Offset;
1161
 
1162
      case PC_Ctrl.Oper is
1163
        when PC_INCR =>
1164
          Program_Ctr        <= Program_Ctr + Offset_SX - 2;
1165
 
1166
        when PC_LOAD =>
1167 185 jshamlet
          Program_Ctr        <= Operand2 & Operand1;
1168 169 jshamlet
 
1169
        when others =>
1170
          null;
1171
      end case;
1172
 
1173
-------------------------------------------------------------------------------
1174
-- (Write) Data Path
1175
-------------------------------------------------------------------------------
1176 260 jshamlet
 
1177
      -- Note that this code handles both the Rd_En and Wr_En signals. These
1178
      --  were separated to make downstream logic simpler (As opposed to the
1179
      --  more classic RD_WRn and ADDR_STROBE scheme) It is also true to the
1180
      --  original core, which also had separate read and write enable outputs
1181
 
1182
      Open8_Bus.Wr_En        <= '0';
1183
      Open8_Bus.Wr_Data      <= OPEN8_NULLBUS;
1184
      Open8_Bus.Rd_En        <= '0';
1185
 
1186 169 jshamlet
      case DP_Ctrl.Src is
1187
        when DATA_BUS_IDLE =>
1188
          null;
1189
 
1190
        when DATA_RD_MEM =>
1191 223 jshamlet
          Open8_Bus.Rd_En    <= '1';
1192 169 jshamlet
 
1193
        when DATA_WR_REG =>
1194 223 jshamlet
          Open8_Bus.Wr_En    <= '1';
1195
          Open8_Bus.Wr_Data  <= Regfile(conv_integer(DP_Ctrl.Reg));
1196 169 jshamlet
 
1197
        when DATA_WR_FLAG =>
1198 223 jshamlet
          Open8_Bus.Wr_En    <= '1';
1199
          Open8_Bus.Wr_Data  <= Flags;
1200 169 jshamlet
 
1201
        when DATA_WR_PC =>
1202 223 jshamlet
          Open8_Bus.Wr_En    <= '1';
1203
          Open8_Bus.Wr_Data  <= Program_Ctr(15 downto 8);
1204 182 jshamlet
          if( DP_Ctrl.Reg = PC_LSB )then
1205 223 jshamlet
            Open8_Bus.Wr_Data <= Program_Ctr(7 downto 0);
1206 169 jshamlet
          end if;
1207
 
1208
        when others =>
1209
          null;
1210
      end case;
1211
 
1212
-------------------------------------------------------------------------------
1213
-- Stack Pointer
1214
-------------------------------------------------------------------------------
1215
      case SP_Ctrl.Oper is
1216
        when SP_IDLE =>
1217
          null;
1218
 
1219 181 jshamlet
        when SP_CLR =>
1220 169 jshamlet
          Stack_Ptr          <= Stack_Start_Addr;
1221
 
1222 181 jshamlet
        when SP_SET =>
1223 245 jshamlet
          if( Supervisor_Mode )then
1224
            if( Flags(PSR_I) = '1' )then
1225
              Stack_Ptr      <= Regfile(1) & Regfile(0);
1226
            end if;
1227
          else
1228
            Stack_Ptr        <= Regfile(1) & Regfile(0);
1229
          end if;
1230 181 jshamlet
 
1231 169 jshamlet
        when SP_POP  =>
1232
          Stack_Ptr          <= Stack_Ptr + 1;
1233
 
1234
        when SP_PUSH =>
1235
          Stack_Ptr          <= Stack_Ptr - 1;
1236
 
1237
        when others =>
1238
          null;
1239
 
1240
      end case;
1241
 
1242
-------------------------------------------------------------------------------
1243
-- Interrupt Controller
1244
-------------------------------------------------------------------------------
1245 245 jshamlet
 
1246
      -- If Supervisor_Mode is set, restrict the SMSK instruction such that it
1247
      --  requires the I bit to be set.
1248
      if( Supervisor_Mode )then
1249
        Set_Mask             <= INT_Ctrl.Mask_Set and Flags(PSR_I);
1250
      else
1251
        Set_Mask             <= INT_Ctrl.Mask_Set;
1252
      end if;
1253
 
1254 169 jshamlet
      -- The interrupt control mask is always sourced out of R0
1255 245 jshamlet
      if( Set_Mask = '1' )then
1256 169 jshamlet
        if( Enable_NMI )then
1257
          Int_Mask           <= Regfile(conv_integer(ACCUM))(7 downto 1) & '1';
1258
        else
1259
          Int_Mask           <= Regfile(conv_integer(ACCUM));
1260
        end if;
1261
      end if;
1262
 
1263
      -- Combine external and internal interrupts, and mask the OR of the two
1264
      --  with the mask. Record any incoming interrupts to the pending buffer
1265
      i_Ints                 := (Interrupts or INT_Ctrl.Soft_Ints) and
1266
                                Int_Mask;
1267 172 jshamlet
 
1268 169 jshamlet
      Pending                <= i_Ints or Pending;
1269
 
1270 260 jshamlet
      -- If Sequential_Interrupts is set true, Wait_for_ISR should follow the
1271
      --  I bit, preventing a new interrupt from starting until the I bit is
1272
      --  cleared.
1273 210 jshamlet
      if( Sequential_Interrupts )then
1274
        Wait_for_ISR         <= Flags(PSR_I);
1275
      else
1276
        Wait_for_ISR         <= '0';
1277
      end if;
1278
 
1279
      if( Wait_for_FSM = '0' and Wait_for_ISR = '0' )then
1280 169 jshamlet
        if(    Pending(0) = '1' )then
1281 254 jshamlet
          ISR_Addr_Offset    <= INT_VECTOR_0;
1282 169 jshamlet
          Pending(0)         <= '0';
1283
        elsif( Pending(1) = '1' )then
1284 254 jshamlet
          ISR_Addr_Offset    <= INT_VECTOR_1;
1285 169 jshamlet
          Pending(1)         <= '0';
1286
        elsif( Pending(2) = '1' )then
1287 254 jshamlet
          ISR_Addr_Offset    <= INT_VECTOR_2;
1288 169 jshamlet
          Pending(2)         <= '0';
1289
        elsif( Pending(3) = '1' )then
1290 254 jshamlet
          ISR_Addr_Offset    <= INT_VECTOR_3;
1291 169 jshamlet
          Pending(3)         <= '0';
1292
        elsif( Pending(4) = '1' )then
1293 254 jshamlet
          ISR_Addr_Offset    <= INT_VECTOR_4;
1294 169 jshamlet
          Pending(4)         <= '0';
1295
        elsif( Pending(5) = '1' )then
1296 254 jshamlet
          ISR_Addr_Offset    <= INT_VECTOR_5;
1297 169 jshamlet
          Pending(5)         <= '0';
1298
        elsif( Pending(6) = '1' )then
1299 254 jshamlet
          ISR_Addr_Offset    <= INT_VECTOR_6;
1300 169 jshamlet
          Pending(6)         <= '0';
1301
        elsif( Pending(7) = '1' )then
1302 254 jshamlet
          ISR_Addr_Offset    <= INT_VECTOR_7;
1303 169 jshamlet
          Pending(7)         <= '0';
1304
        end if;
1305 185 jshamlet
        Wait_for_FSM         <= or_reduce(Pending);
1306 169 jshamlet
      end if;
1307
 
1308
      -- Reset the Wait_for_FSM flag on Int_Ack
1309
      Ack_Q                  <= Ack_D;
1310
      Ack_Q1                 <= Ack_Q;
1311
      Int_Ack                <= Ack_Q1;
1312
      if( Int_Ack = '1' )then
1313
        Wait_for_FSM         <= '0';
1314
      end if;
1315
 
1316
      Int_Req                <= Wait_for_FSM and (not Int_Ack);
1317
 
1318
      -- Incr_ISR allows the CPU Core to advance the vector address to pop the
1319
      --  lower half of the address.
1320
      if( INT_Ctrl.Incr_ISR = '1' )then
1321 254 jshamlet
        ISR_Addr_Offset             <= ISR_Addr_Offset + 1;
1322 169 jshamlet
      end if;
1323
 
1324
-------------------------------------------------------------------------------
1325
-- ALU (Arithmetic / Logic Unit)
1326
-------------------------------------------------------------------------------
1327 260 jshamlet
 
1328
      -- The ALU code is responsible for (and should be the only code altering)
1329
      --  the register file. Most of the "instructions" directly map to opcodes
1330
      --  but a few are for internal use only, such as operations involving the
1331 263 jshamlet
      --  stack pointer or interrupt mask.
1332 260 jshamlet
 
1333 169 jshamlet
      Index                  := conv_integer(ALU_Ctrl.Reg);
1334
      Sum                    := (others => '0');
1335
      Temp                   := (others => '0');
1336
 
1337
      case ALU_Ctrl.Oper is
1338
        when ALU_INC => -- Rn = Rn + 1 : Flags N,C,Z
1339
          Sum                := ("0" & x"01") +
1340
                                ("0" & Regfile(Index));
1341 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1342
          Flags(PSR_C)       <= Sum(8);
1343 209 jshamlet
          Flags(PSR_N)       <= Sum(7);
1344 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1345
 
1346
        when ALU_UPP => -- Rn = Rn + 1
1347
          Sum                := ("0" & x"01") +
1348
                                ("0" & Regfile(Index));
1349 185 jshamlet
          Flags(PSR_C)       <= Sum(8);
1350 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1351
 
1352
        when ALU_UPP2 => -- Rn = Rn + C
1353 263 jshamlet
          Sum                := (x"00" & Flags(PSR_C)) +
1354
                                ("0" & Regfile(Index));
1355 185 jshamlet
          Flags(PSR_C)       <= Sum(8);
1356 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1357
 
1358
        when ALU_ADC => -- R0 = R0 + Rn + C : Flags N,C,Z
1359
          Sum                := ("0" & Regfile(0)) +
1360
                                ("0" & Regfile(Index)) +
1361 185 jshamlet
                                Flags(PSR_C);
1362
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1363
          Flags(PSR_C)       <= Sum(8);
1364
          Flags(PSR_N)       <= Sum(7);
1365 169 jshamlet
          Regfile(0)         <= Sum(7 downto 0);
1366
 
1367
        when ALU_TX0 => -- R0 = Rn : Flags N,Z
1368
          Temp               := "0" & Regfile(Index);
1369 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1370
          Flags(PSR_N)       <= Temp(7);
1371 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1372
 
1373
        when ALU_OR  => -- R0 = R0 | Rn : Flags N,Z
1374
          Temp(7 downto 0)   := Regfile(0) or Regfile(Index);
1375 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1376
          Flags(PSR_N)       <= Temp(7);
1377 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1378
 
1379
        when ALU_AND => -- R0 = R0 & Rn : Flags N,Z
1380
          Temp(7 downto 0)   := Regfile(0) and Regfile(Index);
1381 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1382
          Flags(PSR_N)       <= Temp(7);
1383 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1384
 
1385
        when ALU_XOR => -- R0 = R0 ^ Rn : Flags N,Z
1386
          Temp(7 downto 0)   := Regfile(0) xor Regfile(Index);
1387 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1388
          Flags(PSR_N)       <= Temp(7);
1389 169 jshamlet
          Regfile(0)         <= Temp(7 downto 0);
1390
 
1391
        when ALU_ROL => -- Rn = Rn<<1,C : Flags N,C,Z
1392 185 jshamlet
          Temp               := Regfile(Index) & Flags(PSR_C);
1393
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1394
          Flags(PSR_C)       <= Temp(8);
1395
          Flags(PSR_N)       <= Temp(7);
1396 169 jshamlet
          Regfile(Index)     <= Temp(7 downto 0);
1397
 
1398
        when ALU_ROR => -- Rn = C,Rn>>1 : Flags N,C,Z
1399 185 jshamlet
          Temp               := Regfile(Index)(0) & Flags(PSR_C) &
1400 169 jshamlet
                                Regfile(Index)(7 downto 1);
1401 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1402
          Flags(PSR_C)       <= Temp(8);
1403
          Flags(PSR_N)       <= Temp(7);
1404 169 jshamlet
          Regfile(Index)     <= Temp(7 downto 0);
1405
 
1406
        when ALU_DEC => -- Rn = Rn - 1 : Flags N,C,Z
1407
          Sum                := ("0" & Regfile(Index)) +
1408
                                ("0" & x"FF");
1409 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1410
          Flags(PSR_C)       <= Sum(8);
1411
          Flags(PSR_N)       <= Sum(7);
1412 169 jshamlet
          Regfile(Index)     <= Sum(7 downto 0);
1413
 
1414
        when ALU_SBC => -- Rn = R0 - Rn - C : Flags N,C,Z
1415
          Sum                := ("0" & Regfile(0)) +
1416
                                ("1" & (not Regfile(Index))) +
1417 185 jshamlet
                                Flags(PSR_C);
1418
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1419
          Flags(PSR_C)       <= Sum(8);
1420
          Flags(PSR_N)       <= Sum(7);
1421 169 jshamlet
          Regfile(0)         <= Sum(7 downto 0);
1422
 
1423
        when ALU_ADD => -- R0 = R0 + Rn : Flags N,C,Z
1424
          Sum                := ("0" & Regfile(0)) +
1425
                                ("0" & Regfile(Index));
1426 185 jshamlet
          Flags(PSR_C)       <= Sum(8);
1427 169 jshamlet
          Regfile(0)         <= Sum(7 downto 0);
1428 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1429
          Flags(PSR_N)       <= Sum(7);
1430 169 jshamlet
 
1431
        when ALU_STP => -- Sets bit(n) in the Flags register
1432
          Flags(Index)       <= '1';
1433
 
1434
        when ALU_BTT => -- Z = !R0(N), N = R0(7)
1435 185 jshamlet
          Flags(PSR_Z)       <= not Regfile(0)(Index);
1436
          Flags(PSR_N)       <= Regfile(0)(7);
1437 169 jshamlet
 
1438
        when ALU_CLP => -- Clears bit(n) in the Flags register
1439
          Flags(Index)       <= '0';
1440
 
1441
        when ALU_T0X => -- Rn = R0 : Flags N,Z
1442
          Temp               := "0" & Regfile(0);
1443 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Temp(7 downto 0));
1444
          Flags(PSR_N)       <= Temp(7);
1445 169 jshamlet
          Regfile(Index)     <= Temp(7 downto 0);
1446
 
1447
        when ALU_CMP => -- Sets Flags on R0 - Rn : Flags N,C,Z
1448
          Sum                := ("0" & Regfile(0)) +
1449
                                ("1" & (not Regfile(Index))) +
1450
                                '1';
1451 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Sum(7 downto 0));
1452
          Flags(PSR_C)       <= Sum(8);
1453
          Flags(PSR_N)       <= Sum(7);
1454 169 jshamlet
 
1455
        when ALU_MUL => -- Stage 1 of 2 {R1:R0} = R0 * Rn : Flags Z
1456
          Regfile(0)         <= Mult(7 downto 0);
1457
          Regfile(1)         <= Mult(15 downto 8);
1458 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Mult);
1459 169 jshamlet
 
1460
        when ALU_LDI => -- Rn <= Data : Flags N,Z
1461 185 jshamlet
          Flags(PSR_Z)       <= nor_reduce(Operand1);
1462
          Flags(PSR_N)       <= Operand1(7);
1463
          Regfile(Index)     <= Operand1;
1464 169 jshamlet
 
1465
        when ALU_POP => -- Rn <= Data
1466 185 jshamlet
          Regfile(Index)     <= Operand1;
1467 169 jshamlet
 
1468
        when ALU_RFLG =>
1469 188 jshamlet
          Flags(3 downto 0)  <= Operand1(3 downto 0);
1470
          if( not RTI_Ignores_GP_Flags )then
1471
            Flags(7 downto 4)<= Operand1(7 downto 4);
1472
          end if;
1473 169 jshamlet
 
1474 185 jshamlet
        when ALU_RSP =>
1475 181 jshamlet
          Regfile(0)         <= Stack_Ptr(7 downto 0);
1476
          Regfile(1)         <= Stack_Ptr(15 downto 8);
1477
 
1478 185 jshamlet
        when ALU_GMSK =>
1479
          Flags(PSR_Z)       <= nor_reduce(Int_Mask);
1480
          Regfile(0)         <= Int_Mask;
1481
 
1482 169 jshamlet
        when others =>
1483
          null;
1484
      end case;
1485
 
1486 224 jshamlet
      Open8_Bus.GP_Flags     <= Flags(7 downto 3);
1487 188 jshamlet
 
1488 169 jshamlet
    end if;
1489
  end process;
1490
 
1491 182 jshamlet
-------------------------------------------------------------------------------
1492
-- Multiplier Logic
1493
--
1494
-- We need to infer a hardware multipler, so we create a special clocked
1495
--  process with no reset or clock enable
1496
-------------------------------------------------------------------------------
1497
 
1498
  Multiplier_proc: process( Clock )
1499
  begin
1500
    if( rising_edge(Clock) )then
1501
      Mult                   <= Regfile(0) *
1502 186 jshamlet
                                Regfile(conv_integer(ALU_Ctrl.Reg));
1503
    end if;
1504
  end process;
1505
 
1506
end architecture;

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