OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_pwm16.vhd] - Blame information for rev 217

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 214 jshamlet
-- Copyright (c)2018, 2020 Jeremy Seth Henry
2
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23
--
24
-- VHDL Units :  o8_pwm16
25
-- Description:  Provides a 16-bit standard PWM output with 1 uSec resolution,
26
--                as well as CPU interrupt on overflow. Note that the PWM
27
--                timers reload from registers on overflow, not on write
28
--
29
-- Register Map:
30
-- Offset  Bitfield Description                        Read/Write
31
--   0x00  AAAAAAAA Period (lower byte)                  (RW)
32
--   0x01  AAAAAAAA Period (upper byte)                  (RW)
33
--   0x02  AAAAAAAA Width (lower byte)                   (RW)
34
--   0x03  AAAAAAAA Width (upper byte)                   (RW)
35
--   0x04  A------- Timer Status                         (RW)
36
--                  A: Enabled on '1' / Disable on '0'
37
--
38
-- Revision History
39
-- Author          Date     Change
40
------------------ -------- ---------------------------------------------------
41
-- Seth Henry      04/25/18 Design Start
42
-- Seth Henry      04/10/20 Code cleanup and comments
43
 
44
library ieee;
45
  use ieee.std_logic_1164.all;
46
  use ieee.std_logic_unsigned.all;
47
  use ieee.std_logic_misc.all;
48
 
49
library work;
50
  use work.open8_pkg.all;
51
 
52
entity o8_pwm16 is
53
generic(
54 217 jshamlet
  Reset_Level                : std_logic;
55
  Address                    : ADDRESS_TYPE
56 214 jshamlet
);
57
port(
58 217 jshamlet
  Clock                      : in  std_logic;
59
  Reset                      : in  std_logic;
60
  uSec_Tick                  : in  std_logic;
61 214 jshamlet
  --
62 217 jshamlet
  PWM_Out                    : out std_logic;
63 214 jshamlet
  -- Bus interface
64 217 jshamlet
  Bus_Address                : in  ADDRESS_TYPE;
65
  Wr_Enable                  : in  std_logic;
66
  Wr_Data                    : in  DATA_TYPE;
67
  Rd_Enable                  : in  std_logic;
68
  Rd_Data                    : out DATA_TYPE;
69
  Interrupt                  : out std_logic
70 214 jshamlet
);
71
end entity;
72
 
73
architecture behave of o8_pwm16 is
74
 
75 217 jshamlet
  constant User_Addr         : std_logic_vector(15 downto 3) :=
76
                                Address(15 downto 3);
77 214 jshamlet
 
78 217 jshamlet
  alias  Comp_Addr           is Bus_Address(15 downto 3);
79
  signal Addr_Match          : std_logic := '0';
80 214 jshamlet
 
81 217 jshamlet
  alias  Reg_Addr            is Bus_Address(2 downto 0);
82
  signal Reg_Addr_q          : std_logic_vector(2 downto 0) := (others => '0');
83 214 jshamlet
 
84 217 jshamlet
  signal Wr_En               : std_logic := '0';
85
  signal Wr_Data_q           : DATA_TYPE := x"00";
86
  signal Rd_En               : std_logic := '0';
87 214 jshamlet
 
88 217 jshamlet
  signal PWM_Enable          : std_logic := '0';
89
  signal PWM_Period          : std_logic_vector(15 downto 0) := (others => '0');
90
  alias  PWM_Period_l        is PWM_Period(7 downto 0);
91
  alias  PWM_Period_u        is PWM_Period(15 downto 8);
92 214 jshamlet
 
93 217 jshamlet
  signal PWM_Width           : std_logic_vector(15 downto 0) := (others => '0');
94
  alias  PWM_Width_l         is PWM_Width(7 downto 0);
95
  alias  PWM_Width_u         is PWM_Width(15 downto 8);
96 214 jshamlet
 
97 217 jshamlet
  signal Period_Ctr          : std_logic_vector(15 downto 0) := (others => '0');
98
  signal Width_Ctr           : std_logic_vector(15 downto 0) := (others => '0');
99 214 jshamlet
 
100
begin
101
 
102 217 jshamlet
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
103 214 jshamlet
 
104
  PWM_proc: process( Clock, Reset )
105
  begin
106
    if( Reset = Reset_Level )then
107 217 jshamlet
      Wr_Data_q              <= (others => '0');
108
      Reg_Addr_q             <= (others => '0');
109
      Wr_En                  <= '0';
110
      Rd_En                  <= '0';
111
      Rd_Data                <= x"00";
112
      Interrupt              <= '0';
113 214 jshamlet
 
114 217 jshamlet
      PWM_Enable             <= '0';
115
      PWM_Period             <= (others => '0');
116
      PWM_Width              <= (others => '0');
117 214 jshamlet
 
118 217 jshamlet
      Period_Ctr             <= (others => '0');
119
      Width_Ctr              <= (others => '0');
120
      PWM_Out                <= '0';
121 214 jshamlet
    elsif( rising_edge(Clock) )then
122 217 jshamlet
      Reg_Addr_q             <= Reg_Addr;
123
      Wr_Data_q              <= Wr_Data;
124
      Wr_En                  <= Addr_Match and Wr_Enable;
125 214 jshamlet
 
126
      if( Wr_En = '1' )then
127
        case( Reg_Addr_q )is
128
          when "000" =>
129 217 jshamlet
            PWM_Period_l     <= Wr_Data_q;
130 214 jshamlet
          when "001" =>
131 217 jshamlet
            PWM_Period_u     <= Wr_Data_q;
132 214 jshamlet
          when "010" =>
133 217 jshamlet
            PWM_Width_l      <= Wr_Data_q;
134 214 jshamlet
          when "011" =>
135 217 jshamlet
            PWM_Width_u      <= Wr_Data_q;
136 214 jshamlet
          when "100" | "101" | "110" | "111" =>
137 217 jshamlet
            PWM_Enable       <= Wr_Data_q(7);
138 214 jshamlet
          when others => null;
139
        end case;
140
      end if;
141
 
142 217 jshamlet
      Rd_Data                <= (others => '0');
143
      Rd_En                  <= Addr_Match and Rd_Enable;
144 214 jshamlet
      if( Rd_En = '1' )then
145
        case( Reg_Addr_q )is
146
          when "000" =>
147 217 jshamlet
            Rd_Data          <= PWM_Period_l;
148 214 jshamlet
          when "001" =>
149 217 jshamlet
            Rd_Data          <= PWM_Period_u;
150 214 jshamlet
          when "010" =>
151 217 jshamlet
            Rd_Data          <= PWM_Width_l;
152 214 jshamlet
          when "011" =>
153 217 jshamlet
            Rd_Data          <= PWM_Width_u;
154 214 jshamlet
          when "100" | "101" | "110" | "111" =>
155 217 jshamlet
            Rd_Data          <= PWM_Enable & "0000000";
156 214 jshamlet
          when others => null;
157
        end case;
158
      end if;
159
 
160 217 jshamlet
      Interrupt              <= '0';
161
      Period_Ctr             <= Period_Ctr - uSec_tick;
162
      Width_Ctr              <= Width_Ctr - uSec_tick;
163 214 jshamlet
 
164
      -- Stop the width counter from rolling over at 0
165
      if( or_reduce(Width_Ctr) = '0' )then
166 217 jshamlet
        Width_Ctr            <= (others => '0');
167 214 jshamlet
      end if;
168 217 jshamlet
 
169 214 jshamlet
      -- Reload both counters when period reaches 0
170
      if( or_reduce(Period_Ctr) = '0' )then
171 217 jshamlet
        Period_Ctr           <= PWM_Period;
172
        Width_Ctr            <= PWM_Width;
173
        Interrupt            <= '1';
174 214 jshamlet
      end if;
175
 
176
      -- Drive the output high as long as Width > 0 and PWM_Enable is high
177 217 jshamlet
      PWM_Out                <= or_reduce(Width_Ctr) and PWM_Enable;
178 214 jshamlet
 
179
      -- If the counter is disabled, reload the counters, and drive the output
180
      --  low.
181
      if( PWM_Enable = '0' )then
182 217 jshamlet
        Period_Ctr           <= PWM_Period;
183
        Width_Ctr            <= PWM_Width;
184
        Interrupt            <= '0';
185 214 jshamlet
      end if;
186
 
187
    end if;
188
  end process;
189
 
190
end architecture;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.