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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_vdsm8.vhd] - Blame information for rev 167

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1 167 jshamlet
-- Copyright (c)2013 Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--     * Redistributions of source code must retain the above copyright
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--       notice, this list of conditions and the following disclaimer.
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--     * Redistributions in binary form must reproduce the above copyright
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--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
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--       where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- VHDL Units :  o8_vdsm8
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-- Description:  8-bit variable delta-sigma modulator. Requires Open8_pkg.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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library work;
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  use work.open8_pkg.all;
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entity o8_vdsm8 is
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generic(
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  Reset_Level           : std_logic;
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  Address               : ADDRESS_TYPE
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);
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port(
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  Clock                 : in  std_logic;
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  Reset                 : in  std_logic;
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  --
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  Bus_Address           : in  ADDRESS_TYPE;
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  Wr_Enable             : in  std_logic;
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  Wr_Data               : in  DATA_TYPE;
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  Rd_Enable             : in  std_logic;
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  Rd_Data               : out DATA_TYPE;
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  --
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  DACout                : out std_logic
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);
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end entity;
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architecture behave of o8_vdsm8 is
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  function ceil_log2 (x : in natural) return natural is
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    variable retval     : natural;
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  begin
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    retval              := 1;
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    while ((2**retval) - 1) < x loop
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      retval            := retval + 1;
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    end loop;
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    return retval;
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  end function;
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  constant User_Addr    : std_logic_vector(15 downto 0) := Address;
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  alias  Comp_Addr      is Bus_Address(15 downto 0);
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  signal Addr_Match     : std_logic;
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  signal Wr_En          : std_logic;
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  signal Wr_Data_q      : DATA_TYPE;
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  signal Rd_En          : std_logic;
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  signal DACin          : DATA_TYPE;
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  -- DAC WIDTH = 8 is fixed, with all constants normalized
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  --  against 256 (the MAX PERIOD)
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  constant DAC_WIDTH    : integer := 8;
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  constant DELTA_1_I    : integer := 1;
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  constant DELTA_2_I    : integer := 5;
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  constant DELTA_3_I    : integer := 25;
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  constant DELTA_4_I    : integer := 75;
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  constant DELTA_5_I    : integer := 125;
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  constant DELTA_6_I    : integer := 195;
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  constant DELTA_1      : std_logic_vector(DAC_WIDTH - 1 downto 0) :=
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                           conv_std_logic_vector(DELTA_1_I, DAC_WIDTH);
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  constant DELTA_2      : std_logic_vector(DAC_WIDTH - 1 downto 0) :=
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                           conv_std_logic_vector(DELTA_2_I, DAC_WIDTH);
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  constant DELTA_3      : std_logic_vector(DAC_WIDTH - 1 downto 0) :=
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                           conv_std_logic_vector(DELTA_3_I, DAC_WIDTH);
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  constant DELTA_4      : std_logic_vector(DAC_WIDTH - 1 downto 0) :=
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                           conv_std_logic_vector(DELTA_4_I, DAC_WIDTH);
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  constant DELTA_5      : std_logic_vector(DAC_WIDTH - 1 downto 0) :=
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                           conv_std_logic_vector(DELTA_5_I, DAC_WIDTH);
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  constant DELTA_6      : std_logic_vector(DAC_WIDTH - 1 downto 0) :=
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                           conv_std_logic_vector(DELTA_6_I, DAC_WIDTH);
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  constant MAX_PERIOD   : integer := 2**DAC_WIDTH;
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  constant DIV_WIDTH    : integer := 2 * DAC_WIDTH;
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  constant PADJ_1_I     : integer := DELTA_1_I * MAX_PERIOD;
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  constant PADJ_2_I     : integer := DELTA_2_I * MAX_PERIOD;
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  constant PADJ_3_I     : integer := DELTA_3_I * MAX_PERIOD;
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  constant PADJ_4_I     : integer := DELTA_4_I * MAX_PERIOD;
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  constant PADJ_5_I     : integer := DELTA_5_I * MAX_PERIOD;
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  constant PADJ_6_I     : integer := DELTA_6_I * MAX_PERIOD;
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  constant PADJ_1       : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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                           conv_std_logic_vector(PADJ_1_I,DIV_WIDTH);
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  constant PADJ_2       : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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                           conv_std_logic_vector(PADJ_2_I,DIV_WIDTH);
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  constant PADJ_3       : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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                           conv_std_logic_vector(PADJ_3_I,DIV_WIDTH);
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  constant PADJ_4       : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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                           conv_std_logic_vector(PADJ_4_I,DIV_WIDTH);
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  constant PADJ_5       : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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                           conv_std_logic_vector(PADJ_5_I,DIV_WIDTH);
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  constant PADJ_6       : std_logic_vector(DIV_WIDTH-1 downto 0) :=
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                           conv_std_logic_vector(PADJ_6_I,DIV_WIDTH);
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  signal DACin_q        : DATA_TYPE;
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  signal Divisor        : std_logic_vector(DIV_WIDTH-1 downto 0);
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  signal Dividend       : std_logic_vector(DIV_WIDTH-1 downto 0);
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  signal q              : std_logic_vector(DIV_WIDTH*2-1 downto 0);
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  signal diff           : std_logic_vector(DIV_WIDTH downto 0);
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  constant CB           : integer := ceil_log2(DIV_WIDTH);
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  signal count          : std_logic_vector(CB-1 downto 0);
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  signal Next_Width     : DATA_TYPE;
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  signal Next_Period    : DATA_TYPE;
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  signal PWM_Width      : DATA_TYPE;
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  signal PWM_Period     : DATA_TYPE;
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  signal Width_Ctr      : DATA_TYPE;
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  signal Period_Ctr     : DATA_TYPE;
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begin
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  Addr_Match            <= '1' when Comp_Addr = User_Addr else '0';
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  io_reg: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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       Wr_En             <= '0';
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      Wr_Data_q         <= x"00";
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      Rd_En             <= '0';
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      Rd_Data           <= x"00";
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        DACin             <= x"00";
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    elsif( rising_edge( Clock ) )then
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      Wr_En             <= Addr_Match and Wr_Enable;
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      Wr_Data_q         <= Wr_Data;
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      if( Wr_En = '1' )then
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          DACin           <= Wr_Data_q;
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        end if;
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      Rd_Data           <= (others => '0');
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      Rd_En             <= Addr_Match and Rd_Enable;
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      if( Rd_En = '1' )then
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        Rd_Data         <= DACin;
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      end if;
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    end if;
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  end process;
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  diff                  <= ('0' & q(DIV_WIDTH*2-2 downto DIV_WIDTH-1)) -
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                           ('0' & Divisor);
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  Dividend   <= PADJ_2 when DACin_q >= DELTA_2_I and DACin_q < DELTA_3_I else
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                PADJ_3 when DACin_q >= DELTA_3_I and DACin_q < DELTA_4_I else
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                PADJ_4 when DACin_q >= DELTA_4_I and DACin_q < DELTA_5_I else
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                PADJ_5 when DACin_q >= DELTA_5_I and DACin_q < DELTA_6_I else
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                PADJ_6 when DACin_q >= DELTA_6_I else
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                PADJ_1;
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  Next_Width <= DELTA_1 when DACin_q >= DELTA_1_I and DACin_q < DELTA_2_I else
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                DELTA_2 when DACin_q >= DELTA_2_I and DACin_q < DELTA_3_I else
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                DELTA_3 when DACin_q >= DELTA_3_I and DACin_q < DELTA_4_I else
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                DELTA_4 when DACin_q >= DELTA_4_I and DACin_q < DELTA_5_I else
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                DELTA_5 when DACin_q >= DELTA_5_I and DACin_q < DELTA_6_I else
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                DELTA_6 when DACin_q >= DELTA_6_I else
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                (others => '0');
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  Next_Period           <= q(7 downto 0) - 1;
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  vDSM_proc: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      q                 <= (others => '0');
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      count             <= (others => '1');
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      Divisor           <= (others => '0');
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      DACin_q           <= (others => '0');
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      PWM_Width         <= (others => '0');
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      PWM_Period        <= (others => '0');
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      Period_Ctr        <= (others => '0');
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      Width_Ctr         <= (others => '0');
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      DACout            <= '0';
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    elsif( rising_edge(Clock) )then
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      q                 <= diff(DIV_WIDTH-1 downto 0) &
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                           q(DIV_WIDTH-2 downto 0) & '1';
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      if( diff(DIV_WIDTH) = '1' )then
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        q               <= q(DIV_WIDTH*2-2 downto 0) & '0';
206
      end if;
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      count             <= count + 1;
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      if( count = DIV_WIDTH )then
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        PWM_Width       <= Next_Width;
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        PWM_Period      <= Next_Period;
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        DACin_q         <= DACin;
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        Divisor         <= (others => '0');
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        Divisor(7 downto 0) <= DACin_q;
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        q               <= conv_std_logic_vector(0,DIV_WIDTH) & Dividend;
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        count           <= (others => '0');
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      end if;
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      Period_Ctr        <= Period_Ctr - 1;
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      Width_Ctr         <= Width_Ctr - 1;
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      DACout            <= '1';
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      if( Width_Ctr = 0 )then
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        DACout          <= '0';
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        Width_Ctr       <= (others => '0');
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      end if;
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228
      if( Period_Ctr = 0 )then
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        Period_Ctr      <= PWM_Period;
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        Width_Ctr       <= PWM_Width;
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      end if;
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233
    end if;
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  end process;
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end architecture;

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