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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_vector_rx.vhd] - Blame information for rev 244

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1 240 jshamlet
-- Copyright (c)2020 Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--     * Redistributions of source code must retain the above copyright
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--       notice, this list of conditions and the following disclaimer.
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--     * Redistributions in binary form must reproduce the above copyright
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--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
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--       where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- VHDL Entity: o8_vector_rx
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-- Description: Receives a 6-bit vector command and 16-bit argument from the
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--               vector_tx entity. Issues interrupt to the CPU on receipt of
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--               three bytes.
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--
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-- Register Map:
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-- Offset  Bitfield Description                        Read/Write
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--   0x0   --AAAAAA Vector Select
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--   0x1   AAAAAAAA Vector Argument LB
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--   0x2   AAAAAAAA Vector Argument UB
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--
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-- Revision History
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-- Author          Date     Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry      04/15/20 Created from o8_epoch_timer due to requirement
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--                           change.
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-- Seth Henry      04/16/20 Modified to make use of Open8 bus record
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-- Seth Henry      05/06/20 Modified to eliminate request line and detect idle
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--                           conditions instead
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library ieee;
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  use ieee.std_logic_1164.all;
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  use ieee.std_logic_unsigned.all;
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  use ieee.std_logic_arith.all;
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  use ieee.std_logic_misc.all;
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library work;
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  use work.Open8_pkg.all;
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entity o8_vector_rx is
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generic(
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  Bit_Rate                   : real;
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  Enable_Parity              : boolean;
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  Parity_Odd_Even_n          : std_logic;
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  Clock_Frequency            : real;
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  Address                    : ADDRESS_TYPE
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);
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port(
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  Open8_Bus                  : in  OPEN8_BUS_TYPE;
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  Rd_Data                    : out DATA_TYPE;
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  Interrupt                  : out std_logic;
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  --
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  Rx_In                      : in  std_logic
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);
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end entity;
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architecture behave of o8_vector_rx is
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  alias Clock                is Open8_Bus.Clock;
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  alias Reset                is Open8_Bus.Reset;
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  constant User_Addr         : std_logic_vector(15 downto 2) :=
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                                Address(15 downto 2);
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  alias  Comp_Addr           is Open8_Bus.Address(15 downto 2);
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  signal Addr_Match          : std_logic := '0';
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80 244 jshamlet
  alias  Reg_Sel_d           is Open8_Bus.Address(1 downto 0);
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  signal Reg_Sel_q           : std_logic_vector(1 downto 0) := "00";
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  signal Rd_En_d             : std_logic := '0';
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  signal Rd_En_q             : std_logic := '0';
84 240 jshamlet
 
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  constant BAUD_RATE_DIV     : integer := integer(Clock_Frequency / Bit_Rate);
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  -- Period of each bit in sub-clocks (subtract one to account for zero)
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  constant Full_Per_i        : integer := BAUD_RATE_DIV - 1;
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  constant Baud_Bits         : integer := ceil_log2(Full_Per_i);
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  constant FULL_PERIOD       : std_logic_vector(Baud_Bits - 1 downto 0) :=
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                                 conv_std_logic_vector(Full_Per_i, Baud_Bits);
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  signal Rx_Baud_Cntr        : std_logic_vector(Baud_Bits - 1 downto 0) :=
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                                 (others => '0');
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  signal Rx_Baud_Tick        : std_logic;
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  signal Rx_In_SR            : std_logic_vector(2 downto 0);
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  alias  Rx_In_MS            is Rx_In_SR(2);
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  signal Rx_Idle_Cntr        : std_logic_vector(3 downto 0);
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  signal RX_Idle             : std_logic;
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  type VECTOR_RX_STATES is ( GET_VECTOR_CMD, GET_VECTOR_ARG_LB, GET_VECTOR_ARG_UB,
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                             SEND_INTERRUPT );
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  signal Vector_State        : VECTOR_RX_STATES := GET_VECTOR_CMD;
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  signal Vector_Cmd          : DATA_TYPE := x"00";
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  signal Vector_Arg_LB       : DATA_TYPE := x"00";
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  signal Vector_Arg_UB       : DATA_TYPE := x"00";
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  signal Rx_Data             : DATA_TYPE := x"00";
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  signal Rx_Valid            : std_logic;
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begin
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  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
117 244 jshamlet
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
118 240 jshamlet
 
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  io_reg: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
122 244 jshamlet
      Reg_Sel_q         <= (others => '0');
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      Rd_En_q           <= '0';
124 240 jshamlet
      Rd_Data           <= OPEN8_NULLBUS;
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    elsif( rising_edge( Clock ) )then
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      Reg_Sel_q         <= Reg_Sel_d;
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128 240 jshamlet
      Rd_Data           <= OPEN8_NULLBUS;
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      Rd_En_q           <= Rd_En_d;
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      if( Rd_En_q = '1'  )then
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        case( Reg_Sel_q )is
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          when "00" =>
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            Rd_Data     <= Vector_Cmd;
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          when "01" =>
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            Rd_Data     <= Vector_Arg_LB;
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          when "10" =>
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            Rd_Data     <= Vector_Arg_UB;
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          when others =>
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            null;
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      end case;
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      end if;
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    end if;
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  end process;
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  RX_Idle_proc: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      Rx_Baud_Cntr     <= (others => '0');
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      Rx_Baud_Tick     <= '0';
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      Rx_In_SR         <= (others => '1');
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      Rx_Idle_Cntr     <= (others => '0');
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      Rx_Idle          <= '0';
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    elsif( rising_edge(Clock) )then
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      Rx_Baud_Cntr     <= Rx_Baud_Cntr - 1;
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      Rx_Baud_Tick     <= '0';
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      if( Rx_Baud_Cntr = 0 )then
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        Rx_Baud_Cntr   <= FULL_PERIOD;
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        Rx_Baud_Tick   <= '1';
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      end if;
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      Rx_In_SR         <= Rx_In_SR(1 downto 0) & Rx_In;
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      Rx_Idle_Cntr     <= Rx_Idle_Cntr - Rx_Baud_Tick;
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      if( Rx_In_MS = '0' )then
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        Rx_Idle_Cntr   <= (others => '1');
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      elsif( Rx_Idle_Cntr = 0 )then
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        Rx_Idle_Cntr   <= (others => '0');
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      end if;
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      Rx_Idle          <= nor_reduce(Rx_Idle_Cntr);
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    end if;
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  end process;
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  U_RX : entity work.async_ser_rx
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  generic map(
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    Reset_Level              => Reset_Level,
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    Enable_Parity            => Enable_Parity,
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    Parity_Odd_Even_n        => Parity_Odd_Even_n,
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    Clock_Divider            => BAUD_RATE_DIV
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  )
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  port map(
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    Clock                    => Clock,
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    Reset                    => Reset,
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    --
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    Rx_In                    => RX_In,
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    --
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    Rx_Data                  => RX_Data,
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    Rx_Valid                 => RX_Valid,
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    Rx_PErr                  => open
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  );
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  Vector_RX_proc: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      Vector_State           <= GET_VECTOR_CMD;
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      Vector_Cmd             <= x"00";
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      Vector_Arg_LB          <= x"00";
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      Vector_Arg_UB          <= x"00";
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      Interrupt              <= '0';
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    elsif( rising_edge(Clock) )then
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      Interrupt              <= '0';
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      case( Vector_State )is
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        when GET_VECTOR_CMD =>
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          if( Rx_Valid = '1' )then
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            Vector_Cmd       <= Rx_Data;
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            Vector_State     <= GET_VECTOR_ARG_LB;
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          end if;
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        when GET_VECTOR_ARG_LB =>
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          if( Rx_Valid = '1' )then
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            Vector_Arg_LB    <= Rx_Data;
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            Vector_State     <= GET_VECTOR_ARG_UB;
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          end if;
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        when GET_VECTOR_ARG_UB =>
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          if( Rx_Valid = '1' )then
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            Vector_Arg_UB    <= Rx_Data;
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            Vector_State     <= SEND_INTERRUPT;
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          end if;
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        when SEND_INTERRUPT =>
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          Interrupt          <= '1';
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          Vector_State       <= GET_VECTOR_CMD;
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        when others => null;
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      end case;
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      if( Rx_Idle = '1' )then
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        Vector_State         <= GET_VECTOR_CMD;
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      end if;
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    end if;
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  end process;
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end architecture;

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