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[/] [open8_urisc/] [trunk/] [gnu/] [binutils/] [opcodes/] [i386-dis.c] - Blame information for rev 158

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1 18 khays
/* Print i386 instructions for GDB, the GNU debugger.
2
   Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3
   2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4
   Free Software Foundation, Inc.
5
 
6
   This file is part of the GNU opcodes library.
7
 
8
   This library is free software; you can redistribute it and/or modify
9
   it under the terms of the GNU General Public License as published by
10
   the Free Software Foundation; either version 3, or (at your option)
11
   any later version.
12
 
13
   It is distributed in the hope that it will be useful, but WITHOUT
14
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
16
   License for more details.
17
 
18
   You should have received a copy of the GNU General Public License
19
   along with this program; if not, write to the Free Software
20
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21
   MA 02110-1301, USA.  */
22
 
23
 
24
/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
25
   July 1988
26
    modified by John Hassey (hassey@dg-rtp.dg.com)
27
    x86-64 support added by Jan Hubicka (jh@suse.cz)
28
    VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
29
 
30
/* The main tables describing the instructions is essentially a copy
31
   of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32
   Programmers Manual.  Usually, there is a capital letter, followed
33
   by a small letter.  The capital letter tell the addressing mode,
34
   and the small letter tells about the operand size.  Refer to
35
   the Intel manual for details.  */
36
 
37
#include "sysdep.h"
38
#include "dis-asm.h"
39
#include "opintl.h"
40
#include "opcode/i386.h"
41
#include "libiberty.h"
42
 
43
#include <setjmp.h>
44
 
45
static int print_insn (bfd_vma, disassemble_info *);
46
static void dofloat (int);
47
static void OP_ST (int, int);
48
static void OP_STi (int, int);
49
static int putop (const char *, int);
50
static void oappend (const char *);
51
static void append_seg (void);
52
static void OP_indirE (int, int);
53
static void print_operand_value (char *, int, bfd_vma);
54
static void OP_E_register (int, int);
55
static void OP_E_memory (int, int);
56
static void print_displacement (char *, bfd_vma);
57
static void OP_E (int, int);
58
static void OP_G (int, int);
59
static bfd_vma get64 (void);
60
static bfd_signed_vma get32 (void);
61
static bfd_signed_vma get32s (void);
62
static int get16 (void);
63
static void set_op (bfd_vma, int);
64
static void OP_Skip_MODRM (int, int);
65
static void OP_REG (int, int);
66
static void OP_IMREG (int, int);
67
static void OP_I (int, int);
68
static void OP_I64 (int, int);
69
static void OP_sI (int, int);
70
static void OP_J (int, int);
71
static void OP_SEG (int, int);
72
static void OP_DIR (int, int);
73
static void OP_OFF (int, int);
74
static void OP_OFF64 (int, int);
75
static void ptr_reg (int, int);
76
static void OP_ESreg (int, int);
77
static void OP_DSreg (int, int);
78
static void OP_C (int, int);
79
static void OP_D (int, int);
80
static void OP_T (int, int);
81
static void OP_R (int, int);
82
static void OP_MMX (int, int);
83
static void OP_XMM (int, int);
84
static void OP_EM (int, int);
85
static void OP_EX (int, int);
86
static void OP_EMC (int,int);
87
static void OP_MXC (int,int);
88
static void OP_MS (int, int);
89
static void OP_XS (int, int);
90
static void OP_M (int, int);
91
static void OP_VEX (int, int);
92
static void OP_EX_Vex (int, int);
93
static void OP_EX_VexW (int, int);
94
static void OP_EX_VexImmW (int, int);
95
static void OP_XMM_Vex (int, int);
96
static void OP_XMM_VexW (int, int);
97
static void OP_REG_VexI4 (int, int);
98
static void PCLMUL_Fixup (int, int);
99
static void VEXI4_Fixup (int, int);
100
static void VZERO_Fixup (int, int);
101
static void VCMP_Fixup (int, int);
102
static void OP_0f07 (int, int);
103
static void OP_Monitor (int, int);
104
static void OP_Mwait (int, int);
105
static void NOP_Fixup1 (int, int);
106
static void NOP_Fixup2 (int, int);
107
static void OP_3DNowSuffix (int, int);
108
static void CMP_Fixup (int, int);
109
static void BadOp (void);
110
static void REP_Fixup (int, int);
111
static void CMPXCHG8B_Fixup (int, int);
112
static void XMM_Fixup (int, int);
113
static void CRC32_Fixup (int, int);
114
static void FXSAVE_Fixup (int, int);
115
static void OP_LWPCB_E (int, int);
116
static void OP_LWP_E (int, int);
117
static void OP_Vex_2src_1 (int, int);
118
static void OP_Vex_2src_2 (int, int);
119
 
120
static void MOVBE_Fixup (int, int);
121
 
122
struct dis_private {
123
  /* Points to first byte not fetched.  */
124
  bfd_byte *max_fetched;
125
  bfd_byte the_buffer[MAX_MNEM_SIZE];
126
  bfd_vma insn_start;
127
  int orig_sizeflag;
128
  jmp_buf bailout;
129
};
130
 
131
enum address_mode
132
{
133
  mode_16bit,
134
  mode_32bit,
135
  mode_64bit
136
};
137
 
138
enum address_mode address_mode;
139
 
140
/* Flags for the prefixes for the current instruction.  See below.  */
141
static int prefixes;
142
 
143
/* REX prefix the current instruction.  See below.  */
144
static int rex;
145
/* Bits of REX we've already used.  */
146
static int rex_used;
147
/* REX bits in original REX prefix ignored.  */
148
static int rex_ignored;
149
/* Mark parts used in the REX prefix.  When we are testing for
150
   empty prefix (for 8bit register REX extension), just mask it
151
   out.  Otherwise test for REX bit is excuse for existence of REX
152
   only in case value is nonzero.  */
153
#define USED_REX(value)                                 \
154
  {                                                     \
155
    if (value)                                          \
156
      {                                                 \
157
        if ((rex & value))                              \
158
          rex_used |= (value) | REX_OPCODE;             \
159
      }                                                 \
160
    else                                                \
161
      rex_used |= REX_OPCODE;                           \
162
  }
163
 
164
/* Flags for prefixes which we somehow handled when printing the
165
   current instruction.  */
166
static int used_prefixes;
167
 
168
/* Flags stored in PREFIXES.  */
169
#define PREFIX_REPZ 1
170
#define PREFIX_REPNZ 2
171
#define PREFIX_LOCK 4
172
#define PREFIX_CS 8
173
#define PREFIX_SS 0x10
174
#define PREFIX_DS 0x20
175
#define PREFIX_ES 0x40
176
#define PREFIX_FS 0x80
177
#define PREFIX_GS 0x100
178
#define PREFIX_DATA 0x200
179
#define PREFIX_ADDR 0x400
180
#define PREFIX_FWAIT 0x800
181
 
182
/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
183
   to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
184
   on error.  */
185
#define FETCH_DATA(info, addr) \
186
  ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
187
   ? 1 : fetch_data ((info), (addr)))
188
 
189
static int
190
fetch_data (struct disassemble_info *info, bfd_byte *addr)
191
{
192
  int status;
193
  struct dis_private *priv = (struct dis_private *) info->private_data;
194
  bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
195
 
196
  if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
197
    status = (*info->read_memory_func) (start,
198
                                        priv->max_fetched,
199
                                        addr - priv->max_fetched,
200
                                        info);
201
  else
202
    status = -1;
203
  if (status != 0)
204
    {
205
      /* If we did manage to read at least one byte, then
206
         print_insn_i386 will do something sensible.  Otherwise, print
207
         an error.  We do that here because this is where we know
208
         STATUS.  */
209
      if (priv->max_fetched == priv->the_buffer)
210
        (*info->memory_error_func) (status, start, info);
211
      longjmp (priv->bailout, 1);
212
    }
213
  else
214
    priv->max_fetched = addr;
215
  return 1;
216
}
217
 
218
#define XX { NULL, 0 }
219
#define Bad_Opcode NULL, { { NULL, 0 } }
220
 
221
#define Eb { OP_E, b_mode }
222
#define EbS { OP_E, b_swap_mode }
223
#define Ev { OP_E, v_mode }
224
#define EvS { OP_E, v_swap_mode }
225
#define Ed { OP_E, d_mode }
226
#define Edq { OP_E, dq_mode }
227
#define Edqw { OP_E, dqw_mode }
228
#define Edqb { OP_E, dqb_mode }
229
#define Edqd { OP_E, dqd_mode }
230
#define Eq { OP_E, q_mode }
231
#define indirEv { OP_indirE, stack_v_mode }
232
#define indirEp { OP_indirE, f_mode }
233
#define stackEv { OP_E, stack_v_mode }
234
#define Em { OP_E, m_mode }
235
#define Ew { OP_E, w_mode }
236
#define M { OP_M, 0 }           /* lea, lgdt, etc. */
237
#define Ma { OP_M, a_mode }
238
#define Mb { OP_M, b_mode }
239
#define Md { OP_M, d_mode }
240
#define Mo { OP_M, o_mode }
241
#define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
242
#define Mq { OP_M, q_mode }
243
#define Mx { OP_M, x_mode }
244
#define Mxmm { OP_M, xmm_mode }
245
#define Gb { OP_G, b_mode }
246
#define Gv { OP_G, v_mode }
247
#define Gd { OP_G, d_mode }
248
#define Gdq { OP_G, dq_mode }
249
#define Gm { OP_G, m_mode }
250
#define Gw { OP_G, w_mode }
251
#define Rd { OP_R, d_mode }
252
#define Rm { OP_R, m_mode }
253
#define Ib { OP_I, b_mode }
254
#define sIb { OP_sI, b_mode }   /* sign extened byte */
255
#define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
256
#define Iv { OP_I, v_mode }
257
#define sIv { OP_sI, v_mode } 
258
#define Iq { OP_I, q_mode }
259
#define Iv64 { OP_I64, v_mode }
260
#define Iw { OP_I, w_mode }
261
#define I1 { OP_I, const_1_mode }
262
#define Jb { OP_J, b_mode }
263
#define Jv { OP_J, v_mode }
264
#define Cm { OP_C, m_mode }
265
#define Dm { OP_D, m_mode }
266
#define Td { OP_T, d_mode }
267
#define Skip_MODRM { OP_Skip_MODRM, 0 }
268
 
269
#define RMeAX { OP_REG, eAX_reg }
270
#define RMeBX { OP_REG, eBX_reg }
271
#define RMeCX { OP_REG, eCX_reg }
272
#define RMeDX { OP_REG, eDX_reg }
273
#define RMeSP { OP_REG, eSP_reg }
274
#define RMeBP { OP_REG, eBP_reg }
275
#define RMeSI { OP_REG, eSI_reg }
276
#define RMeDI { OP_REG, eDI_reg }
277
#define RMrAX { OP_REG, rAX_reg }
278
#define RMrBX { OP_REG, rBX_reg }
279
#define RMrCX { OP_REG, rCX_reg }
280
#define RMrDX { OP_REG, rDX_reg }
281
#define RMrSP { OP_REG, rSP_reg }
282
#define RMrBP { OP_REG, rBP_reg }
283
#define RMrSI { OP_REG, rSI_reg }
284
#define RMrDI { OP_REG, rDI_reg }
285
#define RMAL { OP_REG, al_reg }
286
#define RMCL { OP_REG, cl_reg }
287
#define RMDL { OP_REG, dl_reg }
288
#define RMBL { OP_REG, bl_reg }
289
#define RMAH { OP_REG, ah_reg }
290
#define RMCH { OP_REG, ch_reg }
291
#define RMDH { OP_REG, dh_reg }
292
#define RMBH { OP_REG, bh_reg }
293
#define RMAX { OP_REG, ax_reg }
294
#define RMDX { OP_REG, dx_reg }
295
 
296
#define eAX { OP_IMREG, eAX_reg }
297
#define eBX { OP_IMREG, eBX_reg }
298
#define eCX { OP_IMREG, eCX_reg }
299
#define eDX { OP_IMREG, eDX_reg }
300
#define eSP { OP_IMREG, eSP_reg }
301
#define eBP { OP_IMREG, eBP_reg }
302
#define eSI { OP_IMREG, eSI_reg }
303
#define eDI { OP_IMREG, eDI_reg }
304
#define AL { OP_IMREG, al_reg }
305
#define CL { OP_IMREG, cl_reg }
306
#define DL { OP_IMREG, dl_reg }
307
#define BL { OP_IMREG, bl_reg }
308
#define AH { OP_IMREG, ah_reg }
309
#define CH { OP_IMREG, ch_reg }
310
#define DH { OP_IMREG, dh_reg }
311
#define BH { OP_IMREG, bh_reg }
312
#define AX { OP_IMREG, ax_reg }
313
#define DX { OP_IMREG, dx_reg }
314
#define zAX { OP_IMREG, z_mode_ax_reg }
315
#define indirDX { OP_IMREG, indir_dx_reg }
316
 
317
#define Sw { OP_SEG, w_mode }
318
#define Sv { OP_SEG, v_mode }
319
#define Ap { OP_DIR, 0 }
320
#define Ob { OP_OFF64, b_mode }
321
#define Ov { OP_OFF64, v_mode }
322
#define Xb { OP_DSreg, eSI_reg }
323
#define Xv { OP_DSreg, eSI_reg }
324
#define Xz { OP_DSreg, eSI_reg }
325
#define Yb { OP_ESreg, eDI_reg }
326
#define Yv { OP_ESreg, eDI_reg }
327
#define DSBX { OP_DSreg, eBX_reg }
328
 
329
#define es { OP_REG, es_reg }
330
#define ss { OP_REG, ss_reg }
331
#define cs { OP_REG, cs_reg }
332
#define ds { OP_REG, ds_reg }
333
#define fs { OP_REG, fs_reg }
334
#define gs { OP_REG, gs_reg }
335
 
336
#define MX { OP_MMX, 0 }
337
#define XM { OP_XMM, 0 }
338
#define XMScalar { OP_XMM, scalar_mode }
339 148 khays
#define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
340 18 khays
#define XMM { OP_XMM, xmm_mode }
341
#define EM { OP_EM, v_mode }
342
#define EMS { OP_EM, v_swap_mode }
343
#define EMd { OP_EM, d_mode }
344
#define EMx { OP_EM, x_mode }
345
#define EXw { OP_EX, w_mode }
346
#define EXd { OP_EX, d_mode }
347
#define EXdScalar { OP_EX, d_scalar_mode }
348
#define EXdS { OP_EX, d_swap_mode }
349
#define EXq { OP_EX, q_mode }
350
#define EXqScalar { OP_EX, q_scalar_mode }
351
#define EXqScalarS { OP_EX, q_scalar_swap_mode }
352
#define EXqS { OP_EX, q_swap_mode }
353
#define EXx { OP_EX, x_mode }
354
#define EXxS { OP_EX, x_swap_mode }
355
#define EXxmm { OP_EX, xmm_mode }
356
#define EXxmmq { OP_EX, xmmq_mode }
357 148 khays
#define EXxmm_mb { OP_EX, xmm_mb_mode }
358
#define EXxmm_mw { OP_EX, xmm_mw_mode }
359
#define EXxmm_md { OP_EX, xmm_md_mode }
360
#define EXxmm_mq { OP_EX, xmm_mq_mode }
361
#define EXxmmdw { OP_EX, xmmdw_mode }
362
#define EXxmmqd { OP_EX, xmmqd_mode }
363 18 khays
#define EXymmq { OP_EX, ymmq_mode }
364
#define EXVexWdq { OP_EX, vex_w_dq_mode }
365
#define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
366
#define MS { OP_MS, v_mode }
367
#define XS { OP_XS, v_mode }
368
#define EMCq { OP_EMC, q_mode }
369
#define MXC { OP_MXC, 0 }
370
#define OPSUF { OP_3DNowSuffix, 0 }
371
#define CMP { CMP_Fixup, 0 }
372
#define XMM0 { XMM_Fixup, 0 }
373
#define FXSAVE { FXSAVE_Fixup, 0 }
374
#define Vex_2src_1 { OP_Vex_2src_1, 0 }
375
#define Vex_2src_2 { OP_Vex_2src_2, 0 }
376
 
377
#define Vex { OP_VEX, vex_mode }
378
#define VexScalar { OP_VEX, vex_scalar_mode }
379 148 khays
#define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
380 18 khays
#define Vex128 { OP_VEX, vex128_mode }
381
#define Vex256 { OP_VEX, vex256_mode }
382
#define VexGdq { OP_VEX, dq_mode }
383
#define VexI4 { VEXI4_Fixup, 0}
384
#define EXdVex { OP_EX_Vex, d_mode }
385
#define EXdVexS { OP_EX_Vex, d_swap_mode }
386
#define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
387
#define EXqVex { OP_EX_Vex, q_mode }
388
#define EXqVexS { OP_EX_Vex, q_swap_mode }
389
#define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
390
#define EXVexW { OP_EX_VexW, x_mode }
391
#define EXdVexW { OP_EX_VexW, d_mode }
392
#define EXqVexW { OP_EX_VexW, q_mode }
393
#define EXVexImmW { OP_EX_VexImmW, x_mode }
394
#define XMVex { OP_XMM_Vex, 0 }
395
#define XMVexScalar { OP_XMM_Vex, scalar_mode }
396
#define XMVexW { OP_XMM_VexW, 0 }
397
#define XMVexI4 { OP_REG_VexI4, x_mode }
398
#define PCLMUL { PCLMUL_Fixup, 0 }
399
#define VZERO { VZERO_Fixup, 0 }
400
#define VCMP { VCMP_Fixup, 0 }
401
 
402 148 khays
#define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
403
#define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
404
 
405 18 khays
/* Used handle "rep" prefix for string instructions.  */
406
#define Xbr { REP_Fixup, eSI_reg }
407
#define Xvr { REP_Fixup, eSI_reg }
408
#define Ybr { REP_Fixup, eDI_reg }
409
#define Yvr { REP_Fixup, eDI_reg }
410
#define Yzr { REP_Fixup, eDI_reg }
411
#define indirDXr { REP_Fixup, indir_dx_reg }
412
#define ALr { REP_Fixup, al_reg }
413
#define eAXr { REP_Fixup, eAX_reg }
414
 
415
#define cond_jump_flag { NULL, cond_jump_mode }
416
#define loop_jcxz_flag { NULL, loop_jcxz_mode }
417
 
418
/* bits in sizeflag */
419
#define SUFFIX_ALWAYS 4
420
#define AFLAG 2
421
#define DFLAG 1
422
 
423
enum
424
{
425
  /* byte operand */
426
  b_mode = 1,
427
  /* byte operand with operand swapped */
428
  b_swap_mode,
429
  /* byte operand, sign extend like 'T' suffix */
430
  b_T_mode,
431
  /* operand size depends on prefixes */
432
  v_mode,
433
  /* operand size depends on prefixes with operand swapped */
434
  v_swap_mode,
435
  /* word operand */
436
  w_mode,
437
  /* double word operand  */
438
  d_mode,
439
  /* double word operand with operand swapped */
440
  d_swap_mode,
441
  /* quad word operand */
442
  q_mode,
443
  /* quad word operand with operand swapped */
444
  q_swap_mode,
445
  /* ten-byte operand */
446
  t_mode,
447
  /* 16-byte XMM or 32-byte YMM operand */
448
  x_mode,
449
  /* 16-byte XMM or 32-byte YMM operand with operand swapped */
450
  x_swap_mode,
451
  /* 16-byte XMM operand */
452
  xmm_mode,
453
  /* 16-byte XMM or quad word operand */
454
  xmmq_mode,
455 148 khays
  /* XMM register or byte memory operand */
456
  xmm_mb_mode,
457
  /* XMM register or word memory operand */
458
  xmm_mw_mode,
459
  /* XMM register or double word memory operand */
460
  xmm_md_mode,
461
  /* XMM register or quad word memory operand */
462
  xmm_mq_mode,
463
  /* 16-byte XMM, word or double word operand  */
464
  xmmdw_mode,
465
  /* 16-byte XMM, double word or quad word operand */
466
  xmmqd_mode,
467 18 khays
  /* 32-byte YMM or quad word operand */
468
  ymmq_mode,
469 148 khays
  /* 32-byte YMM or 16-byte word operand */
470
  ymmxmm_mode,
471 18 khays
  /* d_mode in 32bit, q_mode in 64bit mode.  */
472
  m_mode,
473
  /* pair of v_mode operands */
474
  a_mode,
475
  cond_jump_mode,
476
  loop_jcxz_mode,
477
  /* operand size depends on REX prefixes.  */
478
  dq_mode,
479
  /* registers like dq_mode, memory like w_mode.  */
480
  dqw_mode,
481
  /* 4- or 6-byte pointer operand */
482
  f_mode,
483
  const_1_mode,
484
  /* v_mode for stack-related opcodes.  */
485
  stack_v_mode,
486
  /* non-quad operand size depends on prefixes */
487
  z_mode,
488
  /* 16-byte operand */
489
  o_mode,
490
  /* registers like dq_mode, memory like b_mode.  */
491
  dqb_mode,
492
  /* registers like dq_mode, memory like d_mode.  */
493
  dqd_mode,
494
  /* normal vex mode */
495
  vex_mode,
496
  /* 128bit vex mode */
497
  vex128_mode,
498
  /* 256bit vex mode */
499
  vex256_mode,
500
  /* operand size depends on the VEX.W bit.  */
501
  vex_w_dq_mode,
502
 
503 148 khays
  /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
504
  vex_vsib_d_w_dq_mode,
505
  /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
506
  vex_vsib_q_w_dq_mode,
507
 
508 18 khays
  /* scalar, ignore vector length.  */
509
  scalar_mode,
510
  /* like d_mode, ignore vector length.  */
511
  d_scalar_mode,
512
  /* like d_swap_mode, ignore vector length.  */
513
  d_scalar_swap_mode,
514
  /* like q_mode, ignore vector length.  */
515
  q_scalar_mode,
516
  /* like q_swap_mode, ignore vector length.  */
517
  q_scalar_swap_mode,
518
  /* like vex_mode, ignore vector length.  */
519
  vex_scalar_mode,
520
  /* like vex_w_dq_mode, ignore vector length.  */
521
  vex_scalar_w_dq_mode,
522
 
523
  es_reg,
524
  cs_reg,
525
  ss_reg,
526
  ds_reg,
527
  fs_reg,
528
  gs_reg,
529
 
530
  eAX_reg,
531
  eCX_reg,
532
  eDX_reg,
533
  eBX_reg,
534
  eSP_reg,
535
  eBP_reg,
536
  eSI_reg,
537
  eDI_reg,
538
 
539
  al_reg,
540
  cl_reg,
541
  dl_reg,
542
  bl_reg,
543
  ah_reg,
544
  ch_reg,
545
  dh_reg,
546
  bh_reg,
547
 
548
  ax_reg,
549
  cx_reg,
550
  dx_reg,
551
  bx_reg,
552
  sp_reg,
553
  bp_reg,
554
  si_reg,
555
  di_reg,
556
 
557
  rAX_reg,
558
  rCX_reg,
559
  rDX_reg,
560
  rBX_reg,
561
  rSP_reg,
562
  rBP_reg,
563
  rSI_reg,
564
  rDI_reg,
565
 
566
  z_mode_ax_reg,
567
  indir_dx_reg
568
};
569
 
570
enum
571
{
572
  FLOATCODE = 1,
573
  USE_REG_TABLE,
574
  USE_MOD_TABLE,
575
  USE_RM_TABLE,
576
  USE_PREFIX_TABLE,
577
  USE_X86_64_TABLE,
578
  USE_3BYTE_TABLE,
579
  USE_XOP_8F_TABLE,
580
  USE_VEX_C4_TABLE,
581
  USE_VEX_C5_TABLE,
582
  USE_VEX_LEN_TABLE,
583
  USE_VEX_W_TABLE
584
};
585
 
586
#define FLOAT                   NULL, { { NULL, FLOATCODE } }
587
 
588
#define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
589
#define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
590
#define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
591
#define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
592
#define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
593
#define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
594
#define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
595
#define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
596
#define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
597
#define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
598
#define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
599
#define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
600
 
601
enum
602
{
603
  REG_80 = 0,
604
  REG_81,
605
  REG_82,
606
  REG_8F,
607
  REG_C0,
608
  REG_C1,
609
  REG_C6,
610
  REG_C7,
611
  REG_D0,
612
  REG_D1,
613
  REG_D2,
614
  REG_D3,
615
  REG_F6,
616
  REG_F7,
617
  REG_FE,
618
  REG_FF,
619
  REG_0F00,
620
  REG_0F01,
621
  REG_0F0D,
622
  REG_0F18,
623
  REG_0F71,
624
  REG_0F72,
625
  REG_0F73,
626
  REG_0FA6,
627
  REG_0FA7,
628
  REG_0FAE,
629
  REG_0FBA,
630
  REG_0FC7,
631
  REG_VEX_0F71,
632
  REG_VEX_0F72,
633
  REG_VEX_0F73,
634
  REG_VEX_0FAE,
635
  REG_VEX_0F38F3,
636
  REG_XOP_LWPCB,
637
  REG_XOP_LWP,
638
  REG_XOP_TBM_01,
639
  REG_XOP_TBM_02
640
};
641
 
642
enum
643
{
644
  MOD_8D = 0,
645
  MOD_0F01_REG_0,
646
  MOD_0F01_REG_1,
647
  MOD_0F01_REG_2,
648
  MOD_0F01_REG_3,
649
  MOD_0F01_REG_7,
650
  MOD_0F12_PREFIX_0,
651
  MOD_0F13,
652
  MOD_0F16_PREFIX_0,
653
  MOD_0F17,
654
  MOD_0F18_REG_0,
655
  MOD_0F18_REG_1,
656
  MOD_0F18_REG_2,
657
  MOD_0F18_REG_3,
658
  MOD_0F20,
659
  MOD_0F21,
660
  MOD_0F22,
661
  MOD_0F23,
662
  MOD_0F24,
663
  MOD_0F26,
664
  MOD_0F2B_PREFIX_0,
665
  MOD_0F2B_PREFIX_1,
666
  MOD_0F2B_PREFIX_2,
667
  MOD_0F2B_PREFIX_3,
668
  MOD_0F51,
669
  MOD_0F71_REG_2,
670
  MOD_0F71_REG_4,
671
  MOD_0F71_REG_6,
672
  MOD_0F72_REG_2,
673
  MOD_0F72_REG_4,
674
  MOD_0F72_REG_6,
675
  MOD_0F73_REG_2,
676
  MOD_0F73_REG_3,
677
  MOD_0F73_REG_6,
678
  MOD_0F73_REG_7,
679
  MOD_0FAE_REG_0,
680
  MOD_0FAE_REG_1,
681
  MOD_0FAE_REG_2,
682
  MOD_0FAE_REG_3,
683
  MOD_0FAE_REG_4,
684
  MOD_0FAE_REG_5,
685
  MOD_0FAE_REG_6,
686
  MOD_0FAE_REG_7,
687
  MOD_0FB2,
688
  MOD_0FB4,
689
  MOD_0FB5,
690
  MOD_0FC7_REG_6,
691
  MOD_0FC7_REG_7,
692
  MOD_0FD7,
693
  MOD_0FE7_PREFIX_2,
694
  MOD_0FF0_PREFIX_3,
695
  MOD_0F382A_PREFIX_2,
696
  MOD_62_32BIT,
697
  MOD_C4_32BIT,
698
  MOD_C5_32BIT,
699
  MOD_VEX_0F12_PREFIX_0,
700
  MOD_VEX_0F13,
701
  MOD_VEX_0F16_PREFIX_0,
702
  MOD_VEX_0F17,
703
  MOD_VEX_0F2B,
704
  MOD_VEX_0F50,
705
  MOD_VEX_0F71_REG_2,
706
  MOD_VEX_0F71_REG_4,
707
  MOD_VEX_0F71_REG_6,
708
  MOD_VEX_0F72_REG_2,
709
  MOD_VEX_0F72_REG_4,
710
  MOD_VEX_0F72_REG_6,
711
  MOD_VEX_0F73_REG_2,
712
  MOD_VEX_0F73_REG_3,
713
  MOD_VEX_0F73_REG_6,
714
  MOD_VEX_0F73_REG_7,
715
  MOD_VEX_0FAE_REG_2,
716
  MOD_VEX_0FAE_REG_3,
717
  MOD_VEX_0FD7_PREFIX_2,
718
  MOD_VEX_0FE7_PREFIX_2,
719
  MOD_VEX_0FF0_PREFIX_3,
720
  MOD_VEX_0F381A_PREFIX_2,
721
  MOD_VEX_0F382A_PREFIX_2,
722
  MOD_VEX_0F382C_PREFIX_2,
723
  MOD_VEX_0F382D_PREFIX_2,
724
  MOD_VEX_0F382E_PREFIX_2,
725 148 khays
  MOD_VEX_0F382F_PREFIX_2,
726
  MOD_VEX_0F385A_PREFIX_2,
727
  MOD_VEX_0F388C_PREFIX_2,
728
  MOD_VEX_0F388E_PREFIX_2,
729 18 khays
};
730
 
731
enum
732
{
733
  RM_0F01_REG_0 = 0,
734
  RM_0F01_REG_1,
735
  RM_0F01_REG_2,
736
  RM_0F01_REG_3,
737
  RM_0F01_REG_7,
738
  RM_0FAE_REG_5,
739
  RM_0FAE_REG_6,
740
  RM_0FAE_REG_7
741
};
742
 
743
enum
744
{
745
  PREFIX_90 = 0,
746
  PREFIX_0F10,
747
  PREFIX_0F11,
748
  PREFIX_0F12,
749
  PREFIX_0F16,
750
  PREFIX_0F2A,
751
  PREFIX_0F2B,
752
  PREFIX_0F2C,
753
  PREFIX_0F2D,
754
  PREFIX_0F2E,
755
  PREFIX_0F2F,
756
  PREFIX_0F51,
757
  PREFIX_0F52,
758
  PREFIX_0F53,
759
  PREFIX_0F58,
760
  PREFIX_0F59,
761
  PREFIX_0F5A,
762
  PREFIX_0F5B,
763
  PREFIX_0F5C,
764
  PREFIX_0F5D,
765
  PREFIX_0F5E,
766
  PREFIX_0F5F,
767
  PREFIX_0F60,
768
  PREFIX_0F61,
769
  PREFIX_0F62,
770
  PREFIX_0F6C,
771
  PREFIX_0F6D,
772
  PREFIX_0F6F,
773
  PREFIX_0F70,
774
  PREFIX_0F73_REG_3,
775
  PREFIX_0F73_REG_7,
776
  PREFIX_0F78,
777
  PREFIX_0F79,
778
  PREFIX_0F7C,
779
  PREFIX_0F7D,
780
  PREFIX_0F7E,
781
  PREFIX_0F7F,
782
  PREFIX_0FAE_REG_0,
783
  PREFIX_0FAE_REG_1,
784
  PREFIX_0FAE_REG_2,
785
  PREFIX_0FAE_REG_3,
786
  PREFIX_0FB8,
787
  PREFIX_0FBC,
788
  PREFIX_0FBD,
789
  PREFIX_0FC2,
790
  PREFIX_0FC3,
791
  PREFIX_0FC7_REG_6,
792
  PREFIX_0FD0,
793
  PREFIX_0FD6,
794
  PREFIX_0FE6,
795
  PREFIX_0FE7,
796
  PREFIX_0FF0,
797
  PREFIX_0FF7,
798
  PREFIX_0F3810,
799
  PREFIX_0F3814,
800
  PREFIX_0F3815,
801
  PREFIX_0F3817,
802
  PREFIX_0F3820,
803
  PREFIX_0F3821,
804
  PREFIX_0F3822,
805
  PREFIX_0F3823,
806
  PREFIX_0F3824,
807
  PREFIX_0F3825,
808
  PREFIX_0F3828,
809
  PREFIX_0F3829,
810
  PREFIX_0F382A,
811
  PREFIX_0F382B,
812
  PREFIX_0F3830,
813
  PREFIX_0F3831,
814
  PREFIX_0F3832,
815
  PREFIX_0F3833,
816
  PREFIX_0F3834,
817
  PREFIX_0F3835,
818
  PREFIX_0F3837,
819
  PREFIX_0F3838,
820
  PREFIX_0F3839,
821
  PREFIX_0F383A,
822
  PREFIX_0F383B,
823
  PREFIX_0F383C,
824
  PREFIX_0F383D,
825
  PREFIX_0F383E,
826
  PREFIX_0F383F,
827
  PREFIX_0F3840,
828
  PREFIX_0F3841,
829
  PREFIX_0F3880,
830
  PREFIX_0F3881,
831 148 khays
  PREFIX_0F3882,
832 18 khays
  PREFIX_0F38DB,
833
  PREFIX_0F38DC,
834
  PREFIX_0F38DD,
835
  PREFIX_0F38DE,
836
  PREFIX_0F38DF,
837
  PREFIX_0F38F0,
838
  PREFIX_0F38F1,
839
  PREFIX_0F3A08,
840
  PREFIX_0F3A09,
841
  PREFIX_0F3A0A,
842
  PREFIX_0F3A0B,
843
  PREFIX_0F3A0C,
844
  PREFIX_0F3A0D,
845
  PREFIX_0F3A0E,
846
  PREFIX_0F3A14,
847
  PREFIX_0F3A15,
848
  PREFIX_0F3A16,
849
  PREFIX_0F3A17,
850
  PREFIX_0F3A20,
851
  PREFIX_0F3A21,
852
  PREFIX_0F3A22,
853
  PREFIX_0F3A40,
854
  PREFIX_0F3A41,
855
  PREFIX_0F3A42,
856
  PREFIX_0F3A44,
857
  PREFIX_0F3A60,
858
  PREFIX_0F3A61,
859
  PREFIX_0F3A62,
860
  PREFIX_0F3A63,
861
  PREFIX_0F3ADF,
862
  PREFIX_VEX_0F10,
863
  PREFIX_VEX_0F11,
864
  PREFIX_VEX_0F12,
865
  PREFIX_VEX_0F16,
866
  PREFIX_VEX_0F2A,
867
  PREFIX_VEX_0F2C,
868
  PREFIX_VEX_0F2D,
869
  PREFIX_VEX_0F2E,
870
  PREFIX_VEX_0F2F,
871
  PREFIX_VEX_0F51,
872
  PREFIX_VEX_0F52,
873
  PREFIX_VEX_0F53,
874
  PREFIX_VEX_0F58,
875
  PREFIX_VEX_0F59,
876
  PREFIX_VEX_0F5A,
877
  PREFIX_VEX_0F5B,
878
  PREFIX_VEX_0F5C,
879
  PREFIX_VEX_0F5D,
880
  PREFIX_VEX_0F5E,
881
  PREFIX_VEX_0F5F,
882
  PREFIX_VEX_0F60,
883
  PREFIX_VEX_0F61,
884
  PREFIX_VEX_0F62,
885
  PREFIX_VEX_0F63,
886
  PREFIX_VEX_0F64,
887
  PREFIX_VEX_0F65,
888
  PREFIX_VEX_0F66,
889
  PREFIX_VEX_0F67,
890
  PREFIX_VEX_0F68,
891
  PREFIX_VEX_0F69,
892
  PREFIX_VEX_0F6A,
893
  PREFIX_VEX_0F6B,
894
  PREFIX_VEX_0F6C,
895
  PREFIX_VEX_0F6D,
896
  PREFIX_VEX_0F6E,
897
  PREFIX_VEX_0F6F,
898
  PREFIX_VEX_0F70,
899
  PREFIX_VEX_0F71_REG_2,
900
  PREFIX_VEX_0F71_REG_4,
901
  PREFIX_VEX_0F71_REG_6,
902
  PREFIX_VEX_0F72_REG_2,
903
  PREFIX_VEX_0F72_REG_4,
904
  PREFIX_VEX_0F72_REG_6,
905
  PREFIX_VEX_0F73_REG_2,
906
  PREFIX_VEX_0F73_REG_3,
907
  PREFIX_VEX_0F73_REG_6,
908
  PREFIX_VEX_0F73_REG_7,
909
  PREFIX_VEX_0F74,
910
  PREFIX_VEX_0F75,
911
  PREFIX_VEX_0F76,
912
  PREFIX_VEX_0F77,
913
  PREFIX_VEX_0F7C,
914
  PREFIX_VEX_0F7D,
915
  PREFIX_VEX_0F7E,
916
  PREFIX_VEX_0F7F,
917
  PREFIX_VEX_0FC2,
918
  PREFIX_VEX_0FC4,
919
  PREFIX_VEX_0FC5,
920
  PREFIX_VEX_0FD0,
921
  PREFIX_VEX_0FD1,
922
  PREFIX_VEX_0FD2,
923
  PREFIX_VEX_0FD3,
924
  PREFIX_VEX_0FD4,
925
  PREFIX_VEX_0FD5,
926
  PREFIX_VEX_0FD6,
927
  PREFIX_VEX_0FD7,
928
  PREFIX_VEX_0FD8,
929
  PREFIX_VEX_0FD9,
930
  PREFIX_VEX_0FDA,
931
  PREFIX_VEX_0FDB,
932
  PREFIX_VEX_0FDC,
933
  PREFIX_VEX_0FDD,
934
  PREFIX_VEX_0FDE,
935
  PREFIX_VEX_0FDF,
936
  PREFIX_VEX_0FE0,
937
  PREFIX_VEX_0FE1,
938
  PREFIX_VEX_0FE2,
939
  PREFIX_VEX_0FE3,
940
  PREFIX_VEX_0FE4,
941
  PREFIX_VEX_0FE5,
942
  PREFIX_VEX_0FE6,
943
  PREFIX_VEX_0FE7,
944
  PREFIX_VEX_0FE8,
945
  PREFIX_VEX_0FE9,
946
  PREFIX_VEX_0FEA,
947
  PREFIX_VEX_0FEB,
948
  PREFIX_VEX_0FEC,
949
  PREFIX_VEX_0FED,
950
  PREFIX_VEX_0FEE,
951
  PREFIX_VEX_0FEF,
952
  PREFIX_VEX_0FF0,
953
  PREFIX_VEX_0FF1,
954
  PREFIX_VEX_0FF2,
955
  PREFIX_VEX_0FF3,
956
  PREFIX_VEX_0FF4,
957
  PREFIX_VEX_0FF5,
958
  PREFIX_VEX_0FF6,
959
  PREFIX_VEX_0FF7,
960
  PREFIX_VEX_0FF8,
961
  PREFIX_VEX_0FF9,
962
  PREFIX_VEX_0FFA,
963
  PREFIX_VEX_0FFB,
964
  PREFIX_VEX_0FFC,
965
  PREFIX_VEX_0FFD,
966
  PREFIX_VEX_0FFE,
967
  PREFIX_VEX_0F3800,
968
  PREFIX_VEX_0F3801,
969
  PREFIX_VEX_0F3802,
970
  PREFIX_VEX_0F3803,
971
  PREFIX_VEX_0F3804,
972
  PREFIX_VEX_0F3805,
973
  PREFIX_VEX_0F3806,
974
  PREFIX_VEX_0F3807,
975
  PREFIX_VEX_0F3808,
976
  PREFIX_VEX_0F3809,
977
  PREFIX_VEX_0F380A,
978
  PREFIX_VEX_0F380B,
979
  PREFIX_VEX_0F380C,
980
  PREFIX_VEX_0F380D,
981
  PREFIX_VEX_0F380E,
982
  PREFIX_VEX_0F380F,
983
  PREFIX_VEX_0F3813,
984 148 khays
  PREFIX_VEX_0F3816,
985 18 khays
  PREFIX_VEX_0F3817,
986
  PREFIX_VEX_0F3818,
987
  PREFIX_VEX_0F3819,
988
  PREFIX_VEX_0F381A,
989
  PREFIX_VEX_0F381C,
990
  PREFIX_VEX_0F381D,
991
  PREFIX_VEX_0F381E,
992
  PREFIX_VEX_0F3820,
993
  PREFIX_VEX_0F3821,
994
  PREFIX_VEX_0F3822,
995
  PREFIX_VEX_0F3823,
996
  PREFIX_VEX_0F3824,
997
  PREFIX_VEX_0F3825,
998
  PREFIX_VEX_0F3828,
999
  PREFIX_VEX_0F3829,
1000
  PREFIX_VEX_0F382A,
1001
  PREFIX_VEX_0F382B,
1002
  PREFIX_VEX_0F382C,
1003
  PREFIX_VEX_0F382D,
1004
  PREFIX_VEX_0F382E,
1005
  PREFIX_VEX_0F382F,
1006
  PREFIX_VEX_0F3830,
1007
  PREFIX_VEX_0F3831,
1008
  PREFIX_VEX_0F3832,
1009
  PREFIX_VEX_0F3833,
1010
  PREFIX_VEX_0F3834,
1011
  PREFIX_VEX_0F3835,
1012 148 khays
  PREFIX_VEX_0F3836,
1013 18 khays
  PREFIX_VEX_0F3837,
1014
  PREFIX_VEX_0F3838,
1015
  PREFIX_VEX_0F3839,
1016
  PREFIX_VEX_0F383A,
1017
  PREFIX_VEX_0F383B,
1018
  PREFIX_VEX_0F383C,
1019
  PREFIX_VEX_0F383D,
1020
  PREFIX_VEX_0F383E,
1021
  PREFIX_VEX_0F383F,
1022
  PREFIX_VEX_0F3840,
1023
  PREFIX_VEX_0F3841,
1024 148 khays
  PREFIX_VEX_0F3845,
1025
  PREFIX_VEX_0F3846,
1026
  PREFIX_VEX_0F3847,
1027
  PREFIX_VEX_0F3858,
1028
  PREFIX_VEX_0F3859,
1029
  PREFIX_VEX_0F385A,
1030
  PREFIX_VEX_0F3878,
1031
  PREFIX_VEX_0F3879,
1032
  PREFIX_VEX_0F388C,
1033
  PREFIX_VEX_0F388E,
1034
  PREFIX_VEX_0F3890,
1035
  PREFIX_VEX_0F3891,
1036
  PREFIX_VEX_0F3892,
1037
  PREFIX_VEX_0F3893,
1038 18 khays
  PREFIX_VEX_0F3896,
1039
  PREFIX_VEX_0F3897,
1040
  PREFIX_VEX_0F3898,
1041
  PREFIX_VEX_0F3899,
1042
  PREFIX_VEX_0F389A,
1043
  PREFIX_VEX_0F389B,
1044
  PREFIX_VEX_0F389C,
1045
  PREFIX_VEX_0F389D,
1046
  PREFIX_VEX_0F389E,
1047
  PREFIX_VEX_0F389F,
1048
  PREFIX_VEX_0F38A6,
1049
  PREFIX_VEX_0F38A7,
1050
  PREFIX_VEX_0F38A8,
1051
  PREFIX_VEX_0F38A9,
1052
  PREFIX_VEX_0F38AA,
1053
  PREFIX_VEX_0F38AB,
1054
  PREFIX_VEX_0F38AC,
1055
  PREFIX_VEX_0F38AD,
1056
  PREFIX_VEX_0F38AE,
1057
  PREFIX_VEX_0F38AF,
1058
  PREFIX_VEX_0F38B6,
1059
  PREFIX_VEX_0F38B7,
1060
  PREFIX_VEX_0F38B8,
1061
  PREFIX_VEX_0F38B9,
1062
  PREFIX_VEX_0F38BA,
1063
  PREFIX_VEX_0F38BB,
1064
  PREFIX_VEX_0F38BC,
1065
  PREFIX_VEX_0F38BD,
1066
  PREFIX_VEX_0F38BE,
1067
  PREFIX_VEX_0F38BF,
1068
  PREFIX_VEX_0F38DB,
1069
  PREFIX_VEX_0F38DC,
1070
  PREFIX_VEX_0F38DD,
1071
  PREFIX_VEX_0F38DE,
1072
  PREFIX_VEX_0F38DF,
1073
  PREFIX_VEX_0F38F2,
1074
  PREFIX_VEX_0F38F3_REG_1,
1075
  PREFIX_VEX_0F38F3_REG_2,
1076
  PREFIX_VEX_0F38F3_REG_3,
1077 148 khays
  PREFIX_VEX_0F38F5,
1078
  PREFIX_VEX_0F38F6,
1079 18 khays
  PREFIX_VEX_0F38F7,
1080 148 khays
  PREFIX_VEX_0F3A00,
1081
  PREFIX_VEX_0F3A01,
1082
  PREFIX_VEX_0F3A02,
1083 18 khays
  PREFIX_VEX_0F3A04,
1084
  PREFIX_VEX_0F3A05,
1085
  PREFIX_VEX_0F3A06,
1086
  PREFIX_VEX_0F3A08,
1087
  PREFIX_VEX_0F3A09,
1088
  PREFIX_VEX_0F3A0A,
1089
  PREFIX_VEX_0F3A0B,
1090
  PREFIX_VEX_0F3A0C,
1091
  PREFIX_VEX_0F3A0D,
1092
  PREFIX_VEX_0F3A0E,
1093
  PREFIX_VEX_0F3A0F,
1094
  PREFIX_VEX_0F3A14,
1095
  PREFIX_VEX_0F3A15,
1096
  PREFIX_VEX_0F3A16,
1097
  PREFIX_VEX_0F3A17,
1098
  PREFIX_VEX_0F3A18,
1099
  PREFIX_VEX_0F3A19,
1100
  PREFIX_VEX_0F3A1D,
1101
  PREFIX_VEX_0F3A20,
1102
  PREFIX_VEX_0F3A21,
1103
  PREFIX_VEX_0F3A22,
1104 148 khays
  PREFIX_VEX_0F3A38,
1105
  PREFIX_VEX_0F3A39,
1106 18 khays
  PREFIX_VEX_0F3A40,
1107
  PREFIX_VEX_0F3A41,
1108
  PREFIX_VEX_0F3A42,
1109
  PREFIX_VEX_0F3A44,
1110 148 khays
  PREFIX_VEX_0F3A46,
1111 18 khays
  PREFIX_VEX_0F3A48,
1112
  PREFIX_VEX_0F3A49,
1113
  PREFIX_VEX_0F3A4A,
1114
  PREFIX_VEX_0F3A4B,
1115
  PREFIX_VEX_0F3A4C,
1116
  PREFIX_VEX_0F3A5C,
1117
  PREFIX_VEX_0F3A5D,
1118
  PREFIX_VEX_0F3A5E,
1119
  PREFIX_VEX_0F3A5F,
1120
  PREFIX_VEX_0F3A60,
1121
  PREFIX_VEX_0F3A61,
1122
  PREFIX_VEX_0F3A62,
1123
  PREFIX_VEX_0F3A63,
1124
  PREFIX_VEX_0F3A68,
1125
  PREFIX_VEX_0F3A69,
1126
  PREFIX_VEX_0F3A6A,
1127
  PREFIX_VEX_0F3A6B,
1128
  PREFIX_VEX_0F3A6C,
1129
  PREFIX_VEX_0F3A6D,
1130
  PREFIX_VEX_0F3A6E,
1131
  PREFIX_VEX_0F3A6F,
1132
  PREFIX_VEX_0F3A78,
1133
  PREFIX_VEX_0F3A79,
1134
  PREFIX_VEX_0F3A7A,
1135
  PREFIX_VEX_0F3A7B,
1136
  PREFIX_VEX_0F3A7C,
1137
  PREFIX_VEX_0F3A7D,
1138
  PREFIX_VEX_0F3A7E,
1139
  PREFIX_VEX_0F3A7F,
1140 148 khays
  PREFIX_VEX_0F3ADF,
1141
  PREFIX_VEX_0F3AF0
1142 18 khays
};
1143
 
1144
enum
1145
{
1146
  X86_64_06 = 0,
1147
  X86_64_07,
1148
  X86_64_0D,
1149
  X86_64_16,
1150
  X86_64_17,
1151
  X86_64_1E,
1152
  X86_64_1F,
1153
  X86_64_27,
1154
  X86_64_2F,
1155
  X86_64_37,
1156
  X86_64_3F,
1157
  X86_64_60,
1158
  X86_64_61,
1159
  X86_64_62,
1160
  X86_64_63,
1161
  X86_64_6D,
1162
  X86_64_6F,
1163
  X86_64_9A,
1164
  X86_64_C4,
1165
  X86_64_C5,
1166
  X86_64_CE,
1167
  X86_64_D4,
1168
  X86_64_D5,
1169
  X86_64_EA,
1170
  X86_64_0F01_REG_0,
1171
  X86_64_0F01_REG_1,
1172
  X86_64_0F01_REG_2,
1173
  X86_64_0F01_REG_3
1174
};
1175
 
1176
enum
1177
{
1178
  THREE_BYTE_0F38 = 0,
1179
  THREE_BYTE_0F3A,
1180
  THREE_BYTE_0F7A
1181
};
1182
 
1183
enum
1184
{
1185
  XOP_08 = 0,
1186
  XOP_09,
1187
  XOP_0A
1188
};
1189
 
1190
enum
1191
{
1192
  VEX_0F = 0,
1193
  VEX_0F38,
1194
  VEX_0F3A
1195
};
1196
 
1197
enum
1198
{
1199
  VEX_LEN_0F10_P_1 = 0,
1200
  VEX_LEN_0F10_P_3,
1201
  VEX_LEN_0F11_P_1,
1202
  VEX_LEN_0F11_P_3,
1203
  VEX_LEN_0F12_P_0_M_0,
1204
  VEX_LEN_0F12_P_0_M_1,
1205
  VEX_LEN_0F12_P_2,
1206
  VEX_LEN_0F13_M_0,
1207
  VEX_LEN_0F16_P_0_M_0,
1208
  VEX_LEN_0F16_P_0_M_1,
1209
  VEX_LEN_0F16_P_2,
1210
  VEX_LEN_0F17_M_0,
1211
  VEX_LEN_0F2A_P_1,
1212
  VEX_LEN_0F2A_P_3,
1213
  VEX_LEN_0F2C_P_1,
1214
  VEX_LEN_0F2C_P_3,
1215
  VEX_LEN_0F2D_P_1,
1216
  VEX_LEN_0F2D_P_3,
1217
  VEX_LEN_0F2E_P_0,
1218
  VEX_LEN_0F2E_P_2,
1219
  VEX_LEN_0F2F_P_0,
1220
  VEX_LEN_0F2F_P_2,
1221
  VEX_LEN_0F51_P_1,
1222
  VEX_LEN_0F51_P_3,
1223
  VEX_LEN_0F52_P_1,
1224
  VEX_LEN_0F53_P_1,
1225
  VEX_LEN_0F58_P_1,
1226
  VEX_LEN_0F58_P_3,
1227
  VEX_LEN_0F59_P_1,
1228
  VEX_LEN_0F59_P_3,
1229
  VEX_LEN_0F5A_P_1,
1230
  VEX_LEN_0F5A_P_3,
1231
  VEX_LEN_0F5C_P_1,
1232
  VEX_LEN_0F5C_P_3,
1233
  VEX_LEN_0F5D_P_1,
1234
  VEX_LEN_0F5D_P_3,
1235
  VEX_LEN_0F5E_P_1,
1236
  VEX_LEN_0F5E_P_3,
1237
  VEX_LEN_0F5F_P_1,
1238
  VEX_LEN_0F5F_P_3,
1239
  VEX_LEN_0F6E_P_2,
1240
  VEX_LEN_0F7E_P_1,
1241
  VEX_LEN_0F7E_P_2,
1242
  VEX_LEN_0FAE_R_2_M_0,
1243
  VEX_LEN_0FAE_R_3_M_0,
1244
  VEX_LEN_0FC2_P_1,
1245
  VEX_LEN_0FC2_P_3,
1246
  VEX_LEN_0FC4_P_2,
1247
  VEX_LEN_0FC5_P_2,
1248
  VEX_LEN_0FD6_P_2,
1249
  VEX_LEN_0FF7_P_2,
1250 148 khays
  VEX_LEN_0F3816_P_2,
1251
  VEX_LEN_0F3819_P_2,
1252 18 khays
  VEX_LEN_0F381A_P_2_M_0,
1253 148 khays
  VEX_LEN_0F3836_P_2,
1254 18 khays
  VEX_LEN_0F3841_P_2,
1255 148 khays
  VEX_LEN_0F385A_P_2_M_0,
1256 18 khays
  VEX_LEN_0F38DB_P_2,
1257
  VEX_LEN_0F38DC_P_2,
1258
  VEX_LEN_0F38DD_P_2,
1259
  VEX_LEN_0F38DE_P_2,
1260
  VEX_LEN_0F38DF_P_2,
1261
  VEX_LEN_0F38F2_P_0,
1262
  VEX_LEN_0F38F3_R_1_P_0,
1263
  VEX_LEN_0F38F3_R_2_P_0,
1264
  VEX_LEN_0F38F3_R_3_P_0,
1265 148 khays
  VEX_LEN_0F38F5_P_0,
1266
  VEX_LEN_0F38F5_P_1,
1267
  VEX_LEN_0F38F5_P_3,
1268
  VEX_LEN_0F38F6_P_3,
1269 18 khays
  VEX_LEN_0F38F7_P_0,
1270 148 khays
  VEX_LEN_0F38F7_P_1,
1271
  VEX_LEN_0F38F7_P_2,
1272
  VEX_LEN_0F38F7_P_3,
1273
  VEX_LEN_0F3A00_P_2,
1274
  VEX_LEN_0F3A01_P_2,
1275 18 khays
  VEX_LEN_0F3A06_P_2,
1276
  VEX_LEN_0F3A0A_P_2,
1277
  VEX_LEN_0F3A0B_P_2,
1278
  VEX_LEN_0F3A14_P_2,
1279
  VEX_LEN_0F3A15_P_2,
1280
  VEX_LEN_0F3A16_P_2,
1281
  VEX_LEN_0F3A17_P_2,
1282
  VEX_LEN_0F3A18_P_2,
1283
  VEX_LEN_0F3A19_P_2,
1284
  VEX_LEN_0F3A20_P_2,
1285
  VEX_LEN_0F3A21_P_2,
1286
  VEX_LEN_0F3A22_P_2,
1287 148 khays
  VEX_LEN_0F3A38_P_2,
1288
  VEX_LEN_0F3A39_P_2,
1289 18 khays
  VEX_LEN_0F3A41_P_2,
1290
  VEX_LEN_0F3A44_P_2,
1291 148 khays
  VEX_LEN_0F3A46_P_2,
1292 18 khays
  VEX_LEN_0F3A60_P_2,
1293
  VEX_LEN_0F3A61_P_2,
1294
  VEX_LEN_0F3A62_P_2,
1295
  VEX_LEN_0F3A63_P_2,
1296
  VEX_LEN_0F3A6A_P_2,
1297
  VEX_LEN_0F3A6B_P_2,
1298
  VEX_LEN_0F3A6E_P_2,
1299
  VEX_LEN_0F3A6F_P_2,
1300
  VEX_LEN_0F3A7A_P_2,
1301
  VEX_LEN_0F3A7B_P_2,
1302
  VEX_LEN_0F3A7E_P_2,
1303
  VEX_LEN_0F3A7F_P_2,
1304
  VEX_LEN_0F3ADF_P_2,
1305 148 khays
  VEX_LEN_0F3AF0_P_3,
1306 18 khays
  VEX_LEN_0FXOP_09_80,
1307
  VEX_LEN_0FXOP_09_81
1308
};
1309
 
1310
enum
1311
{
1312
  VEX_W_0F10_P_0 = 0,
1313
  VEX_W_0F10_P_1,
1314
  VEX_W_0F10_P_2,
1315
  VEX_W_0F10_P_3,
1316
  VEX_W_0F11_P_0,
1317
  VEX_W_0F11_P_1,
1318
  VEX_W_0F11_P_2,
1319
  VEX_W_0F11_P_3,
1320
  VEX_W_0F12_P_0_M_0,
1321
  VEX_W_0F12_P_0_M_1,
1322
  VEX_W_0F12_P_1,
1323
  VEX_W_0F12_P_2,
1324
  VEX_W_0F12_P_3,
1325
  VEX_W_0F13_M_0,
1326
  VEX_W_0F14,
1327
  VEX_W_0F15,
1328
  VEX_W_0F16_P_0_M_0,
1329
  VEX_W_0F16_P_0_M_1,
1330
  VEX_W_0F16_P_1,
1331
  VEX_W_0F16_P_2,
1332
  VEX_W_0F17_M_0,
1333
  VEX_W_0F28,
1334
  VEX_W_0F29,
1335
  VEX_W_0F2B_M_0,
1336
  VEX_W_0F2E_P_0,
1337
  VEX_W_0F2E_P_2,
1338
  VEX_W_0F2F_P_0,
1339
  VEX_W_0F2F_P_2,
1340
  VEX_W_0F50_M_0,
1341
  VEX_W_0F51_P_0,
1342
  VEX_W_0F51_P_1,
1343
  VEX_W_0F51_P_2,
1344
  VEX_W_0F51_P_3,
1345
  VEX_W_0F52_P_0,
1346
  VEX_W_0F52_P_1,
1347
  VEX_W_0F53_P_0,
1348
  VEX_W_0F53_P_1,
1349
  VEX_W_0F58_P_0,
1350
  VEX_W_0F58_P_1,
1351
  VEX_W_0F58_P_2,
1352
  VEX_W_0F58_P_3,
1353
  VEX_W_0F59_P_0,
1354
  VEX_W_0F59_P_1,
1355
  VEX_W_0F59_P_2,
1356
  VEX_W_0F59_P_3,
1357
  VEX_W_0F5A_P_0,
1358
  VEX_W_0F5A_P_1,
1359
  VEX_W_0F5A_P_3,
1360
  VEX_W_0F5B_P_0,
1361
  VEX_W_0F5B_P_1,
1362
  VEX_W_0F5B_P_2,
1363
  VEX_W_0F5C_P_0,
1364
  VEX_W_0F5C_P_1,
1365
  VEX_W_0F5C_P_2,
1366
  VEX_W_0F5C_P_3,
1367
  VEX_W_0F5D_P_0,
1368
  VEX_W_0F5D_P_1,
1369
  VEX_W_0F5D_P_2,
1370
  VEX_W_0F5D_P_3,
1371
  VEX_W_0F5E_P_0,
1372
  VEX_W_0F5E_P_1,
1373
  VEX_W_0F5E_P_2,
1374
  VEX_W_0F5E_P_3,
1375
  VEX_W_0F5F_P_0,
1376
  VEX_W_0F5F_P_1,
1377
  VEX_W_0F5F_P_2,
1378
  VEX_W_0F5F_P_3,
1379
  VEX_W_0F60_P_2,
1380
  VEX_W_0F61_P_2,
1381
  VEX_W_0F62_P_2,
1382
  VEX_W_0F63_P_2,
1383
  VEX_W_0F64_P_2,
1384
  VEX_W_0F65_P_2,
1385
  VEX_W_0F66_P_2,
1386
  VEX_W_0F67_P_2,
1387
  VEX_W_0F68_P_2,
1388
  VEX_W_0F69_P_2,
1389
  VEX_W_0F6A_P_2,
1390
  VEX_W_0F6B_P_2,
1391
  VEX_W_0F6C_P_2,
1392
  VEX_W_0F6D_P_2,
1393
  VEX_W_0F6F_P_1,
1394
  VEX_W_0F6F_P_2,
1395
  VEX_W_0F70_P_1,
1396
  VEX_W_0F70_P_2,
1397
  VEX_W_0F70_P_3,
1398
  VEX_W_0F71_R_2_P_2,
1399
  VEX_W_0F71_R_4_P_2,
1400
  VEX_W_0F71_R_6_P_2,
1401
  VEX_W_0F72_R_2_P_2,
1402
  VEX_W_0F72_R_4_P_2,
1403
  VEX_W_0F72_R_6_P_2,
1404
  VEX_W_0F73_R_2_P_2,
1405
  VEX_W_0F73_R_3_P_2,
1406
  VEX_W_0F73_R_6_P_2,
1407
  VEX_W_0F73_R_7_P_2,
1408
  VEX_W_0F74_P_2,
1409
  VEX_W_0F75_P_2,
1410
  VEX_W_0F76_P_2,
1411
  VEX_W_0F77_P_0,
1412
  VEX_W_0F7C_P_2,
1413
  VEX_W_0F7C_P_3,
1414
  VEX_W_0F7D_P_2,
1415
  VEX_W_0F7D_P_3,
1416
  VEX_W_0F7E_P_1,
1417
  VEX_W_0F7F_P_1,
1418
  VEX_W_0F7F_P_2,
1419
  VEX_W_0FAE_R_2_M_0,
1420
  VEX_W_0FAE_R_3_M_0,
1421
  VEX_W_0FC2_P_0,
1422
  VEX_W_0FC2_P_1,
1423
  VEX_W_0FC2_P_2,
1424
  VEX_W_0FC2_P_3,
1425
  VEX_W_0FC4_P_2,
1426
  VEX_W_0FC5_P_2,
1427
  VEX_W_0FD0_P_2,
1428
  VEX_W_0FD0_P_3,
1429
  VEX_W_0FD1_P_2,
1430
  VEX_W_0FD2_P_2,
1431
  VEX_W_0FD3_P_2,
1432
  VEX_W_0FD4_P_2,
1433
  VEX_W_0FD5_P_2,
1434
  VEX_W_0FD6_P_2,
1435
  VEX_W_0FD7_P_2_M_1,
1436
  VEX_W_0FD8_P_2,
1437
  VEX_W_0FD9_P_2,
1438
  VEX_W_0FDA_P_2,
1439
  VEX_W_0FDB_P_2,
1440
  VEX_W_0FDC_P_2,
1441
  VEX_W_0FDD_P_2,
1442
  VEX_W_0FDE_P_2,
1443
  VEX_W_0FDF_P_2,
1444
  VEX_W_0FE0_P_2,
1445
  VEX_W_0FE1_P_2,
1446
  VEX_W_0FE2_P_2,
1447
  VEX_W_0FE3_P_2,
1448
  VEX_W_0FE4_P_2,
1449
  VEX_W_0FE5_P_2,
1450
  VEX_W_0FE6_P_1,
1451
  VEX_W_0FE6_P_2,
1452
  VEX_W_0FE6_P_3,
1453
  VEX_W_0FE7_P_2_M_0,
1454
  VEX_W_0FE8_P_2,
1455
  VEX_W_0FE9_P_2,
1456
  VEX_W_0FEA_P_2,
1457
  VEX_W_0FEB_P_2,
1458
  VEX_W_0FEC_P_2,
1459
  VEX_W_0FED_P_2,
1460
  VEX_W_0FEE_P_2,
1461
  VEX_W_0FEF_P_2,
1462
  VEX_W_0FF0_P_3_M_0,
1463
  VEX_W_0FF1_P_2,
1464
  VEX_W_0FF2_P_2,
1465
  VEX_W_0FF3_P_2,
1466
  VEX_W_0FF4_P_2,
1467
  VEX_W_0FF5_P_2,
1468
  VEX_W_0FF6_P_2,
1469
  VEX_W_0FF7_P_2,
1470
  VEX_W_0FF8_P_2,
1471
  VEX_W_0FF9_P_2,
1472
  VEX_W_0FFA_P_2,
1473
  VEX_W_0FFB_P_2,
1474
  VEX_W_0FFC_P_2,
1475
  VEX_W_0FFD_P_2,
1476
  VEX_W_0FFE_P_2,
1477
  VEX_W_0F3800_P_2,
1478
  VEX_W_0F3801_P_2,
1479
  VEX_W_0F3802_P_2,
1480
  VEX_W_0F3803_P_2,
1481
  VEX_W_0F3804_P_2,
1482
  VEX_W_0F3805_P_2,
1483
  VEX_W_0F3806_P_2,
1484
  VEX_W_0F3807_P_2,
1485
  VEX_W_0F3808_P_2,
1486
  VEX_W_0F3809_P_2,
1487
  VEX_W_0F380A_P_2,
1488
  VEX_W_0F380B_P_2,
1489
  VEX_W_0F380C_P_2,
1490
  VEX_W_0F380D_P_2,
1491
  VEX_W_0F380E_P_2,
1492
  VEX_W_0F380F_P_2,
1493 148 khays
  VEX_W_0F3816_P_2,
1494 18 khays
  VEX_W_0F3817_P_2,
1495 148 khays
  VEX_W_0F3818_P_2,
1496
  VEX_W_0F3819_P_2,
1497 18 khays
  VEX_W_0F381A_P_2_M_0,
1498
  VEX_W_0F381C_P_2,
1499
  VEX_W_0F381D_P_2,
1500
  VEX_W_0F381E_P_2,
1501
  VEX_W_0F3820_P_2,
1502
  VEX_W_0F3821_P_2,
1503
  VEX_W_0F3822_P_2,
1504
  VEX_W_0F3823_P_2,
1505
  VEX_W_0F3824_P_2,
1506
  VEX_W_0F3825_P_2,
1507
  VEX_W_0F3828_P_2,
1508
  VEX_W_0F3829_P_2,
1509
  VEX_W_0F382A_P_2_M_0,
1510
  VEX_W_0F382B_P_2,
1511
  VEX_W_0F382C_P_2_M_0,
1512
  VEX_W_0F382D_P_2_M_0,
1513
  VEX_W_0F382E_P_2_M_0,
1514
  VEX_W_0F382F_P_2_M_0,
1515
  VEX_W_0F3830_P_2,
1516
  VEX_W_0F3831_P_2,
1517
  VEX_W_0F3832_P_2,
1518
  VEX_W_0F3833_P_2,
1519
  VEX_W_0F3834_P_2,
1520
  VEX_W_0F3835_P_2,
1521 148 khays
  VEX_W_0F3836_P_2,
1522 18 khays
  VEX_W_0F3837_P_2,
1523
  VEX_W_0F3838_P_2,
1524
  VEX_W_0F3839_P_2,
1525
  VEX_W_0F383A_P_2,
1526
  VEX_W_0F383B_P_2,
1527
  VEX_W_0F383C_P_2,
1528
  VEX_W_0F383D_P_2,
1529
  VEX_W_0F383E_P_2,
1530
  VEX_W_0F383F_P_2,
1531
  VEX_W_0F3840_P_2,
1532
  VEX_W_0F3841_P_2,
1533 148 khays
  VEX_W_0F3846_P_2,
1534
  VEX_W_0F3858_P_2,
1535
  VEX_W_0F3859_P_2,
1536
  VEX_W_0F385A_P_2_M_0,
1537
  VEX_W_0F3878_P_2,
1538
  VEX_W_0F3879_P_2,
1539 18 khays
  VEX_W_0F38DB_P_2,
1540
  VEX_W_0F38DC_P_2,
1541
  VEX_W_0F38DD_P_2,
1542
  VEX_W_0F38DE_P_2,
1543
  VEX_W_0F38DF_P_2,
1544 148 khays
  VEX_W_0F3A00_P_2,
1545
  VEX_W_0F3A01_P_2,
1546
  VEX_W_0F3A02_P_2,
1547 18 khays
  VEX_W_0F3A04_P_2,
1548
  VEX_W_0F3A05_P_2,
1549
  VEX_W_0F3A06_P_2,
1550
  VEX_W_0F3A08_P_2,
1551
  VEX_W_0F3A09_P_2,
1552
  VEX_W_0F3A0A_P_2,
1553
  VEX_W_0F3A0B_P_2,
1554
  VEX_W_0F3A0C_P_2,
1555
  VEX_W_0F3A0D_P_2,
1556
  VEX_W_0F3A0E_P_2,
1557
  VEX_W_0F3A0F_P_2,
1558
  VEX_W_0F3A14_P_2,
1559
  VEX_W_0F3A15_P_2,
1560
  VEX_W_0F3A18_P_2,
1561
  VEX_W_0F3A19_P_2,
1562
  VEX_W_0F3A20_P_2,
1563
  VEX_W_0F3A21_P_2,
1564 148 khays
  VEX_W_0F3A38_P_2,
1565
  VEX_W_0F3A39_P_2,
1566 18 khays
  VEX_W_0F3A40_P_2,
1567
  VEX_W_0F3A41_P_2,
1568
  VEX_W_0F3A42_P_2,
1569
  VEX_W_0F3A44_P_2,
1570 148 khays
  VEX_W_0F3A46_P_2,
1571 18 khays
  VEX_W_0F3A48_P_2,
1572
  VEX_W_0F3A49_P_2,
1573
  VEX_W_0F3A4A_P_2,
1574
  VEX_W_0F3A4B_P_2,
1575
  VEX_W_0F3A4C_P_2,
1576
  VEX_W_0F3A60_P_2,
1577
  VEX_W_0F3A61_P_2,
1578
  VEX_W_0F3A62_P_2,
1579
  VEX_W_0F3A63_P_2,
1580
  VEX_W_0F3ADF_P_2
1581
};
1582
 
1583
typedef void (*op_rtn) (int bytemode, int sizeflag);
1584
 
1585
struct dis386 {
1586
  const char *name;
1587
  struct
1588
    {
1589
      op_rtn rtn;
1590
      int bytemode;
1591
    } op[MAX_OPERANDS];
1592
};
1593
 
1594
/* Upper case letters in the instruction names here are macros.
1595
   'A' => print 'b' if no register operands or suffix_always is true
1596
   'B' => print 'b' if suffix_always is true
1597
   'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1598
          size prefix
1599
   'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1600
          suffix_always is true
1601
   'E' => print 'e' if 32-bit form of jcxz
1602
   'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1603
   'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1604
   'H' => print ",pt" or ",pn" branch hint
1605
   'I' => honor following macro letter even in Intel mode (implemented only
1606
          for some of the macro letters)
1607
   'J' => print 'l'
1608
   'K' => print 'd' or 'q' if rex prefix is present.
1609
   'L' => print 'l' if suffix_always is true
1610
   'M' => print 'r' if intel_mnemonic is false.
1611
   'N' => print 'n' if instruction has no wait "prefix"
1612
   'O' => print 'd' or 'o' (or 'q' in Intel mode)
1613
   'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1614
          or suffix_always is true.  print 'q' if rex prefix is present.
1615
   'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1616
          is true
1617
   'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1618
   'S' => print 'w', 'l' or 'q' if suffix_always is true
1619
   'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1620
   'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1621
   'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1622
   'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1623
   'X' => print 's', 'd' depending on data16 prefix (for XMM)
1624
   'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1625
          suffix_always is true.
1626
   'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1627
   '!' => change condition from true to false or from false to true.
1628
   '%' => add 1 upper case letter to the macro.
1629
 
1630
   2 upper case letter macros:
1631
   "XY" => print 'x' or 'y' if no register operands or suffix_always
1632
           is true.
1633
   "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1634
   "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1635
           or suffix_always is true
1636
   "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1637
   "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1638
   "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1639 148 khays
   "LW" => print 'd', 'q' depending on the VEX.W bit
1640 18 khays
 
1641
   Many of the above letters print nothing in Intel mode.  See "putop"
1642
   for the details.
1643
 
1644
   Braces '{' and '}', and vertical bars '|', indicate alternative
1645
   mnemonic strings for AT&T and Intel.  */
1646
 
1647
static const struct dis386 dis386[] = {
1648
  /* 00 */
1649
  { "addB",             { Eb, Gb } },
1650
  { "addS",             { Ev, Gv } },
1651
  { "addB",             { Gb, EbS } },
1652
  { "addS",             { Gv, EvS } },
1653
  { "addB",             { AL, Ib } },
1654
  { "addS",             { eAX, Iv } },
1655
  { X86_64_TABLE (X86_64_06) },
1656
  { X86_64_TABLE (X86_64_07) },
1657
  /* 08 */
1658
  { "orB",              { Eb, Gb } },
1659
  { "orS",              { Ev, Gv } },
1660
  { "orB",              { Gb, EbS } },
1661
  { "orS",              { Gv, EvS } },
1662
  { "orB",              { AL, Ib } },
1663
  { "orS",              { eAX, Iv } },
1664
  { X86_64_TABLE (X86_64_0D) },
1665
  { Bad_Opcode },       /* 0x0f extended opcode escape */
1666
  /* 10 */
1667
  { "adcB",             { Eb, Gb } },
1668
  { "adcS",             { Ev, Gv } },
1669
  { "adcB",             { Gb, EbS } },
1670
  { "adcS",             { Gv, EvS } },
1671
  { "adcB",             { AL, Ib } },
1672
  { "adcS",             { eAX, Iv } },
1673
  { X86_64_TABLE (X86_64_16) },
1674
  { X86_64_TABLE (X86_64_17) },
1675
  /* 18 */
1676
  { "sbbB",             { Eb, Gb } },
1677
  { "sbbS",             { Ev, Gv } },
1678
  { "sbbB",             { Gb, EbS } },
1679
  { "sbbS",             { Gv, EvS } },
1680
  { "sbbB",             { AL, Ib } },
1681
  { "sbbS",             { eAX, Iv } },
1682
  { X86_64_TABLE (X86_64_1E) },
1683
  { X86_64_TABLE (X86_64_1F) },
1684
  /* 20 */
1685
  { "andB",             { Eb, Gb } },
1686
  { "andS",             { Ev, Gv } },
1687
  { "andB",             { Gb, EbS } },
1688
  { "andS",             { Gv, EvS } },
1689
  { "andB",             { AL, Ib } },
1690
  { "andS",             { eAX, Iv } },
1691
  { Bad_Opcode },       /* SEG ES prefix */
1692
  { X86_64_TABLE (X86_64_27) },
1693
  /* 28 */
1694
  { "subB",             { Eb, Gb } },
1695
  { "subS",             { Ev, Gv } },
1696
  { "subB",             { Gb, EbS } },
1697
  { "subS",             { Gv, EvS } },
1698
  { "subB",             { AL, Ib } },
1699
  { "subS",             { eAX, Iv } },
1700
  { Bad_Opcode },       /* SEG CS prefix */
1701
  { X86_64_TABLE (X86_64_2F) },
1702
  /* 30 */
1703
  { "xorB",             { Eb, Gb } },
1704
  { "xorS",             { Ev, Gv } },
1705
  { "xorB",             { Gb, EbS } },
1706
  { "xorS",             { Gv, EvS } },
1707
  { "xorB",             { AL, Ib } },
1708
  { "xorS",             { eAX, Iv } },
1709
  { Bad_Opcode },       /* SEG SS prefix */
1710
  { X86_64_TABLE (X86_64_37) },
1711
  /* 38 */
1712
  { "cmpB",             { Eb, Gb } },
1713
  { "cmpS",             { Ev, Gv } },
1714
  { "cmpB",             { Gb, EbS } },
1715
  { "cmpS",             { Gv, EvS } },
1716
  { "cmpB",             { AL, Ib } },
1717
  { "cmpS",             { eAX, Iv } },
1718
  { Bad_Opcode },       /* SEG DS prefix */
1719
  { X86_64_TABLE (X86_64_3F) },
1720
  /* 40 */
1721
  { "inc{S|}",          { RMeAX } },
1722
  { "inc{S|}",          { RMeCX } },
1723
  { "inc{S|}",          { RMeDX } },
1724
  { "inc{S|}",          { RMeBX } },
1725
  { "inc{S|}",          { RMeSP } },
1726
  { "inc{S|}",          { RMeBP } },
1727
  { "inc{S|}",          { RMeSI } },
1728
  { "inc{S|}",          { RMeDI } },
1729
  /* 48 */
1730
  { "dec{S|}",          { RMeAX } },
1731
  { "dec{S|}",          { RMeCX } },
1732
  { "dec{S|}",          { RMeDX } },
1733
  { "dec{S|}",          { RMeBX } },
1734
  { "dec{S|}",          { RMeSP } },
1735
  { "dec{S|}",          { RMeBP } },
1736
  { "dec{S|}",          { RMeSI } },
1737
  { "dec{S|}",          { RMeDI } },
1738
  /* 50 */
1739
  { "pushV",            { RMrAX } },
1740
  { "pushV",            { RMrCX } },
1741
  { "pushV",            { RMrDX } },
1742
  { "pushV",            { RMrBX } },
1743
  { "pushV",            { RMrSP } },
1744
  { "pushV",            { RMrBP } },
1745
  { "pushV",            { RMrSI } },
1746
  { "pushV",            { RMrDI } },
1747
  /* 58 */
1748
  { "popV",             { RMrAX } },
1749
  { "popV",             { RMrCX } },
1750
  { "popV",             { RMrDX } },
1751
  { "popV",             { RMrBX } },
1752
  { "popV",             { RMrSP } },
1753
  { "popV",             { RMrBP } },
1754
  { "popV",             { RMrSI } },
1755
  { "popV",             { RMrDI } },
1756
  /* 60 */
1757
  { X86_64_TABLE (X86_64_60) },
1758
  { X86_64_TABLE (X86_64_61) },
1759
  { X86_64_TABLE (X86_64_62) },
1760
  { X86_64_TABLE (X86_64_63) },
1761
  { Bad_Opcode },       /* seg fs */
1762
  { Bad_Opcode },       /* seg gs */
1763
  { Bad_Opcode },       /* op size prefix */
1764
  { Bad_Opcode },       /* adr size prefix */
1765
  /* 68 */
1766
  { "pushT",            { sIv } },
1767
  { "imulS",            { Gv, Ev, Iv } },
1768
  { "pushT",            { sIbT } },
1769
  { "imulS",            { Gv, Ev, sIb } },
1770
  { "ins{b|}",          { Ybr, indirDX } },
1771
  { X86_64_TABLE (X86_64_6D) },
1772
  { "outs{b|}",         { indirDXr, Xb } },
1773
  { X86_64_TABLE (X86_64_6F) },
1774
  /* 70 */
1775
  { "joH",              { Jb, XX, cond_jump_flag } },
1776
  { "jnoH",             { Jb, XX, cond_jump_flag } },
1777
  { "jbH",              { Jb, XX, cond_jump_flag } },
1778
  { "jaeH",             { Jb, XX, cond_jump_flag } },
1779
  { "jeH",              { Jb, XX, cond_jump_flag } },
1780
  { "jneH",             { Jb, XX, cond_jump_flag } },
1781
  { "jbeH",             { Jb, XX, cond_jump_flag } },
1782
  { "jaH",              { Jb, XX, cond_jump_flag } },
1783
  /* 78 */
1784
  { "jsH",              { Jb, XX, cond_jump_flag } },
1785
  { "jnsH",             { Jb, XX, cond_jump_flag } },
1786
  { "jpH",              { Jb, XX, cond_jump_flag } },
1787
  { "jnpH",             { Jb, XX, cond_jump_flag } },
1788
  { "jlH",              { Jb, XX, cond_jump_flag } },
1789
  { "jgeH",             { Jb, XX, cond_jump_flag } },
1790
  { "jleH",             { Jb, XX, cond_jump_flag } },
1791
  { "jgH",              { Jb, XX, cond_jump_flag } },
1792
  /* 80 */
1793
  { REG_TABLE (REG_80) },
1794
  { REG_TABLE (REG_81) },
1795
  { Bad_Opcode },
1796
  { REG_TABLE (REG_82) },
1797
  { "testB",            { Eb, Gb } },
1798
  { "testS",            { Ev, Gv } },
1799
  { "xchgB",            { Eb, Gb } },
1800
  { "xchgS",            { Ev, Gv } },
1801
  /* 88 */
1802
  { "movB",             { Eb, Gb } },
1803
  { "movS",             { Ev, Gv } },
1804
  { "movB",             { Gb, EbS } },
1805
  { "movS",             { Gv, EvS } },
1806
  { "movD",             { Sv, Sw } },
1807
  { MOD_TABLE (MOD_8D) },
1808
  { "movD",             { Sw, Sv } },
1809
  { REG_TABLE (REG_8F) },
1810
  /* 90 */
1811
  { PREFIX_TABLE (PREFIX_90) },
1812
  { "xchgS",            { RMeCX, eAX } },
1813
  { "xchgS",            { RMeDX, eAX } },
1814
  { "xchgS",            { RMeBX, eAX } },
1815
  { "xchgS",            { RMeSP, eAX } },
1816
  { "xchgS",            { RMeBP, eAX } },
1817
  { "xchgS",            { RMeSI, eAX } },
1818
  { "xchgS",            { RMeDI, eAX } },
1819
  /* 98 */
1820
  { "cW{t|}R",          { XX } },
1821
  { "cR{t|}O",          { XX } },
1822
  { X86_64_TABLE (X86_64_9A) },
1823
  { Bad_Opcode },       /* fwait */
1824
  { "pushfT",           { XX } },
1825
  { "popfT",            { XX } },
1826
  { "sahf",             { XX } },
1827
  { "lahf",             { XX } },
1828
  /* a0 */
1829
  { "mov%LB",           { AL, Ob } },
1830
  { "mov%LS",           { eAX, Ov } },
1831
  { "mov%LB",           { Ob, AL } },
1832
  { "mov%LS",           { Ov, eAX } },
1833
  { "movs{b|}",         { Ybr, Xb } },
1834
  { "movs{R|}",         { Yvr, Xv } },
1835
  { "cmps{b|}",         { Xb, Yb } },
1836
  { "cmps{R|}",         { Xv, Yv } },
1837
  /* a8 */
1838
  { "testB",            { AL, Ib } },
1839
  { "testS",            { eAX, Iv } },
1840
  { "stosB",            { Ybr, AL } },
1841
  { "stosS",            { Yvr, eAX } },
1842
  { "lodsB",            { ALr, Xb } },
1843
  { "lodsS",            { eAXr, Xv } },
1844
  { "scasB",            { AL, Yb } },
1845
  { "scasS",            { eAX, Yv } },
1846
  /* b0 */
1847
  { "movB",             { RMAL, Ib } },
1848
  { "movB",             { RMCL, Ib } },
1849
  { "movB",             { RMDL, Ib } },
1850
  { "movB",             { RMBL, Ib } },
1851
  { "movB",             { RMAH, Ib } },
1852
  { "movB",             { RMCH, Ib } },
1853
  { "movB",             { RMDH, Ib } },
1854
  { "movB",             { RMBH, Ib } },
1855
  /* b8 */
1856
  { "mov%LV",           { RMeAX, Iv64 } },
1857
  { "mov%LV",           { RMeCX, Iv64 } },
1858
  { "mov%LV",           { RMeDX, Iv64 } },
1859
  { "mov%LV",           { RMeBX, Iv64 } },
1860
  { "mov%LV",           { RMeSP, Iv64 } },
1861
  { "mov%LV",           { RMeBP, Iv64 } },
1862
  { "mov%LV",           { RMeSI, Iv64 } },
1863
  { "mov%LV",           { RMeDI, Iv64 } },
1864
  /* c0 */
1865
  { REG_TABLE (REG_C0) },
1866
  { REG_TABLE (REG_C1) },
1867
  { "retT",             { Iw } },
1868
  { "retT",             { XX } },
1869
  { X86_64_TABLE (X86_64_C4) },
1870
  { X86_64_TABLE (X86_64_C5) },
1871
  { REG_TABLE (REG_C6) },
1872
  { REG_TABLE (REG_C7) },
1873
  /* c8 */
1874
  { "enterT",           { Iw, Ib } },
1875
  { "leaveT",           { XX } },
1876
  { "Jret{|f}P",        { Iw } },
1877
  { "Jret{|f}P",        { XX } },
1878
  { "int3",             { XX } },
1879
  { "int",              { Ib } },
1880
  { X86_64_TABLE (X86_64_CE) },
1881
  { "iretP",            { XX } },
1882
  /* d0 */
1883
  { REG_TABLE (REG_D0) },
1884
  { REG_TABLE (REG_D1) },
1885
  { REG_TABLE (REG_D2) },
1886
  { REG_TABLE (REG_D3) },
1887
  { X86_64_TABLE (X86_64_D4) },
1888
  { X86_64_TABLE (X86_64_D5) },
1889
  { Bad_Opcode },
1890
  { "xlat",             { DSBX } },
1891
  /* d8 */
1892
  { FLOAT },
1893
  { FLOAT },
1894
  { FLOAT },
1895
  { FLOAT },
1896
  { FLOAT },
1897
  { FLOAT },
1898
  { FLOAT },
1899
  { FLOAT },
1900
  /* e0 */
1901
  { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1902
  { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1903
  { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1904
  { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1905
  { "inB",              { AL, Ib } },
1906
  { "inG",              { zAX, Ib } },
1907
  { "outB",             { Ib, AL } },
1908
  { "outG",             { Ib, zAX } },
1909
  /* e8 */
1910
  { "callT",            { Jv } },
1911
  { "jmpT",             { Jv } },
1912
  { X86_64_TABLE (X86_64_EA) },
1913
  { "jmp",              { Jb } },
1914
  { "inB",              { AL, indirDX } },
1915
  { "inG",              { zAX, indirDX } },
1916
  { "outB",             { indirDX, AL } },
1917
  { "outG",             { indirDX, zAX } },
1918
  /* f0 */
1919
  { Bad_Opcode },       /* lock prefix */
1920
  { "icebp",            { XX } },
1921
  { Bad_Opcode },       /* repne */
1922
  { Bad_Opcode },       /* repz */
1923
  { "hlt",              { XX } },
1924
  { "cmc",              { XX } },
1925
  { REG_TABLE (REG_F6) },
1926
  { REG_TABLE (REG_F7) },
1927
  /* f8 */
1928
  { "clc",              { XX } },
1929
  { "stc",              { XX } },
1930
  { "cli",              { XX } },
1931
  { "sti",              { XX } },
1932
  { "cld",              { XX } },
1933
  { "std",              { XX } },
1934
  { REG_TABLE (REG_FE) },
1935
  { REG_TABLE (REG_FF) },
1936
};
1937
 
1938
static const struct dis386 dis386_twobyte[] = {
1939
  /* 00 */
1940
  { REG_TABLE (REG_0F00 ) },
1941
  { REG_TABLE (REG_0F01 ) },
1942
  { "larS",             { Gv, Ew } },
1943
  { "lslS",             { Gv, Ew } },
1944
  { Bad_Opcode },
1945
  { "syscall",          { XX } },
1946
  { "clts",             { XX } },
1947
  { "sysretP",          { XX } },
1948
  /* 08 */
1949
  { "invd",             { XX } },
1950
  { "wbinvd",           { XX } },
1951
  { Bad_Opcode },
1952
  { "ud2",              { XX } },
1953
  { Bad_Opcode },
1954
  { REG_TABLE (REG_0F0D) },
1955
  { "femms",            { XX } },
1956
  { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1957
  /* 10 */
1958
  { PREFIX_TABLE (PREFIX_0F10) },
1959
  { PREFIX_TABLE (PREFIX_0F11) },
1960
  { PREFIX_TABLE (PREFIX_0F12) },
1961
  { MOD_TABLE (MOD_0F13) },
1962
  { "unpcklpX",         { XM, EXx } },
1963
  { "unpckhpX",         { XM, EXx } },
1964
  { PREFIX_TABLE (PREFIX_0F16) },
1965
  { MOD_TABLE (MOD_0F17) },
1966
  /* 18 */
1967
  { REG_TABLE (REG_0F18) },
1968
  { "nopQ",             { Ev } },
1969
  { "nopQ",             { Ev } },
1970
  { "nopQ",             { Ev } },
1971
  { "nopQ",             { Ev } },
1972
  { "nopQ",             { Ev } },
1973
  { "nopQ",             { Ev } },
1974
  { "nopQ",             { Ev } },
1975
  /* 20 */
1976
  { MOD_TABLE (MOD_0F20) },
1977
  { MOD_TABLE (MOD_0F21) },
1978
  { MOD_TABLE (MOD_0F22) },
1979
  { MOD_TABLE (MOD_0F23) },
1980
  { MOD_TABLE (MOD_0F24) },
1981
  { Bad_Opcode },
1982
  { MOD_TABLE (MOD_0F26) },
1983
  { Bad_Opcode },
1984
  /* 28 */
1985
  { "movapX",           { XM, EXx } },
1986
  { "movapX",           { EXxS, XM } },
1987
  { PREFIX_TABLE (PREFIX_0F2A) },
1988
  { PREFIX_TABLE (PREFIX_0F2B) },
1989
  { PREFIX_TABLE (PREFIX_0F2C) },
1990
  { PREFIX_TABLE (PREFIX_0F2D) },
1991
  { PREFIX_TABLE (PREFIX_0F2E) },
1992
  { PREFIX_TABLE (PREFIX_0F2F) },
1993
  /* 30 */
1994
  { "wrmsr",            { XX } },
1995
  { "rdtsc",            { XX } },
1996
  { "rdmsr",            { XX } },
1997
  { "rdpmc",            { XX } },
1998
  { "sysenter",         { XX } },
1999
  { "sysexit",          { XX } },
2000
  { Bad_Opcode },
2001
  { "getsec",           { XX } },
2002
  /* 38 */
2003
  { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2004
  { Bad_Opcode },
2005
  { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2006
  { Bad_Opcode },
2007
  { Bad_Opcode },
2008
  { Bad_Opcode },
2009
  { Bad_Opcode },
2010
  { Bad_Opcode },
2011
  /* 40 */
2012
  { "cmovoS",           { Gv, Ev } },
2013
  { "cmovnoS",          { Gv, Ev } },
2014
  { "cmovbS",           { Gv, Ev } },
2015
  { "cmovaeS",          { Gv, Ev } },
2016
  { "cmoveS",           { Gv, Ev } },
2017
  { "cmovneS",          { Gv, Ev } },
2018
  { "cmovbeS",          { Gv, Ev } },
2019
  { "cmovaS",           { Gv, Ev } },
2020
  /* 48 */
2021
  { "cmovsS",           { Gv, Ev } },
2022
  { "cmovnsS",          { Gv, Ev } },
2023
  { "cmovpS",           { Gv, Ev } },
2024
  { "cmovnpS",          { Gv, Ev } },
2025
  { "cmovlS",           { Gv, Ev } },
2026
  { "cmovgeS",          { Gv, Ev } },
2027
  { "cmovleS",          { Gv, Ev } },
2028
  { "cmovgS",           { Gv, Ev } },
2029
  /* 50 */
2030
  { MOD_TABLE (MOD_0F51) },
2031
  { PREFIX_TABLE (PREFIX_0F51) },
2032
  { PREFIX_TABLE (PREFIX_0F52) },
2033
  { PREFIX_TABLE (PREFIX_0F53) },
2034
  { "andpX",            { XM, EXx } },
2035
  { "andnpX",           { XM, EXx } },
2036
  { "orpX",             { XM, EXx } },
2037
  { "xorpX",            { XM, EXx } },
2038
  /* 58 */
2039
  { PREFIX_TABLE (PREFIX_0F58) },
2040
  { PREFIX_TABLE (PREFIX_0F59) },
2041
  { PREFIX_TABLE (PREFIX_0F5A) },
2042
  { PREFIX_TABLE (PREFIX_0F5B) },
2043
  { PREFIX_TABLE (PREFIX_0F5C) },
2044
  { PREFIX_TABLE (PREFIX_0F5D) },
2045
  { PREFIX_TABLE (PREFIX_0F5E) },
2046
  { PREFIX_TABLE (PREFIX_0F5F) },
2047
  /* 60 */
2048
  { PREFIX_TABLE (PREFIX_0F60) },
2049
  { PREFIX_TABLE (PREFIX_0F61) },
2050
  { PREFIX_TABLE (PREFIX_0F62) },
2051
  { "packsswb",         { MX, EM } },
2052
  { "pcmpgtb",          { MX, EM } },
2053
  { "pcmpgtw",          { MX, EM } },
2054
  { "pcmpgtd",          { MX, EM } },
2055
  { "packuswb",         { MX, EM } },
2056
  /* 68 */
2057
  { "punpckhbw",        { MX, EM } },
2058
  { "punpckhwd",        { MX, EM } },
2059
  { "punpckhdq",        { MX, EM } },
2060
  { "packssdw",         { MX, EM } },
2061
  { PREFIX_TABLE (PREFIX_0F6C) },
2062
  { PREFIX_TABLE (PREFIX_0F6D) },
2063
  { "movK",             { MX, Edq } },
2064
  { PREFIX_TABLE (PREFIX_0F6F) },
2065
  /* 70 */
2066
  { PREFIX_TABLE (PREFIX_0F70) },
2067
  { REG_TABLE (REG_0F71) },
2068
  { REG_TABLE (REG_0F72) },
2069
  { REG_TABLE (REG_0F73) },
2070
  { "pcmpeqb",          { MX, EM } },
2071
  { "pcmpeqw",          { MX, EM } },
2072
  { "pcmpeqd",          { MX, EM } },
2073
  { "emms",             { XX } },
2074
  /* 78 */
2075
  { PREFIX_TABLE (PREFIX_0F78) },
2076
  { PREFIX_TABLE (PREFIX_0F79) },
2077
  { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2078
  { Bad_Opcode },
2079
  { PREFIX_TABLE (PREFIX_0F7C) },
2080
  { PREFIX_TABLE (PREFIX_0F7D) },
2081
  { PREFIX_TABLE (PREFIX_0F7E) },
2082
  { PREFIX_TABLE (PREFIX_0F7F) },
2083
  /* 80 */
2084
  { "joH",              { Jv, XX, cond_jump_flag } },
2085
  { "jnoH",             { Jv, XX, cond_jump_flag } },
2086
  { "jbH",              { Jv, XX, cond_jump_flag } },
2087
  { "jaeH",             { Jv, XX, cond_jump_flag } },
2088
  { "jeH",              { Jv, XX, cond_jump_flag } },
2089
  { "jneH",             { Jv, XX, cond_jump_flag } },
2090
  { "jbeH",             { Jv, XX, cond_jump_flag } },
2091
  { "jaH",              { Jv, XX, cond_jump_flag } },
2092
  /* 88 */
2093
  { "jsH",              { Jv, XX, cond_jump_flag } },
2094
  { "jnsH",             { Jv, XX, cond_jump_flag } },
2095
  { "jpH",              { Jv, XX, cond_jump_flag } },
2096
  { "jnpH",             { Jv, XX, cond_jump_flag } },
2097
  { "jlH",              { Jv, XX, cond_jump_flag } },
2098
  { "jgeH",             { Jv, XX, cond_jump_flag } },
2099
  { "jleH",             { Jv, XX, cond_jump_flag } },
2100
  { "jgH",              { Jv, XX, cond_jump_flag } },
2101
  /* 90 */
2102
  { "seto",             { Eb } },
2103
  { "setno",            { Eb } },
2104
  { "setb",             { Eb } },
2105
  { "setae",            { Eb } },
2106
  { "sete",             { Eb } },
2107
  { "setne",            { Eb } },
2108
  { "setbe",            { Eb } },
2109
  { "seta",             { Eb } },
2110
  /* 98 */
2111
  { "sets",             { Eb } },
2112
  { "setns",            { Eb } },
2113
  { "setp",             { Eb } },
2114
  { "setnp",            { Eb } },
2115
  { "setl",             { Eb } },
2116
  { "setge",            { Eb } },
2117
  { "setle",            { Eb } },
2118
  { "setg",             { Eb } },
2119
  /* a0 */
2120
  { "pushT",            { fs } },
2121
  { "popT",             { fs } },
2122
  { "cpuid",            { XX } },
2123
  { "btS",              { Ev, Gv } },
2124
  { "shldS",            { Ev, Gv, Ib } },
2125
  { "shldS",            { Ev, Gv, CL } },
2126
  { REG_TABLE (REG_0FA6) },
2127
  { REG_TABLE (REG_0FA7) },
2128
  /* a8 */
2129
  { "pushT",            { gs } },
2130
  { "popT",             { gs } },
2131
  { "rsm",              { XX } },
2132
  { "btsS",             { Ev, Gv } },
2133
  { "shrdS",            { Ev, Gv, Ib } },
2134
  { "shrdS",            { Ev, Gv, CL } },
2135
  { REG_TABLE (REG_0FAE) },
2136
  { "imulS",            { Gv, Ev } },
2137
  /* b0 */
2138
  { "cmpxchgB",         { Eb, Gb } },
2139
  { "cmpxchgS",         { Ev, Gv } },
2140
  { MOD_TABLE (MOD_0FB2) },
2141
  { "btrS",             { Ev, Gv } },
2142
  { MOD_TABLE (MOD_0FB4) },
2143
  { MOD_TABLE (MOD_0FB5) },
2144
  { "movz{bR|x}",       { Gv, Eb } },
2145
  { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2146
  /* b8 */
2147
  { PREFIX_TABLE (PREFIX_0FB8) },
2148
  { "ud1",              { XX } },
2149
  { REG_TABLE (REG_0FBA) },
2150
  { "btcS",             { Ev, Gv } },
2151
  { PREFIX_TABLE (PREFIX_0FBC) },
2152
  { PREFIX_TABLE (PREFIX_0FBD) },
2153
  { "movs{bR|x}",       { Gv, Eb } },
2154
  { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2155
  /* c0 */
2156
  { "xaddB",            { Eb, Gb } },
2157
  { "xaddS",            { Ev, Gv } },
2158
  { PREFIX_TABLE (PREFIX_0FC2) },
2159
  { PREFIX_TABLE (PREFIX_0FC3) },
2160
  { "pinsrw",           { MX, Edqw, Ib } },
2161
  { "pextrw",           { Gdq, MS, Ib } },
2162
  { "shufpX",           { XM, EXx, Ib } },
2163
  { REG_TABLE (REG_0FC7) },
2164
  /* c8 */
2165
  { "bswap",            { RMeAX } },
2166
  { "bswap",            { RMeCX } },
2167
  { "bswap",            { RMeDX } },
2168
  { "bswap",            { RMeBX } },
2169
  { "bswap",            { RMeSP } },
2170
  { "bswap",            { RMeBP } },
2171
  { "bswap",            { RMeSI } },
2172
  { "bswap",            { RMeDI } },
2173
  /* d0 */
2174
  { PREFIX_TABLE (PREFIX_0FD0) },
2175
  { "psrlw",            { MX, EM } },
2176
  { "psrld",            { MX, EM } },
2177
  { "psrlq",            { MX, EM } },
2178
  { "paddq",            { MX, EM } },
2179
  { "pmullw",           { MX, EM } },
2180
  { PREFIX_TABLE (PREFIX_0FD6) },
2181
  { MOD_TABLE (MOD_0FD7) },
2182
  /* d8 */
2183
  { "psubusb",          { MX, EM } },
2184
  { "psubusw",          { MX, EM } },
2185
  { "pminub",           { MX, EM } },
2186
  { "pand",             { MX, EM } },
2187
  { "paddusb",          { MX, EM } },
2188
  { "paddusw",          { MX, EM } },
2189
  { "pmaxub",           { MX, EM } },
2190
  { "pandn",            { MX, EM } },
2191
  /* e0 */
2192
  { "pavgb",            { MX, EM } },
2193
  { "psraw",            { MX, EM } },
2194
  { "psrad",            { MX, EM } },
2195
  { "pavgw",            { MX, EM } },
2196
  { "pmulhuw",          { MX, EM } },
2197
  { "pmulhw",           { MX, EM } },
2198
  { PREFIX_TABLE (PREFIX_0FE6) },
2199
  { PREFIX_TABLE (PREFIX_0FE7) },
2200
  /* e8 */
2201
  { "psubsb",           { MX, EM } },
2202
  { "psubsw",           { MX, EM } },
2203
  { "pminsw",           { MX, EM } },
2204
  { "por",              { MX, EM } },
2205
  { "paddsb",           { MX, EM } },
2206
  { "paddsw",           { MX, EM } },
2207
  { "pmaxsw",           { MX, EM } },
2208
  { "pxor",             { MX, EM } },
2209
  /* f0 */
2210
  { PREFIX_TABLE (PREFIX_0FF0) },
2211
  { "psllw",            { MX, EM } },
2212
  { "pslld",            { MX, EM } },
2213
  { "psllq",            { MX, EM } },
2214
  { "pmuludq",          { MX, EM } },
2215
  { "pmaddwd",          { MX, EM } },
2216
  { "psadbw",           { MX, EM } },
2217
  { PREFIX_TABLE (PREFIX_0FF7) },
2218
  /* f8 */
2219
  { "psubb",            { MX, EM } },
2220
  { "psubw",            { MX, EM } },
2221
  { "psubd",            { MX, EM } },
2222
  { "psubq",            { MX, EM } },
2223
  { "paddb",            { MX, EM } },
2224
  { "paddw",            { MX, EM } },
2225
  { "paddd",            { MX, EM } },
2226
  { Bad_Opcode },
2227
};
2228
 
2229
static const unsigned char onebyte_has_modrm[256] = {
2230
  /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2231
  /*       -------------------------------        */
2232
  /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2233
  /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2234
  /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2235
  /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2236
  /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2237
  /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2238
  /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2239
  /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2240
  /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2241
  /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2242
  /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2243
  /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2244
  /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2245
  /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2246
  /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2247
  /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2248
  /*       -------------------------------        */
2249
  /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2250
};
2251
 
2252
static const unsigned char twobyte_has_modrm[256] = {
2253
  /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2254
  /*       -------------------------------        */
2255
  /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2256
  /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2257
  /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2258
  /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2259
  /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2260
  /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2261
  /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2262
  /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2263
  /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2264
  /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2265
  /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2266
  /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2267
  /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2268
  /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2269
  /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2270
  /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
2271
  /*       -------------------------------        */
2272
  /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2273
};
2274
 
2275
static char obuf[100];
2276
static char *obufp;
2277
static char *mnemonicendp;
2278
static char scratchbuf[100];
2279
static unsigned char *start_codep;
2280
static unsigned char *insn_codep;
2281
static unsigned char *codep;
2282
static int last_lock_prefix;
2283
static int last_repz_prefix;
2284
static int last_repnz_prefix;
2285
static int last_data_prefix;
2286
static int last_addr_prefix;
2287
static int last_rex_prefix;
2288
static int last_seg_prefix;
2289
#define MAX_CODE_LENGTH 15
2290
/* We can up to 14 prefixes since the maximum instruction length is
2291
   15bytes.  */
2292
static int all_prefixes[MAX_CODE_LENGTH - 1];
2293
static disassemble_info *the_info;
2294
static struct
2295
  {
2296
    int mod;
2297
    int reg;
2298
    int rm;
2299
  }
2300
modrm;
2301
static unsigned char need_modrm;
2302
static struct
2303
  {
2304
    int scale;
2305
    int index;
2306
    int base;
2307
  }
2308
sib;
2309
static struct
2310
  {
2311
    int register_specifier;
2312
    int length;
2313
    int prefix;
2314
    int w;
2315
  }
2316
vex;
2317
static unsigned char need_vex;
2318
static unsigned char need_vex_reg;
2319
static unsigned char vex_w_done;
2320
 
2321
struct op
2322
  {
2323
    const char *name;
2324
    unsigned int len;
2325
  };
2326
 
2327
/* If we are accessing mod/rm/reg without need_modrm set, then the
2328
   values are stale.  Hitting this abort likely indicates that you
2329
   need to update onebyte_has_modrm or twobyte_has_modrm.  */
2330
#define MODRM_CHECK  if (!need_modrm) abort ()
2331
 
2332
static const char **names64;
2333
static const char **names32;
2334
static const char **names16;
2335
static const char **names8;
2336
static const char **names8rex;
2337
static const char **names_seg;
2338
static const char *index64;
2339
static const char *index32;
2340
static const char **index16;
2341
 
2342
static const char *intel_names64[] = {
2343
  "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2344
  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2345
};
2346
static const char *intel_names32[] = {
2347
  "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2348
  "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2349
};
2350
static const char *intel_names16[] = {
2351
  "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2352
  "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2353
};
2354
static const char *intel_names8[] = {
2355
  "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2356
};
2357
static const char *intel_names8rex[] = {
2358
  "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2359
  "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2360
};
2361
static const char *intel_names_seg[] = {
2362
  "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2363
};
2364
static const char *intel_index64 = "riz";
2365
static const char *intel_index32 = "eiz";
2366
static const char *intel_index16[] = {
2367
  "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2368
};
2369
 
2370
static const char *att_names64[] = {
2371
  "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2372
  "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2373
};
2374
static const char *att_names32[] = {
2375
  "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2376
  "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2377
};
2378
static const char *att_names16[] = {
2379
  "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2380
  "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2381
};
2382
static const char *att_names8[] = {
2383
  "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2384
};
2385
static const char *att_names8rex[] = {
2386
  "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2387
  "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2388
};
2389
static const char *att_names_seg[] = {
2390
  "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2391
};
2392
static const char *att_index64 = "%riz";
2393
static const char *att_index32 = "%eiz";
2394
static const char *att_index16[] = {
2395
  "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2396
};
2397
 
2398
static const char **names_mm;
2399
static const char *intel_names_mm[] = {
2400
  "mm0", "mm1", "mm2", "mm3",
2401
  "mm4", "mm5", "mm6", "mm7"
2402
};
2403
static const char *att_names_mm[] = {
2404
  "%mm0", "%mm1", "%mm2", "%mm3",
2405
  "%mm4", "%mm5", "%mm6", "%mm7"
2406
};
2407
 
2408
static const char **names_xmm;
2409
static const char *intel_names_xmm[] = {
2410
  "xmm0", "xmm1", "xmm2", "xmm3",
2411
  "xmm4", "xmm5", "xmm6", "xmm7",
2412
  "xmm8", "xmm9", "xmm10", "xmm11",
2413
  "xmm12", "xmm13", "xmm14", "xmm15"
2414
};
2415
static const char *att_names_xmm[] = {
2416
  "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2417
  "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2418
  "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2419
  "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2420
};
2421
 
2422
static const char **names_ymm;
2423
static const char *intel_names_ymm[] = {
2424
  "ymm0", "ymm1", "ymm2", "ymm3",
2425
  "ymm4", "ymm5", "ymm6", "ymm7",
2426
  "ymm8", "ymm9", "ymm10", "ymm11",
2427
  "ymm12", "ymm13", "ymm14", "ymm15"
2428
};
2429
static const char *att_names_ymm[] = {
2430
  "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2431
  "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2432
  "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2433
  "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2434
};
2435
 
2436
static const struct dis386 reg_table[][8] = {
2437
  /* REG_80 */
2438
  {
2439
    { "addA",   { Eb, Ib } },
2440
    { "orA",    { Eb, Ib } },
2441
    { "adcA",   { Eb, Ib } },
2442
    { "sbbA",   { Eb, Ib } },
2443
    { "andA",   { Eb, Ib } },
2444
    { "subA",   { Eb, Ib } },
2445
    { "xorA",   { Eb, Ib } },
2446
    { "cmpA",   { Eb, Ib } },
2447
  },
2448
  /* REG_81 */
2449
  {
2450
    { "addQ",   { Ev, Iv } },
2451
    { "orQ",    { Ev, Iv } },
2452
    { "adcQ",   { Ev, Iv } },
2453
    { "sbbQ",   { Ev, Iv } },
2454
    { "andQ",   { Ev, Iv } },
2455
    { "subQ",   { Ev, Iv } },
2456
    { "xorQ",   { Ev, Iv } },
2457
    { "cmpQ",   { Ev, Iv } },
2458
  },
2459
  /* REG_82 */
2460
  {
2461
    { "addQ",   { Ev, sIb } },
2462
    { "orQ",    { Ev, sIb } },
2463
    { "adcQ",   { Ev, sIb } },
2464
    { "sbbQ",   { Ev, sIb } },
2465
    { "andQ",   { Ev, sIb } },
2466
    { "subQ",   { Ev, sIb } },
2467
    { "xorQ",   { Ev, sIb } },
2468
    { "cmpQ",   { Ev, sIb } },
2469
  },
2470
  /* REG_8F */
2471
  {
2472
    { "popU",   { stackEv } },
2473
    { XOP_8F_TABLE (XOP_09) },
2474
    { Bad_Opcode },
2475
    { Bad_Opcode },
2476
    { Bad_Opcode },
2477
    { XOP_8F_TABLE (XOP_09) },
2478
  },
2479
  /* REG_C0 */
2480
  {
2481
    { "rolA",   { Eb, Ib } },
2482
    { "rorA",   { Eb, Ib } },
2483
    { "rclA",   { Eb, Ib } },
2484
    { "rcrA",   { Eb, Ib } },
2485
    { "shlA",   { Eb, Ib } },
2486
    { "shrA",   { Eb, Ib } },
2487
    { Bad_Opcode },
2488
    { "sarA",   { Eb, Ib } },
2489
  },
2490
  /* REG_C1 */
2491
  {
2492
    { "rolQ",   { Ev, Ib } },
2493
    { "rorQ",   { Ev, Ib } },
2494
    { "rclQ",   { Ev, Ib } },
2495
    { "rcrQ",   { Ev, Ib } },
2496
    { "shlQ",   { Ev, Ib } },
2497
    { "shrQ",   { Ev, Ib } },
2498
    { Bad_Opcode },
2499
    { "sarQ",   { Ev, Ib } },
2500
  },
2501
  /* REG_C6 */
2502
  {
2503
    { "movA",   { Eb, Ib } },
2504
  },
2505
  /* REG_C7 */
2506
  {
2507
    { "movQ",   { Ev, Iv } },
2508
  },
2509
  /* REG_D0 */
2510
  {
2511
    { "rolA",   { Eb, I1 } },
2512
    { "rorA",   { Eb, I1 } },
2513
    { "rclA",   { Eb, I1 } },
2514
    { "rcrA",   { Eb, I1 } },
2515
    { "shlA",   { Eb, I1 } },
2516
    { "shrA",   { Eb, I1 } },
2517
    { Bad_Opcode },
2518
    { "sarA",   { Eb, I1 } },
2519
  },
2520
  /* REG_D1 */
2521
  {
2522
    { "rolQ",   { Ev, I1 } },
2523
    { "rorQ",   { Ev, I1 } },
2524
    { "rclQ",   { Ev, I1 } },
2525
    { "rcrQ",   { Ev, I1 } },
2526
    { "shlQ",   { Ev, I1 } },
2527
    { "shrQ",   { Ev, I1 } },
2528
    { Bad_Opcode },
2529
    { "sarQ",   { Ev, I1 } },
2530
  },
2531
  /* REG_D2 */
2532
  {
2533
    { "rolA",   { Eb, CL } },
2534
    { "rorA",   { Eb, CL } },
2535
    { "rclA",   { Eb, CL } },
2536
    { "rcrA",   { Eb, CL } },
2537
    { "shlA",   { Eb, CL } },
2538
    { "shrA",   { Eb, CL } },
2539
    { Bad_Opcode },
2540
    { "sarA",   { Eb, CL } },
2541
  },
2542
  /* REG_D3 */
2543
  {
2544
    { "rolQ",   { Ev, CL } },
2545
    { "rorQ",   { Ev, CL } },
2546
    { "rclQ",   { Ev, CL } },
2547
    { "rcrQ",   { Ev, CL } },
2548
    { "shlQ",   { Ev, CL } },
2549
    { "shrQ",   { Ev, CL } },
2550
    { Bad_Opcode },
2551
    { "sarQ",   { Ev, CL } },
2552
  },
2553
  /* REG_F6 */
2554
  {
2555
    { "testA",  { Eb, Ib } },
2556
    { Bad_Opcode },
2557
    { "notA",   { Eb } },
2558
    { "negA",   { Eb } },
2559
    { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2560
    { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2561
    { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2562
    { "idivA",  { Eb } },       /* and idiv for consistency.               */
2563
  },
2564
  /* REG_F7 */
2565
  {
2566
    { "testQ",  { Ev, Iv } },
2567
    { Bad_Opcode },
2568
    { "notQ",   { Ev } },
2569
    { "negQ",   { Ev } },
2570
    { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2571
    { "imulQ",  { Ev } },
2572
    { "divQ",   { Ev } },
2573
    { "idivQ",  { Ev } },
2574
  },
2575
  /* REG_FE */
2576
  {
2577
    { "incA",   { Eb } },
2578
    { "decA",   { Eb } },
2579
  },
2580
  /* REG_FF */
2581
  {
2582
    { "incQ",   { Ev } },
2583
    { "decQ",   { Ev } },
2584
    { "call{T|}", { indirEv } },
2585
    { "Jcall{T|}", { indirEp } },
2586
    { "jmp{T|}", { indirEv } },
2587
    { "Jjmp{T|}", { indirEp } },
2588
    { "pushU",  { stackEv } },
2589
    { Bad_Opcode },
2590
  },
2591
  /* REG_0F00 */
2592
  {
2593
    { "sldtD",  { Sv } },
2594
    { "strD",   { Sv } },
2595
    { "lldt",   { Ew } },
2596
    { "ltr",    { Ew } },
2597
    { "verr",   { Ew } },
2598
    { "verw",   { Ew } },
2599
    { Bad_Opcode },
2600
    { Bad_Opcode },
2601
  },
2602
  /* REG_0F01 */
2603
  {
2604
    { MOD_TABLE (MOD_0F01_REG_0) },
2605
    { MOD_TABLE (MOD_0F01_REG_1) },
2606
    { MOD_TABLE (MOD_0F01_REG_2) },
2607
    { MOD_TABLE (MOD_0F01_REG_3) },
2608
    { "smswD",  { Sv } },
2609
    { Bad_Opcode },
2610
    { "lmsw",   { Ew } },
2611
    { MOD_TABLE (MOD_0F01_REG_7) },
2612
  },
2613
  /* REG_0F0D */
2614
  {
2615
    { "prefetch",       { Mb } },
2616
    { "prefetchw",      { Mb } },
2617
  },
2618
  /* REG_0F18 */
2619
  {
2620
    { MOD_TABLE (MOD_0F18_REG_0) },
2621
    { MOD_TABLE (MOD_0F18_REG_1) },
2622
    { MOD_TABLE (MOD_0F18_REG_2) },
2623
    { MOD_TABLE (MOD_0F18_REG_3) },
2624
  },
2625
  /* REG_0F71 */
2626
  {
2627
    { Bad_Opcode },
2628
    { Bad_Opcode },
2629
    { MOD_TABLE (MOD_0F71_REG_2) },
2630
    { Bad_Opcode },
2631
    { MOD_TABLE (MOD_0F71_REG_4) },
2632
    { Bad_Opcode },
2633
    { MOD_TABLE (MOD_0F71_REG_6) },
2634
  },
2635
  /* REG_0F72 */
2636
  {
2637
    { Bad_Opcode },
2638
    { Bad_Opcode },
2639
    { MOD_TABLE (MOD_0F72_REG_2) },
2640
    { Bad_Opcode },
2641
    { MOD_TABLE (MOD_0F72_REG_4) },
2642
    { Bad_Opcode },
2643
    { MOD_TABLE (MOD_0F72_REG_6) },
2644
  },
2645
  /* REG_0F73 */
2646
  {
2647
    { Bad_Opcode },
2648
    { Bad_Opcode },
2649
    { MOD_TABLE (MOD_0F73_REG_2) },
2650
    { MOD_TABLE (MOD_0F73_REG_3) },
2651
    { Bad_Opcode },
2652
    { Bad_Opcode },
2653
    { MOD_TABLE (MOD_0F73_REG_6) },
2654
    { MOD_TABLE (MOD_0F73_REG_7) },
2655
  },
2656
  /* REG_0FA6 */
2657
  {
2658
    { "montmul",        { { OP_0f07, 0 } } },
2659
    { "xsha1",          { { OP_0f07, 0 } } },
2660
    { "xsha256",        { { OP_0f07, 0 } } },
2661
  },
2662
  /* REG_0FA7 */
2663
  {
2664
    { "xstore-rng",     { { OP_0f07, 0 } } },
2665
    { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2666
    { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2667
    { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2668
    { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2669
    { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2670
  },
2671
  /* REG_0FAE */
2672
  {
2673
    { MOD_TABLE (MOD_0FAE_REG_0) },
2674
    { MOD_TABLE (MOD_0FAE_REG_1) },
2675
    { MOD_TABLE (MOD_0FAE_REG_2) },
2676
    { MOD_TABLE (MOD_0FAE_REG_3) },
2677
    { MOD_TABLE (MOD_0FAE_REG_4) },
2678
    { MOD_TABLE (MOD_0FAE_REG_5) },
2679
    { MOD_TABLE (MOD_0FAE_REG_6) },
2680
    { MOD_TABLE (MOD_0FAE_REG_7) },
2681
  },
2682
  /* REG_0FBA */
2683
  {
2684
    { Bad_Opcode },
2685
    { Bad_Opcode },
2686
    { Bad_Opcode },
2687
    { Bad_Opcode },
2688
    { "btQ",    { Ev, Ib } },
2689
    { "btsQ",   { Ev, Ib } },
2690
    { "btrQ",   { Ev, Ib } },
2691
    { "btcQ",   { Ev, Ib } },
2692
  },
2693
  /* REG_0FC7 */
2694
  {
2695
    { Bad_Opcode },
2696
    { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2697
    { Bad_Opcode },
2698
    { Bad_Opcode },
2699
    { Bad_Opcode },
2700
    { Bad_Opcode },
2701
    { MOD_TABLE (MOD_0FC7_REG_6) },
2702
    { MOD_TABLE (MOD_0FC7_REG_7) },
2703
  },
2704
  /* REG_VEX_0F71 */
2705
  {
2706
    { Bad_Opcode },
2707
    { Bad_Opcode },
2708
    { MOD_TABLE (MOD_VEX_0F71_REG_2) },
2709
    { Bad_Opcode },
2710
    { MOD_TABLE (MOD_VEX_0F71_REG_4) },
2711
    { Bad_Opcode },
2712
    { MOD_TABLE (MOD_VEX_0F71_REG_6) },
2713
  },
2714
  /* REG_VEX_0F72 */
2715
  {
2716
    { Bad_Opcode },
2717
    { Bad_Opcode },
2718
    { MOD_TABLE (MOD_VEX_0F72_REG_2) },
2719
    { Bad_Opcode },
2720
    { MOD_TABLE (MOD_VEX_0F72_REG_4) },
2721
    { Bad_Opcode },
2722
    { MOD_TABLE (MOD_VEX_0F72_REG_6) },
2723
  },
2724
  /* REG_VEX_0F73 */
2725
  {
2726
    { Bad_Opcode },
2727
    { Bad_Opcode },
2728
    { MOD_TABLE (MOD_VEX_0F73_REG_2) },
2729
    { MOD_TABLE (MOD_VEX_0F73_REG_3) },
2730
    { Bad_Opcode },
2731
    { Bad_Opcode },
2732
    { MOD_TABLE (MOD_VEX_0F73_REG_6) },
2733
    { MOD_TABLE (MOD_VEX_0F73_REG_7) },
2734
  },
2735
  /* REG_VEX_0FAE */
2736
  {
2737
    { Bad_Opcode },
2738
    { Bad_Opcode },
2739
    { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2740
    { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2741
  },
2742
  /* REG_VEX_0F38F3 */
2743
  {
2744
    { Bad_Opcode },
2745
    { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
2746
    { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
2747
    { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
2748
  },
2749
  /* REG_XOP_LWPCB */
2750
  {
2751
    { "llwpcb", { { OP_LWPCB_E, 0 } } },
2752
    { "slwpcb", { { OP_LWPCB_E, 0 } } },
2753
  },
2754
  /* REG_XOP_LWP */
2755
  {
2756
    { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
2757
    { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
2758
  },
2759
  /* REG_XOP_TBM_01 */
2760
  {
2761
    { Bad_Opcode },
2762
    { "blcfill",        { { OP_LWP_E, 0 }, Ev } },
2763
    { "blsfill",        { { OP_LWP_E, 0 }, Ev } },
2764
    { "blcs",   { { OP_LWP_E, 0 }, Ev } },
2765
    { "tzmsk",  { { OP_LWP_E, 0 }, Ev } },
2766
    { "blcic",  { { OP_LWP_E, 0 }, Ev } },
2767
    { "blsic",  { { OP_LWP_E, 0 }, Ev } },
2768
    { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
2769
  },
2770
  /* REG_XOP_TBM_02 */
2771
  {
2772
    { Bad_Opcode },
2773
    { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
2774
    { Bad_Opcode },
2775
    { Bad_Opcode },
2776
    { Bad_Opcode },
2777
    { Bad_Opcode },
2778
    { "blci",   { { OP_LWP_E, 0 }, Ev } },
2779
  },
2780
};
2781
 
2782
static const struct dis386 prefix_table[][4] = {
2783
  /* PREFIX_90 */
2784
  {
2785
    { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2786
    { "pause", { XX } },
2787
    { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2788
  },
2789
 
2790
  /* PREFIX_0F10 */
2791
  {
2792
    { "movups", { XM, EXx } },
2793
    { "movss",  { XM, EXd } },
2794
    { "movupd", { XM, EXx } },
2795
    { "movsd",  { XM, EXq } },
2796
  },
2797
 
2798
  /* PREFIX_0F11 */
2799
  {
2800
    { "movups", { EXxS, XM } },
2801
    { "movss",  { EXdS, XM } },
2802
    { "movupd", { EXxS, XM } },
2803
    { "movsd",  { EXqS, XM } },
2804
  },
2805
 
2806
  /* PREFIX_0F12 */
2807
  {
2808
    { MOD_TABLE (MOD_0F12_PREFIX_0) },
2809
    { "movsldup", { XM, EXx } },
2810
    { "movlpd", { XM, EXq } },
2811
    { "movddup", { XM, EXq } },
2812
  },
2813
 
2814
  /* PREFIX_0F16 */
2815
  {
2816
    { MOD_TABLE (MOD_0F16_PREFIX_0) },
2817
    { "movshdup", { XM, EXx } },
2818
    { "movhpd", { XM, EXq } },
2819
  },
2820
 
2821
  /* PREFIX_0F2A */
2822
  {
2823
    { "cvtpi2ps", { XM, EMCq } },
2824
    { "cvtsi2ss%LQ", { XM, Ev } },
2825
    { "cvtpi2pd", { XM, EMCq } },
2826
    { "cvtsi2sd%LQ", { XM, Ev } },
2827
  },
2828
 
2829
  /* PREFIX_0F2B */
2830
  {
2831
    { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2832
    { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2833
    { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2834
    { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2835
  },
2836
 
2837
  /* PREFIX_0F2C */
2838
  {
2839
    { "cvttps2pi", { MXC, EXq } },
2840
    { "cvttss2siY", { Gv, EXd } },
2841
    { "cvttpd2pi", { MXC, EXx } },
2842
    { "cvttsd2siY", { Gv, EXq } },
2843
  },
2844
 
2845
  /* PREFIX_0F2D */
2846
  {
2847
    { "cvtps2pi", { MXC, EXq } },
2848
    { "cvtss2siY", { Gv, EXd } },
2849
    { "cvtpd2pi", { MXC, EXx } },
2850
    { "cvtsd2siY", { Gv, EXq } },
2851
  },
2852
 
2853
  /* PREFIX_0F2E */
2854
  {
2855
    { "ucomiss",{ XM, EXd } },
2856
    { Bad_Opcode },
2857
    { "ucomisd",{ XM, EXq } },
2858
  },
2859
 
2860
  /* PREFIX_0F2F */
2861
  {
2862
    { "comiss", { XM, EXd } },
2863
    { Bad_Opcode },
2864
    { "comisd", { XM, EXq } },
2865
  },
2866
 
2867
  /* PREFIX_0F51 */
2868
  {
2869
    { "sqrtps", { XM, EXx } },
2870
    { "sqrtss", { XM, EXd } },
2871
    { "sqrtpd", { XM, EXx } },
2872
    { "sqrtsd", { XM, EXq } },
2873
  },
2874
 
2875
  /* PREFIX_0F52 */
2876
  {
2877
    { "rsqrtps",{ XM, EXx } },
2878
    { "rsqrtss",{ XM, EXd } },
2879
  },
2880
 
2881
  /* PREFIX_0F53 */
2882
  {
2883
    { "rcpps",  { XM, EXx } },
2884
    { "rcpss",  { XM, EXd } },
2885
  },
2886
 
2887
  /* PREFIX_0F58 */
2888
  {
2889
    { "addps", { XM, EXx } },
2890
    { "addss", { XM, EXd } },
2891
    { "addpd", { XM, EXx } },
2892
    { "addsd", { XM, EXq } },
2893
  },
2894
 
2895
  /* PREFIX_0F59 */
2896
  {
2897
    { "mulps",  { XM, EXx } },
2898
    { "mulss",  { XM, EXd } },
2899
    { "mulpd",  { XM, EXx } },
2900
    { "mulsd",  { XM, EXq } },
2901
  },
2902
 
2903
  /* PREFIX_0F5A */
2904
  {
2905
    { "cvtps2pd", { XM, EXq } },
2906
    { "cvtss2sd", { XM, EXd } },
2907
    { "cvtpd2ps", { XM, EXx } },
2908
    { "cvtsd2ss", { XM, EXq } },
2909
  },
2910
 
2911
  /* PREFIX_0F5B */
2912
  {
2913
    { "cvtdq2ps", { XM, EXx } },
2914
    { "cvttps2dq", { XM, EXx } },
2915
    { "cvtps2dq", { XM, EXx } },
2916
  },
2917
 
2918
  /* PREFIX_0F5C */
2919
  {
2920
    { "subps",  { XM, EXx } },
2921
    { "subss",  { XM, EXd } },
2922
    { "subpd",  { XM, EXx } },
2923
    { "subsd",  { XM, EXq } },
2924
  },
2925
 
2926
  /* PREFIX_0F5D */
2927
  {
2928
    { "minps",  { XM, EXx } },
2929
    { "minss",  { XM, EXd } },
2930
    { "minpd",  { XM, EXx } },
2931
    { "minsd",  { XM, EXq } },
2932
  },
2933
 
2934
  /* PREFIX_0F5E */
2935
  {
2936
    { "divps",  { XM, EXx } },
2937
    { "divss",  { XM, EXd } },
2938
    { "divpd",  { XM, EXx } },
2939
    { "divsd",  { XM, EXq } },
2940
  },
2941
 
2942
  /* PREFIX_0F5F */
2943
  {
2944
    { "maxps",  { XM, EXx } },
2945
    { "maxss",  { XM, EXd } },
2946
    { "maxpd",  { XM, EXx } },
2947
    { "maxsd",  { XM, EXq } },
2948
  },
2949
 
2950
  /* PREFIX_0F60 */
2951
  {
2952
    { "punpcklbw",{ MX, EMd } },
2953
    { Bad_Opcode },
2954
    { "punpcklbw",{ MX, EMx } },
2955
  },
2956
 
2957
  /* PREFIX_0F61 */
2958
  {
2959
    { "punpcklwd",{ MX, EMd } },
2960
    { Bad_Opcode },
2961
    { "punpcklwd"