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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_top.v] - Blame information for rev 868

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1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200 Top Level                                            ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6 258 julius
////  http://opencores.org/project,or1k                           ////
7 10 unneback
////                                                              ////
8
////  Description                                                 ////
9
////  OR1200 Top Level                                            ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// CVS Revision History
45
//
46 142 marcus.erl
// $Log: or1200_top.v,v $
47
// Revision 2.0  2010/06/30 11:00:00  ORSoC
48
// Major update: 
49
// Structure reordered. 
50
//
51 10 unneback
 
52
// synopsys translate_off
53
`include "timescale.v"
54
// synopsys translate_on
55
`include "or1200_defines.v"
56
 
57
module or1200_top(
58
        // System
59
        clk_i, rst_i, pic_ints_i, clmode_i,
60
 
61
        // Instruction WISHBONE INTERFACE
62
        iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,
63
        iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,
64
`ifdef OR1200_WB_CAB
65
        iwb_cab_o,
66
`endif
67
`ifdef OR1200_WB_B3
68
        iwb_cti_o, iwb_bte_o,
69
`endif
70
        // Data WISHBONE INTERFACE
71
        dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
72
        dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,
73
`ifdef OR1200_WB_CAB
74
        dwb_cab_o,
75
`endif
76
`ifdef OR1200_WB_B3
77
        dwb_cti_o, dwb_bte_o,
78
`endif
79
 
80
        // External Debug Interface
81
        dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
82
        dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o,
83
 
84
`ifdef OR1200_BIST
85
        // RAM BIST
86
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
87
`endif
88
        // Power Management
89
        pm_cpustall_i,
90
        pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o,
91
        pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o
92
 
93 142 marcus.erl
,sig_tick
94
 
95 10 unneback
);
96
 
97
parameter dw = `OR1200_OPERAND_WIDTH;
98
parameter aw = `OR1200_OPERAND_WIDTH;
99
parameter ppic_ints = `OR1200_PIC_INTS;
100 679 olof
parameter boot_adr = `OR1200_BOOT_ADR;
101 10 unneback
 
102
//
103
// I/O
104
//
105
 
106
//
107
// System
108
//
109
input                   clk_i;
110
input                   rst_i;
111
input   [1:0]            clmode_i;       // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
112
input   [ppic_ints-1:0]  pic_ints_i;
113
 
114
//
115
// Instruction WISHBONE interface
116
//
117
input                   iwb_clk_i;      // clock input
118
input                   iwb_rst_i;      // reset input
119
input                   iwb_ack_i;      // normal termination
120
input                   iwb_err_i;      // termination w/ error
121
input                   iwb_rty_i;      // termination w/ retry
122
input   [dw-1:0] iwb_dat_i;      // input data bus
123
output                  iwb_cyc_o;      // cycle valid output
124
output  [aw-1:0] iwb_adr_o;      // address bus outputs
125
output                  iwb_stb_o;      // strobe output
126
output                  iwb_we_o;       // indicates write transfer
127
output  [3:0]            iwb_sel_o;      // byte select outputs
128
output  [dw-1:0] iwb_dat_o;      // output data bus
129
`ifdef OR1200_WB_CAB
130
output                  iwb_cab_o;      // indicates consecutive address burst
131
`endif
132
`ifdef OR1200_WB_B3
133
output  [2:0]            iwb_cti_o;      // cycle type identifier
134
output  [1:0]            iwb_bte_o;      // burst type extension
135
`endif
136
 
137
//
138
// Data WISHBONE interface
139
//
140
input                   dwb_clk_i;      // clock input
141
input                   dwb_rst_i;      // reset input
142
input                   dwb_ack_i;      // normal termination
143
input                   dwb_err_i;      // termination w/ error
144
input                   dwb_rty_i;      // termination w/ retry
145
input   [dw-1:0] dwb_dat_i;      // input data bus
146
output                  dwb_cyc_o;      // cycle valid output
147
output  [aw-1:0] dwb_adr_o;      // address bus outputs
148
output                  dwb_stb_o;      // strobe output
149
output                  dwb_we_o;       // indicates write transfer
150
output  [3:0]            dwb_sel_o;      // byte select outputs
151
output  [dw-1:0] dwb_dat_o;      // output data bus
152
`ifdef OR1200_WB_CAB
153
output                  dwb_cab_o;      // indicates consecutive address burst
154
`endif
155
`ifdef OR1200_WB_B3
156
output  [2:0]            dwb_cti_o;      // cycle type identifier
157
output  [1:0]            dwb_bte_o;      // burst type extension
158
`endif
159
 
160
//
161
// External Debug Interface
162
//
163
input                   dbg_stall_i;    // External Stall Input
164
input                   dbg_ewt_i;      // External Watchpoint Trigger Input
165
output  [3:0]            dbg_lss_o;      // External Load/Store Unit Status
166
output  [1:0]            dbg_is_o;       // External Insn Fetch Status
167
output  [10:0]           dbg_wp_o;       // Watchpoints Outputs
168
output                  dbg_bp_o;       // Breakpoint Output
169
input                   dbg_stb_i;      // External Address/Data Strobe
170
input                   dbg_we_i;       // External Write Enable
171
input   [aw-1:0] dbg_adr_i;      // External Address Input
172
input   [dw-1:0] dbg_dat_i;      // External Data Input
173
output  [dw-1:0] dbg_dat_o;      // External Data Output
174
output                  dbg_ack_o;      // External Data Acknowledge (not WB compatible)
175
 
176
`ifdef OR1200_BIST
177
//
178
// RAM BIST
179
//
180
input mbist_si_i;
181
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
182
output mbist_so_o;
183
`endif
184
 
185
//
186
// Power Management
187
//
188
input                   pm_cpustall_i;
189
output  [3:0]            pm_clksd_o;
190
output                  pm_dc_gate_o;
191
output                  pm_ic_gate_o;
192
output                  pm_dmmu_gate_o;
193
output                  pm_immu_gate_o;
194
output                  pm_tt_gate_o;
195
output                  pm_cpu_gate_o;
196
output                  pm_wakeup_o;
197
output                  pm_lvolt_o;
198
 
199
 
200
//
201
// Internal wires and regs
202
//
203
 
204
//
205
// DC to SB
206
//
207
wire    [dw-1:0] dcsb_dat_dc;
208
wire    [aw-1:0] dcsb_adr_dc;
209
wire                    dcsb_cyc_dc;
210
wire                    dcsb_stb_dc;
211
wire                    dcsb_we_dc;
212
wire    [3:0]            dcsb_sel_dc;
213
wire                    dcsb_cab_dc;
214
wire    [dw-1:0] dcsb_dat_sb;
215
wire                    dcsb_ack_sb;
216
wire                    dcsb_err_sb;
217
 
218
//
219
// SB to BIU
220
//
221
wire    [dw-1:0] sbbiu_dat_sb;
222
wire    [aw-1:0] sbbiu_adr_sb;
223
wire                    sbbiu_cyc_sb;
224
wire                    sbbiu_stb_sb;
225
wire                    sbbiu_we_sb;
226
wire    [3:0]            sbbiu_sel_sb;
227
wire                    sbbiu_cab_sb;
228
wire    [dw-1:0] sbbiu_dat_biu;
229
wire                    sbbiu_ack_biu;
230
wire                    sbbiu_err_biu;
231
 
232
//
233
// IC to BIU
234
//
235
wire    [dw-1:0] icbiu_dat_ic;
236
wire    [aw-1:0] icbiu_adr_ic;
237 142 marcus.erl
wire    [aw-1:0] icbiu_adr_ic_word;
238 10 unneback
wire                    icbiu_cyc_ic;
239
wire                    icbiu_stb_ic;
240
wire                    icbiu_we_ic;
241
wire    [3:0]            icbiu_sel_ic;
242
wire    [3:0]            icbiu_tag_ic;
243
wire                    icbiu_cab_ic;
244
wire    [dw-1:0] icbiu_dat_biu;
245
wire                    icbiu_ack_biu;
246
wire                    icbiu_err_biu;
247
wire    [3:0]            icbiu_tag_biu;
248
 
249
//
250 142 marcus.erl
// SR Interface (this signal can be connected to the input pin)
251
//
252
wire                    boot_adr_sel = `OR1200_SR_EPH_DEF;
253
 
254
//
255 10 unneback
// CPU's SPR access to various RISC units (shared wires)
256
//
257
wire                    supv;
258
wire    [aw-1:0] spr_addr;
259
wire    [dw-1:0] spr_dat_cpu;
260
wire    [31:0]           spr_cs;
261
wire                    spr_we;
262 364 julius
wire                    mtspr_dc_done;
263
 
264 10 unneback
//
265 142 marcus.erl
// SB
266
//
267
wire                    sb_en;
268
 
269
//
270 10 unneback
// DMMU and CPU
271
//
272
wire                    dmmu_en;
273
wire    [31:0]           spr_dat_dmmu;
274
 
275
//
276
// DMMU and QMEM
277
//
278
wire                    qmemdmmu_err_qmem;
279
wire    [3:0]            qmemdmmu_tag_qmem;
280
wire    [aw-1:0] qmemdmmu_adr_dmmu;
281
wire                    qmemdmmu_cycstb_dmmu;
282
wire                    qmemdmmu_ci_dmmu;
283
 
284
//
285
// CPU and data memory subsystem
286
//
287
wire                    dc_en;
288
wire    [31:0]           dcpu_adr_cpu;
289
wire                    dcpu_cycstb_cpu;
290
wire                    dcpu_we_cpu;
291
wire    [3:0]            dcpu_sel_cpu;
292
wire    [3:0]            dcpu_tag_cpu;
293
wire    [31:0]           dcpu_dat_cpu;
294
wire    [31:0]           dcpu_dat_qmem;
295
wire                    dcpu_ack_qmem;
296
wire                    dcpu_rty_qmem;
297
wire                    dcpu_err_dmmu;
298
wire    [3:0]            dcpu_tag_dmmu;
299 258 julius
wire                    dc_no_writethrough;
300
 
301 10 unneback
//
302
// IMMU and CPU
303
//
304
wire                    immu_en;
305
wire    [31:0]           spr_dat_immu;
306
 
307
//
308
// CPU and insn memory subsystem
309
//
310
wire                    ic_en;
311
wire    [31:0]           icpu_adr_cpu;
312
wire                    icpu_cycstb_cpu;
313
wire    [3:0]            icpu_sel_cpu;
314
wire    [3:0]            icpu_tag_cpu;
315
wire    [31:0]           icpu_dat_qmem;
316
wire                    icpu_ack_qmem;
317
wire    [31:0]           icpu_adr_immu;
318
wire                    icpu_err_immu;
319
wire    [3:0]            icpu_tag_immu;
320
wire                    icpu_rty_immu;
321
 
322
//
323
// IMMU and QMEM
324
//
325
wire    [aw-1:0] qmemimmu_adr_immu;
326
wire                    qmemimmu_rty_qmem;
327
wire                    qmemimmu_err_qmem;
328
wire    [3:0]            qmemimmu_tag_qmem;
329
wire                    qmemimmu_cycstb_immu;
330
wire                    qmemimmu_ci_immu;
331
 
332
//
333
// QMEM and IC
334
//
335
wire    [aw-1:0] icqmem_adr_qmem;
336
wire                    icqmem_rty_ic;
337
wire                    icqmem_err_ic;
338
wire    [3:0]            icqmem_tag_ic;
339
wire                    icqmem_cycstb_qmem;
340
wire                    icqmem_ci_qmem;
341
wire    [31:0]           icqmem_dat_ic;
342
wire                    icqmem_ack_ic;
343
 
344
//
345
// QMEM and DC
346
//
347
wire    [aw-1:0] dcqmem_adr_qmem;
348
wire                    dcqmem_rty_dc;
349
wire                    dcqmem_err_dc;
350
wire    [3:0]            dcqmem_tag_dc;
351
wire                    dcqmem_cycstb_qmem;
352
wire                    dcqmem_ci_qmem;
353
wire    [31:0]           dcqmem_dat_dc;
354
wire    [31:0]           dcqmem_dat_qmem;
355
wire                    dcqmem_we_qmem;
356
wire    [3:0]            dcqmem_sel_qmem;
357
wire                    dcqmem_ack_dc;
358
 
359
//
360
// Connection between CPU and PIC
361
//
362
wire    [dw-1:0] spr_dat_pic;
363
wire                    pic_wakeup;
364
wire                    sig_int;
365
 
366
//
367
// Connection between CPU and PM
368
//
369
wire    [dw-1:0] spr_dat_pm;
370
 
371
//
372
// CPU and TT
373
//
374
wire    [dw-1:0] spr_dat_tt;
375 142 marcus.erl
output wire                     sig_tick; // jb
376 10 unneback
 
377
//
378
// Debug port and caches/MMUs
379
//
380
wire    [dw-1:0] spr_dat_du;
381
wire                    du_stall;
382
wire    [dw-1:0] du_addr;
383
wire    [dw-1:0] du_dat_du;
384
wire                    du_read;
385
wire                    du_write;
386 185 julius
wire    [13:0]           du_except_trig;
387
wire    [13:0]           du_except_stop;
388 10 unneback
wire    [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;
389 142 marcus.erl
wire    [24:0]           du_dmr1;
390 10 unneback
wire    [dw-1:0] du_dat_cpu;
391 142 marcus.erl
wire    [dw-1:0] du_lsu_store_dat;
392
wire    [dw-1:0] du_lsu_load_dat;
393 10 unneback
wire                    du_hwbkpt;
394 142 marcus.erl
wire                    du_hwbkpt_ls_r = 1'b0;
395 868 olof
wire                    du_flush_pipe;
396 142 marcus.erl
wire                    flushpipe;
397 10 unneback
wire                    ex_freeze;
398 142 marcus.erl
wire                    wb_freeze;
399
wire                    id_void;
400
wire                    ex_void;
401
wire    [31:0]           id_insn;
402 10 unneback
wire    [31:0]           ex_insn;
403 142 marcus.erl
wire    [31:0]           wb_insn;
404 10 unneback
wire    [31:0]           id_pc;
405 142 marcus.erl
wire    [31:0]           ex_pc;
406
wire    [31:0]           wb_pc;
407 10 unneback
wire    [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
408
wire    [31:0]           spr_dat_npc;
409
wire    [31:0]           rf_dataw;
410 142 marcus.erl
wire                    abort_ex;
411
wire                    abort_mvspr;
412 10 unneback
 
413
`ifdef OR1200_BIST
414
//
415
// RAM BIST
416
//
417
wire                    mbist_immu_so;
418
wire                    mbist_ic_so;
419
wire                    mbist_dmmu_so;
420
wire                    mbist_dc_so;
421 142 marcus.erl
wire                    mbist_qmem_so;
422 10 unneback
wire                    mbist_immu_si = mbist_si_i;
423
wire                    mbist_ic_si = mbist_immu_so;
424
wire                    mbist_qmem_si = mbist_ic_so;
425
wire                    mbist_dmmu_si = mbist_qmem_so;
426
wire                    mbist_dc_si = mbist_dmmu_so;
427
assign                  mbist_so_o = mbist_dc_so;
428
`endif
429
 
430
wire  [3:0] icqmem_sel_qmem;
431
wire  [3:0] icqmem_tag_qmem;
432
wire  [3:0] dcqmem_tag_qmem;
433
 
434
//
435
// Instantiation of Instruction WISHBONE BIU
436
//
437 481 julius
or1200_wb_biu
438
  #(.bl((1 << (`OR1200_ICLS-2))))
439
  iwb_biu(
440 10 unneback
        // RISC clk, rst and clock control
441
        .clk(clk_i),
442
        .rst(rst_i),
443
        .clmode(clmode_i),
444
 
445
        // WISHBONE interface
446
        .wb_clk_i(iwb_clk_i),
447
        .wb_rst_i(iwb_rst_i),
448
        .wb_ack_i(iwb_ack_i),
449
        .wb_err_i(iwb_err_i),
450
        .wb_rty_i(iwb_rty_i),
451
        .wb_dat_i(iwb_dat_i),
452
        .wb_cyc_o(iwb_cyc_o),
453
        .wb_adr_o(iwb_adr_o),
454
        .wb_stb_o(iwb_stb_o),
455
        .wb_we_o(iwb_we_o),
456
        .wb_sel_o(iwb_sel_o),
457
        .wb_dat_o(iwb_dat_o),
458
`ifdef OR1200_WB_CAB
459
        .wb_cab_o(iwb_cab_o),
460
`endif
461
`ifdef OR1200_WB_B3
462
        .wb_cti_o(iwb_cti_o),
463
        .wb_bte_o(iwb_bte_o),
464
`endif
465
 
466
        // Internal RISC bus
467
        .biu_dat_i(icbiu_dat_ic),
468 142 marcus.erl
        .biu_adr_i(icbiu_adr_ic_word),
469 10 unneback
        .biu_cyc_i(icbiu_cyc_ic),
470
        .biu_stb_i(icbiu_stb_ic),
471
        .biu_we_i(icbiu_we_ic),
472
        .biu_sel_i(icbiu_sel_ic),
473
        .biu_cab_i(icbiu_cab_ic),
474
        .biu_dat_o(icbiu_dat_biu),
475
        .biu_ack_o(icbiu_ack_biu),
476
        .biu_err_o(icbiu_err_biu)
477
);
478 142 marcus.erl
assign icbiu_adr_ic_word = {icbiu_adr_ic[31:2], 2'h0};
479 10 unneback
 
480
//
481
// Instantiation of Data WISHBONE BIU
482
//
483 481 julius
or1200_wb_biu
484
  #(.bl((1 << (`OR1200_DCLS-2))))
485
  dwb_biu(
486 10 unneback
        // RISC clk, rst and clock control
487
        .clk(clk_i),
488
        .rst(rst_i),
489
        .clmode(clmode_i),
490
 
491
        // WISHBONE interface
492
        .wb_clk_i(dwb_clk_i),
493
        .wb_rst_i(dwb_rst_i),
494
        .wb_ack_i(dwb_ack_i),
495
        .wb_err_i(dwb_err_i),
496
        .wb_rty_i(dwb_rty_i),
497
        .wb_dat_i(dwb_dat_i),
498
        .wb_cyc_o(dwb_cyc_o),
499
        .wb_adr_o(dwb_adr_o),
500
        .wb_stb_o(dwb_stb_o),
501
        .wb_we_o(dwb_we_o),
502
        .wb_sel_o(dwb_sel_o),
503
        .wb_dat_o(dwb_dat_o),
504
`ifdef OR1200_WB_CAB
505
        .wb_cab_o(dwb_cab_o),
506
`endif
507
`ifdef OR1200_WB_B3
508
        .wb_cti_o(dwb_cti_o),
509
        .wb_bte_o(dwb_bte_o),
510
`endif
511
 
512
        // Internal RISC bus
513
        .biu_dat_i(sbbiu_dat_sb),
514
        .biu_adr_i(sbbiu_adr_sb),
515
        .biu_cyc_i(sbbiu_cyc_sb),
516
        .biu_stb_i(sbbiu_stb_sb),
517
        .biu_we_i(sbbiu_we_sb),
518
        .biu_sel_i(sbbiu_sel_sb),
519
        .biu_cab_i(sbbiu_cab_sb),
520
        .biu_dat_o(sbbiu_dat_biu),
521
        .biu_ack_o(sbbiu_ack_biu),
522
        .biu_err_o(sbbiu_err_biu)
523
);
524
 
525
//
526
// Instantiation of IMMU
527
//
528 679 olof
or1200_immu_top
529
#(.boot_adr(boot_adr))
530
or1200_immu_top(
531 10 unneback
        // Rst and clk
532
        .clk(clk_i),
533
        .rst(rst_i),
534
 
535
`ifdef OR1200_BIST
536
        // RAM BIST
537
        .mbist_si_i(mbist_immu_si),
538
        .mbist_so_o(mbist_immu_so),
539
        .mbist_ctrl_i(mbist_ctrl_i),
540
`endif
541
 
542
        // CPU and IMMU
543
        .ic_en(ic_en),
544
        .immu_en(immu_en),
545
        .supv(supv),
546
        .icpu_adr_i(icpu_adr_cpu),
547
        .icpu_cycstb_i(icpu_cycstb_cpu),
548
        .icpu_adr_o(icpu_adr_immu),
549
        .icpu_tag_o(icpu_tag_immu),
550
        .icpu_rty_o(icpu_rty_immu),
551
        .icpu_err_o(icpu_err_immu),
552
 
553 142 marcus.erl
        // SR Interface
554
        .boot_adr_sel_i(boot_adr_sel),
555
 
556 10 unneback
        // SPR access
557
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_IMMU]),
558
        .spr_write(spr_we),
559
        .spr_addr(spr_addr),
560
        .spr_dat_i(spr_dat_cpu),
561
        .spr_dat_o(spr_dat_immu),
562
 
563
        // QMEM and IMMU
564
        .qmemimmu_rty_i(qmemimmu_rty_qmem),
565
        .qmemimmu_err_i(qmemimmu_err_qmem),
566
        .qmemimmu_tag_i(qmemimmu_tag_qmem),
567
        .qmemimmu_adr_o(qmemimmu_adr_immu),
568
        .qmemimmu_cycstb_o(qmemimmu_cycstb_immu),
569
        .qmemimmu_ci_o(qmemimmu_ci_immu)
570
);
571
 
572
//
573
// Instantiation of Instruction Cache
574
//
575
or1200_ic_top or1200_ic_top(
576
        .clk(clk_i),
577
        .rst(rst_i),
578
 
579
`ifdef OR1200_BIST
580
        // RAM BIST
581
        .mbist_si_i(mbist_ic_si),
582
        .mbist_so_o(mbist_ic_so),
583
        .mbist_ctrl_i(mbist_ctrl_i),
584
`endif
585
 
586
        // IC and QMEM
587
        .ic_en(ic_en),
588
        .icqmem_adr_i(icqmem_adr_qmem),
589
        .icqmem_cycstb_i(icqmem_cycstb_qmem),
590
        .icqmem_ci_i(icqmem_ci_qmem),
591
        .icqmem_sel_i(icqmem_sel_qmem),
592
        .icqmem_tag_i(icqmem_tag_qmem),
593
        .icqmem_dat_o(icqmem_dat_ic),
594
        .icqmem_ack_o(icqmem_ack_ic),
595
        .icqmem_rty_o(icqmem_rty_ic),
596
        .icqmem_err_o(icqmem_err_ic),
597
        .icqmem_tag_o(icqmem_tag_ic),
598
 
599
        // SPR access
600
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_IC]),
601
        .spr_write(spr_we),
602
        .spr_dat_i(spr_dat_cpu),
603
 
604
        // IC and BIU
605
        .icbiu_dat_o(icbiu_dat_ic),
606
        .icbiu_adr_o(icbiu_adr_ic),
607
        .icbiu_cyc_o(icbiu_cyc_ic),
608
        .icbiu_stb_o(icbiu_stb_ic),
609
        .icbiu_we_o(icbiu_we_ic),
610
        .icbiu_sel_o(icbiu_sel_ic),
611
        .icbiu_cab_o(icbiu_cab_ic),
612
        .icbiu_dat_i(icbiu_dat_biu),
613
        .icbiu_ack_i(icbiu_ack_biu),
614
        .icbiu_err_i(icbiu_err_biu)
615
);
616
 
617
//
618
// Instantiation of Instruction Cache
619
//
620 813 olof
or1200_cpu
621
#(.boot_adr(boot_adr))
622
or1200_cpu(
623 10 unneback
        .clk(clk_i),
624
        .rst(rst_i),
625
 
626
        // Connection QMEM and IFETCHER inside CPU
627
        .ic_en(ic_en),
628
        .icpu_adr_o(icpu_adr_cpu),
629
        .icpu_cycstb_o(icpu_cycstb_cpu),
630
        .icpu_sel_o(icpu_sel_cpu),
631
        .icpu_tag_o(icpu_tag_cpu),
632
        .icpu_dat_i(icpu_dat_qmem),
633
        .icpu_ack_i(icpu_ack_qmem),
634
        .icpu_rty_i(icpu_rty_immu),
635
        .icpu_adr_i(icpu_adr_immu),
636
        .icpu_err_i(icpu_err_immu),
637
        .icpu_tag_i(icpu_tag_immu),
638
 
639
        // Connection CPU to external Debug port
640 142 marcus.erl
        .id_void(id_void),
641
        .id_insn(id_insn),
642
        .ex_void(ex_void),
643
        .ex_insn(ex_insn),
644 10 unneback
        .ex_freeze(ex_freeze),
645 142 marcus.erl
        .wb_insn(wb_insn),
646
        .wb_freeze(wb_freeze),
647 10 unneback
        .id_pc(id_pc),
648 142 marcus.erl
        .ex_pc(ex_pc),
649
        .wb_pc(wb_pc),
650 10 unneback
        .branch_op(branch_op),
651 142 marcus.erl
        .rf_dataw(rf_dataw),
652
        .ex_flushpipe(flushpipe),
653 10 unneback
        .du_stall(du_stall),
654
        .du_addr(du_addr),
655
        .du_dat_du(du_dat_du),
656
        .du_read(du_read),
657
        .du_write(du_write),
658 142 marcus.erl
        .du_except_trig(du_except_trig),
659
        .du_except_stop(du_except_stop),
660 10 unneback
        .du_dsr(du_dsr),
661 142 marcus.erl
        .du_dmr1(du_dmr1),
662
        .du_hwbkpt(du_hwbkpt),
663
        .du_hwbkpt_ls_r(du_hwbkpt_ls_r),
664 10 unneback
        .du_dat_cpu(du_dat_cpu),
665 142 marcus.erl
        .du_lsu_store_dat(du_lsu_store_dat),
666
        .du_lsu_load_dat(du_lsu_load_dat),
667
        .abort_mvspr(abort_mvspr),
668
        .abort_ex(abort_ex),
669 859 olof
        .du_flush_pipe(du_flush_pipe),
670 10 unneback
 
671
        // Connection IMMU and CPU internally
672
        .immu_en(immu_en),
673
 
674
        // Connection QMEM and CPU
675
        .dc_en(dc_en),
676
        .dcpu_adr_o(dcpu_adr_cpu),
677
        .dcpu_cycstb_o(dcpu_cycstb_cpu),
678
        .dcpu_we_o(dcpu_we_cpu),
679
        .dcpu_sel_o(dcpu_sel_cpu),
680
        .dcpu_tag_o(dcpu_tag_cpu),
681
        .dcpu_dat_o(dcpu_dat_cpu),
682
        .dcpu_dat_i(dcpu_dat_qmem),
683
        .dcpu_ack_i(dcpu_ack_qmem),
684
        .dcpu_rty_i(dcpu_rty_qmem),
685
        .dcpu_err_i(dcpu_err_dmmu),
686
        .dcpu_tag_i(dcpu_tag_dmmu),
687 258 julius
        .dc_no_writethrough(dc_no_writethrough),
688 10 unneback
 
689
        // Connection DMMU and CPU internally
690
        .dmmu_en(dmmu_en),
691
 
692 142 marcus.erl
        // SR Interface
693
        .boot_adr_sel_i(boot_adr_sel),
694
 
695
        // SB Enable
696
        .sb_en(sb_en),
697
 
698 10 unneback
        // Connection PIC and CPU's EXCEPT
699
        .sig_int(sig_int),
700
        .sig_tick(sig_tick),
701
 
702
        // SPRs
703
        .supv(supv),
704
        .spr_addr(spr_addr),
705
        .spr_dat_cpu(spr_dat_cpu),
706
        .spr_dat_pic(spr_dat_pic),
707
        .spr_dat_tt(spr_dat_tt),
708
        .spr_dat_pm(spr_dat_pm),
709
        .spr_dat_dmmu(spr_dat_dmmu),
710
        .spr_dat_immu(spr_dat_immu),
711
        .spr_dat_du(spr_dat_du),
712
        .spr_dat_npc(spr_dat_npc),
713
        .spr_cs(spr_cs),
714 258 julius
        .spr_we(spr_we),
715
        .mtspr_dc_done(mtspr_dc_done)
716 10 unneback
);
717
 
718
//
719
// Instantiation of DMMU
720
//
721
or1200_dmmu_top or1200_dmmu_top(
722
        // Rst and clk
723
        .clk(clk_i),
724
        .rst(rst_i),
725
 
726
`ifdef OR1200_BIST
727
        // RAM BIST
728
        .mbist_si_i(mbist_dmmu_si),
729
        .mbist_so_o(mbist_dmmu_so),
730
        .mbist_ctrl_i(mbist_ctrl_i),
731
`endif
732
 
733
        // CPU i/f
734
        .dc_en(dc_en),
735
        .dmmu_en(dmmu_en),
736
        .supv(supv),
737
        .dcpu_adr_i(dcpu_adr_cpu),
738
        .dcpu_cycstb_i(dcpu_cycstb_cpu),
739
        .dcpu_we_i(dcpu_we_cpu),
740
        .dcpu_tag_o(dcpu_tag_dmmu),
741
        .dcpu_err_o(dcpu_err_dmmu),
742
 
743
        // SPR access
744
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_DMMU]),
745
        .spr_write(spr_we),
746
        .spr_addr(spr_addr),
747
        .spr_dat_i(spr_dat_cpu),
748
        .spr_dat_o(spr_dat_dmmu),
749
 
750
        // QMEM and DMMU
751
        .qmemdmmu_err_i(qmemdmmu_err_qmem),
752
        .qmemdmmu_tag_i(qmemdmmu_tag_qmem),
753
        .qmemdmmu_adr_o(qmemdmmu_adr_dmmu),
754
        .qmemdmmu_cycstb_o(qmemdmmu_cycstb_dmmu),
755
        .qmemdmmu_ci_o(qmemdmmu_ci_dmmu)
756
);
757
 
758
//
759
// Instantiation of Data Cache
760
//
761
or1200_dc_top or1200_dc_top(
762
        .clk(clk_i),
763
        .rst(rst_i),
764
 
765
`ifdef OR1200_BIST
766
        // RAM BIST
767
        .mbist_si_i(mbist_dc_si),
768
        .mbist_so_o(mbist_dc_so),
769
        .mbist_ctrl_i(mbist_ctrl_i),
770
`endif
771
 
772
        // DC and QMEM
773
        .dc_en(dc_en),
774
        .dcqmem_adr_i(dcqmem_adr_qmem),
775
        .dcqmem_cycstb_i(dcqmem_cycstb_qmem),
776
        .dcqmem_ci_i(dcqmem_ci_qmem),
777
        .dcqmem_we_i(dcqmem_we_qmem),
778
        .dcqmem_sel_i(dcqmem_sel_qmem),
779
        .dcqmem_tag_i(dcqmem_tag_qmem),
780
        .dcqmem_dat_i(dcqmem_dat_qmem),
781
        .dcqmem_dat_o(dcqmem_dat_dc),
782
        .dcqmem_ack_o(dcqmem_ack_dc),
783
        .dcqmem_rty_o(dcqmem_rty_dc),
784
        .dcqmem_err_o(dcqmem_err_dc),
785
        .dcqmem_tag_o(dcqmem_tag_dc),
786
 
787 258 julius
        .dc_no_writethrough(dc_no_writethrough),
788
 
789 10 unneback
        // SPR access
790
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_DC]),
791 258 julius
        .spr_addr(spr_addr),
792 10 unneback
        .spr_write(spr_we),
793
        .spr_dat_i(spr_dat_cpu),
794 258 julius
        .mtspr_dc_done(mtspr_dc_done),
795 10 unneback
 
796
        // DC and BIU
797
        .dcsb_dat_o(dcsb_dat_dc),
798
        .dcsb_adr_o(dcsb_adr_dc),
799
        .dcsb_cyc_o(dcsb_cyc_dc),
800
        .dcsb_stb_o(dcsb_stb_dc),
801
        .dcsb_we_o(dcsb_we_dc),
802
        .dcsb_sel_o(dcsb_sel_dc),
803
        .dcsb_cab_o(dcsb_cab_dc),
804
        .dcsb_dat_i(dcsb_dat_sb),
805
        .dcsb_ack_i(dcsb_ack_sb),
806
        .dcsb_err_i(dcsb_err_sb)
807
);
808
 
809
//
810
// Instantiation of embedded memory - qmem
811
//
812
or1200_qmem_top or1200_qmem_top(
813
        .clk(clk_i),
814
        .rst(rst_i),
815
 
816
`ifdef OR1200_BIST
817
        // RAM BIST
818
        .mbist_si_i(mbist_qmem_si),
819
        .mbist_so_o(mbist_qmem_so),
820
        .mbist_ctrl_i(mbist_ctrl_i),
821
`endif
822
 
823
        // QMEM and CPU/IMMU
824
        .qmemimmu_adr_i(qmemimmu_adr_immu),
825
        .qmemimmu_cycstb_i(qmemimmu_cycstb_immu),
826
        .qmemimmu_ci_i(qmemimmu_ci_immu),
827
        .qmemicpu_sel_i(icpu_sel_cpu),
828
        .qmemicpu_tag_i(icpu_tag_cpu),
829
        .qmemicpu_dat_o(icpu_dat_qmem),
830
        .qmemicpu_ack_o(icpu_ack_qmem),
831
        .qmemimmu_rty_o(qmemimmu_rty_qmem),
832
        .qmemimmu_err_o(qmemimmu_err_qmem),
833
        .qmemimmu_tag_o(qmemimmu_tag_qmem),
834
 
835
        // QMEM and IC
836
        .icqmem_adr_o(icqmem_adr_qmem),
837
        .icqmem_cycstb_o(icqmem_cycstb_qmem),
838
        .icqmem_ci_o(icqmem_ci_qmem),
839
        .icqmem_sel_o(icqmem_sel_qmem),
840
        .icqmem_tag_o(icqmem_tag_qmem),
841
        .icqmem_dat_i(icqmem_dat_ic),
842
        .icqmem_ack_i(icqmem_ack_ic),
843
        .icqmem_rty_i(icqmem_rty_ic),
844
        .icqmem_err_i(icqmem_err_ic),
845
        .icqmem_tag_i(icqmem_tag_ic),
846
 
847
        // QMEM and CPU/DMMU
848
        .qmemdmmu_adr_i(qmemdmmu_adr_dmmu),
849
        .qmemdmmu_cycstb_i(qmemdmmu_cycstb_dmmu),
850
        .qmemdmmu_ci_i(qmemdmmu_ci_dmmu),
851
        .qmemdcpu_we_i(dcpu_we_cpu),
852
        .qmemdcpu_sel_i(dcpu_sel_cpu),
853
        .qmemdcpu_tag_i(dcpu_tag_cpu),
854
        .qmemdcpu_dat_i(dcpu_dat_cpu),
855
        .qmemdcpu_dat_o(dcpu_dat_qmem),
856
        .qmemdcpu_ack_o(dcpu_ack_qmem),
857
        .qmemdcpu_rty_o(dcpu_rty_qmem),
858
        .qmemdmmu_err_o(qmemdmmu_err_qmem),
859
        .qmemdmmu_tag_o(qmemdmmu_tag_qmem),
860
 
861
        // QMEM and DC
862
        .dcqmem_adr_o(dcqmem_adr_qmem),
863
        .dcqmem_cycstb_o(dcqmem_cycstb_qmem),
864
        .dcqmem_ci_o(dcqmem_ci_qmem),
865
        .dcqmem_we_o(dcqmem_we_qmem),
866
        .dcqmem_sel_o(dcqmem_sel_qmem),
867
        .dcqmem_tag_o(dcqmem_tag_qmem),
868
        .dcqmem_dat_o(dcqmem_dat_qmem),
869
        .dcqmem_dat_i(dcqmem_dat_dc),
870
        .dcqmem_ack_i(dcqmem_ack_dc),
871
        .dcqmem_rty_i(dcqmem_rty_dc),
872
        .dcqmem_err_i(dcqmem_err_dc),
873
        .dcqmem_tag_i(dcqmem_tag_dc)
874
);
875
 
876
//
877
// Instantiation of Store Buffer
878
//
879
or1200_sb or1200_sb(
880
        // RISC clock, reset
881
        .clk(clk_i),
882
        .rst(rst_i),
883
 
884 142 marcus.erl
        // Internal RISC bus (SB)
885
        .sb_en(sb_en),
886
 
887 10 unneback
        // Internal RISC bus (DC<->SB)
888
        .dcsb_dat_i(dcsb_dat_dc),
889
        .dcsb_adr_i(dcsb_adr_dc),
890
        .dcsb_cyc_i(dcsb_cyc_dc),
891
        .dcsb_stb_i(dcsb_stb_dc),
892
        .dcsb_we_i(dcsb_we_dc),
893
        .dcsb_sel_i(dcsb_sel_dc),
894
        .dcsb_cab_i(dcsb_cab_dc),
895
        .dcsb_dat_o(dcsb_dat_sb),
896
        .dcsb_ack_o(dcsb_ack_sb),
897
        .dcsb_err_o(dcsb_err_sb),
898
 
899
        // SB and BIU
900
        .sbbiu_dat_o(sbbiu_dat_sb),
901
        .sbbiu_adr_o(sbbiu_adr_sb),
902
        .sbbiu_cyc_o(sbbiu_cyc_sb),
903
        .sbbiu_stb_o(sbbiu_stb_sb),
904
        .sbbiu_we_o(sbbiu_we_sb),
905
        .sbbiu_sel_o(sbbiu_sel_sb),
906
        .sbbiu_cab_o(sbbiu_cab_sb),
907
        .sbbiu_dat_i(sbbiu_dat_biu),
908
        .sbbiu_ack_i(sbbiu_ack_biu),
909
        .sbbiu_err_i(sbbiu_err_biu)
910
);
911
 
912
//
913
// Instantiation of Debug Unit
914
//
915
or1200_du or1200_du(
916
        // RISC Internal Interface
917
        .clk(clk_i),
918
        .rst(rst_i),
919
        .dcpu_cycstb_i(dcpu_cycstb_cpu),
920
        .dcpu_we_i(dcpu_we_cpu),
921
        .dcpu_adr_i(dcpu_adr_cpu),
922
        .dcpu_dat_lsu(dcpu_dat_cpu),
923
        .dcpu_dat_dc(dcpu_dat_qmem),
924
        .icpu_cycstb_i(icpu_cycstb_cpu),
925
        .ex_freeze(ex_freeze),
926
        .branch_op(branch_op),
927
        .ex_insn(ex_insn),
928
        .id_pc(id_pc),
929
        .du_dsr(du_dsr),
930 142 marcus.erl
        .du_dmr1(du_dmr1),
931 859 olof
        .du_flush_pipe(du_flush_pipe),
932 10 unneback
 
933
        // For Trace buffer
934
        .spr_dat_npc(spr_dat_npc),
935
        .rf_dataw(rf_dataw),
936
 
937
        // DU's access to SPR unit
938
        .du_stall(du_stall),
939
        .du_addr(du_addr),
940
        .du_dat_i(du_dat_cpu),
941
        .du_dat_o(du_dat_du),
942
        .du_read(du_read),
943
        .du_write(du_write),
944 142 marcus.erl
        .du_except_stop(du_except_stop),
945 10 unneback
        .du_hwbkpt(du_hwbkpt),
946
 
947
        // Access to DU's SPRs
948
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_DU]),
949
        .spr_write(spr_we),
950
        .spr_addr(spr_addr),
951
        .spr_dat_i(spr_dat_cpu),
952
        .spr_dat_o(spr_dat_du),
953
 
954
        // External Debug Interface
955
        .dbg_stall_i(dbg_stall_i),
956
        .dbg_ewt_i(dbg_ewt_i),
957
        .dbg_lss_o(dbg_lss_o),
958
        .dbg_is_o(dbg_is_o),
959
        .dbg_wp_o(dbg_wp_o),
960
        .dbg_bp_o(dbg_bp_o),
961
        .dbg_stb_i(dbg_stb_i),
962
        .dbg_we_i(dbg_we_i),
963
        .dbg_adr_i(dbg_adr_i),
964
        .dbg_dat_i(dbg_dat_i),
965
        .dbg_dat_o(dbg_dat_o),
966
        .dbg_ack_o(dbg_ack_o)
967
);
968
 
969
//
970
// Programmable interrupt controller
971
//
972
or1200_pic or1200_pic(
973
        // RISC Internal Interface
974
        .clk(clk_i),
975
        .rst(rst_i),
976
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_PIC]),
977
        .spr_write(spr_we),
978
        .spr_addr(spr_addr),
979
        .spr_dat_i(spr_dat_cpu),
980
        .spr_dat_o(spr_dat_pic),
981
        .pic_wakeup(pic_wakeup),
982
        .intr(sig_int),
983
 
984
        // PIC Interface
985
        .pic_int(pic_ints_i)
986
);
987
 
988
//
989
// Instantiation of Tick timer
990
//
991
or1200_tt or1200_tt(
992
        // RISC Internal Interface
993
        .clk(clk_i),
994
        .rst(rst_i),
995
        .du_stall(du_stall),
996
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_TT]),
997
        .spr_write(spr_we),
998
        .spr_addr(spr_addr),
999
        .spr_dat_i(spr_dat_cpu),
1000
        .spr_dat_o(spr_dat_tt),
1001
        .intr(sig_tick)
1002
);
1003
 
1004
//
1005
// Instantiation of Power Management
1006
//
1007
or1200_pm or1200_pm(
1008
        // RISC Internal Interface
1009
        .clk(clk_i),
1010
        .rst(rst_i),
1011
        .pic_wakeup(pic_wakeup),
1012
        .spr_write(spr_we),
1013
        .spr_addr(spr_addr),
1014
        .spr_dat_i(spr_dat_cpu),
1015
        .spr_dat_o(spr_dat_pm),
1016
 
1017
        // Power Management Interface
1018
        .pm_cpustall(pm_cpustall_i),
1019
        .pm_clksd(pm_clksd_o),
1020
        .pm_dc_gate(pm_dc_gate_o),
1021
        .pm_ic_gate(pm_ic_gate_o),
1022
        .pm_dmmu_gate(pm_dmmu_gate_o),
1023
        .pm_immu_gate(pm_immu_gate_o),
1024
        .pm_tt_gate(pm_tt_gate_o),
1025
        .pm_cpu_gate(pm_cpu_gate_o),
1026
        .pm_wakeup(pm_wakeup_o),
1027
        .pm_lvolt(pm_lvolt_o)
1028
);
1029
 
1030
 
1031
endmodule

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