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URL https://opencores.org/ocsvn/orsoc_graphics_accelerator/orsoc_graphics_accelerator/trunk

Subversion Repositories orsoc_graphics_accelerator

[/] [orsoc_graphics_accelerator/] [trunk/] [bench/] [verilog/] [gfx/] [bresenham.sav] - Blame information for rev 6

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Line No. Rev Author Line
1 6 Orka
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[*] GTKWave Analyzer v3.3.32 (w)1999-2012 BSI
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[*] Mon Mar 12 10:07:32 2012
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[*]
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[dumpfile] "/home/maiden/Creative/Svn/orgfx/bench/verilog/gfx/bresenham.vcd"
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[dumpfile_mtime] "Mon Mar 12 10:07:06 2012"
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[dumpfile_size] 14196
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[savefile] "/home/maiden/Creative/Svn/orgfx/bench/verilog/gfx/bresenham.sav"
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[timestart] 0
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[size] 1000 600
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[pos] 114 64
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*-3.047906 10 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] bresenham_bench.
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[sst_width] 225
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[signals_width] 226
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[sst_expanded] 1
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[sst_vpaned_height] 160
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@22
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bresenham_bench.bresenham.Length[15:0]
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@28
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bresenham_bench.bresenham.MajInc
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@22
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bresenham_bench.bresenham.MajStart[15:0]
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bresenham_bench.bresenham.Maj[15:0]
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bresenham_bench.bresenham.MinInc[9:0]
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bresenham_bench.bresenham.MinOut[15:0]
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bresenham_bench.bresenham.MinStart[23:0]
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bresenham_bench.bresenham.Min[23:0]
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@28
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bresenham_bench.bresenham.XMaj
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bresenham_bench.bresenham.clock
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@22
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bresenham_bench.bresenham.counter[15:0]
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@28
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bresenham_bench.bresenham.do_line
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bresenham_bench.bresenham.reset
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@200
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-output
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@28
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bresenham_bench.bresenham.busy
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bresenham_bench.bresenham.valid_out
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@c00024
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bresenham_bench.bresenham.X[15:0]
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@28
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(0)bresenham_bench.bresenham.X[15:0]
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(14)bresenham_bench.bresenham.X[15:0]
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(15)bresenham_bench.bresenham.X[15:0]
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@1401204
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-group_end
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@25
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bresenham_bench.bresenham.Y[15:0]
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[pattern_trace] 1
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[pattern_trace] 0

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