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[/] [orsoc_graphics_accelerator/] [trunk/] [rtl/] [verilog/] [gfx/] [div_uu.v] - Blame information for rev 6

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1 6 Orka
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  Non-restoring unsigned divider                             ////
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////                                                             ////
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////  Author: Richard Herveille                                  ////
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////          richard@asics.ws                                   ////
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////          www.asics.ws                                       ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2002 Richard Herveille                        ////
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////                    richard@asics.ws                         ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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//  CVS Log
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//
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//  $Id: div_uu.v,v 1.3 2003-09-17 13:08:53 rherveille Exp $
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//
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//  $Date: 2003-09-17 13:08:53 $
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//  $Revision: 1.3 $
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//  $Author: rherveille $
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//  $Locker:  $
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//  $State: Exp $
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//
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// Change History:
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//               $Log: not supported by cvs2svn $
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//               Revision 1.2  2002/10/31 13:54:58  rherveille
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//               Fixed a bug in the remainder output of div_su.v
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//
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//               Revision 1.1.1.1  2002/10/29 20:29:10  rherveille
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//
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//
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//
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//synopsys translate_off
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`include "timescale.v"
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//synopsys translate_on
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module div_uu(clk, ena, z, d, q, s, div0, ovf);
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        //
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        // parameters
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        //
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        parameter z_width = 16;
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        parameter d_width = z_width /2;
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        //
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        // inputs & outputs
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        //
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        input clk;               // system clock
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        input ena;               // clock enable
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        input  [z_width -1:0] z; // divident
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        input  [d_width -1:0] d; // divisor
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        output [d_width -1:0] q; // quotient
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        output [d_width -1:0] s; // remainder
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        output div0;
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        output ovf;
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        reg [d_width-1:0] q;
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        reg [d_width-1:0] s;
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        reg div0;
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        reg ovf;
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        //      
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        // functions
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        //
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        function [z_width:0] gen_s;
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                input [z_width:0] si;
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                input [z_width:0] di;
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        begin
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          if(si[z_width])
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            gen_s = {si[z_width-1:0], 1'b0} + di;
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          else
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            gen_s = {si[z_width-1:0], 1'b0} - di;
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        end
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        endfunction
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        function [d_width-1:0] gen_q;
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                input [d_width-1:0] qi;
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                input [z_width:0] si;
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        begin
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          gen_q = {qi[d_width-2:0], ~si[z_width]};
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        end
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        endfunction
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        function [d_width-1:0] assign_s;
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                input [z_width:0] si;
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                input [z_width:0] di;
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                reg [z_width:0] tmp;
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        begin
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          if(si[z_width])
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            tmp = si + di;
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          else
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            tmp = si;
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          assign_s = tmp[z_width-1:z_width-d_width];
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        end
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        endfunction
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        //
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        // variables
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        //
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        reg [d_width-1:0] q_pipe  [d_width-1:0];
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        reg [z_width:0] s_pipe  [d_width:0];
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        reg [z_width:0] d_pipe  [d_width:0];
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        reg [d_width:0] div0_pipe, ovf_pipe;
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        //
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        // perform parameter checks
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        //
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        // synopsys translate_off
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        initial
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        begin
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          if(d_width !== z_width / 2)
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            $display("div.v parameter error (d_width != z_width/2).");
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        end
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        // synopsys translate_on
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        integer n0, n1, n2, n3;
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        // generate divisor (d) pipe
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        always @(d)
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          d_pipe[0] <= {1'b0, d, {(z_width-d_width){1'b0}} };
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        always @(posedge clk)
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          if(ena)
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            for(n0=1; n0 <= d_width; n0=n0+1)
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               d_pipe[n0] <= #1 d_pipe[n0-1];
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        // generate internal remainder pipe
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        always @(z)
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          s_pipe[0] <= z;
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        always @(posedge clk)
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          if(ena)
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            for(n1=1; n1 <= d_width; n1=n1+1)
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               s_pipe[n1] <= #1 gen_s(s_pipe[n1-1], d_pipe[n1-1]);
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        // generate quotient pipe
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        always @(posedge clk)
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          q_pipe[0] <= #1 0;
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        always @(posedge clk)
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          if(ena)
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            for(n2=1; n2 < d_width; n2=n2+1)
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               q_pipe[n2] <= #1 gen_q(q_pipe[n2-1], s_pipe[n2]);
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        // flags (divide_by_zero, overflow)
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        always @(z or d)
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        begin
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          ovf_pipe[0]  <= !(z[z_width-1:d_width] < d);
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          div0_pipe[0] <= ~|d;
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        end
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        always @(posedge clk)
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          if(ena)
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            for(n3=1; n3 <= d_width; n3=n3+1)
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            begin
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                ovf_pipe[n3] <= #1 ovf_pipe[n3-1];
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                div0_pipe[n3] <= #1 div0_pipe[n3-1];
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            end
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        // assign outputs
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        always @(posedge clk)
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          if(ena)
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            ovf <= #1 ovf_pipe[d_width];
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        always @(posedge clk)
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          if(ena)
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            div0 <= #1 div0_pipe[d_width];
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        always @(posedge clk)
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          if(ena)
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            q <= #1 gen_q(q_pipe[d_width-1], s_pipe[d_width]);
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        always @(posedge clk)
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          if(ena)
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            s <= #1 assign_s(s_pipe[d_width], d_pipe[d_width]);
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endmodule
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