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[/] [orsoc_graphics_accelerator/] [trunk/] [rtl/] [verilog/] [gfx/] [gfx_wbm_read_arbiter.v] - Blame information for rev 6

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1 6 Orka
/*
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ORSoC GFX accelerator core
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Copyright 2012, ORSoC, Per Lenander, Anton Fosselius.
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WBM reader arbiter
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Loosely based on the arbiter_dbus.v (LGPL) in orpsocv2 by Julius Baxter, julius@opencores.org
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 This file is part of orgfx.
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 orgfx is free software: you can redistribute it and/or modify
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 it under the terms of the GNU Lesser General Public License as published by
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 the Free Software Foundation, either version 3 of the License, or
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 (at your option) any later version.
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 orgfx is distributed in the hope that it will be useful,
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 but WITHOUT ANY WARRANTY; without even the implied warranty of
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 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 GNU Lesser General Public License for more details.
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 You should have received a copy of the GNU Lesser General Public License
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 along with orgfx.  If not, see <http://www.gnu.org/licenses/>.
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*/
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// 3 Masters, one slave
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module gfx_wbm_read_arbiter
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  (
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   master_busy_o,
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   // Interface against the wbm read module
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   read_request_o,
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   addr_o,
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   sel_o,
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   dat_i,
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   ack_i,
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   // Interface against masters (clip)
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   m0_read_request_i,
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   m0_addr_i,
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   m0_sel_i,
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   m0_dat_o,
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   m0_ack_o,
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   // Interface against masters (fragment processor)
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   m1_read_request_i,
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   m1_addr_i,
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   m1_sel_i,
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   m1_dat_o,
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   m1_ack_o,
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   // Interface against masters (blender)
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   m2_read_request_i,
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   m2_addr_i,
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   m2_sel_i,
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   m2_dat_o,
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   m2_ack_o
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   );
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output        master_busy_o;
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// Interface against the wbm read module
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output        read_request_o;
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output [31:2] addr_o;
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output  [3:0] sel_o;
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input  [31:0] dat_i;
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input         ack_i;
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// Interface against masters (clip)
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input         m0_read_request_i;
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input  [31:2] m0_addr_i;
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input   [3:0] m0_sel_i;
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output [31:0] m0_dat_o;
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output        m0_ack_o;
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// Interface against masters (fragment processor)
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input         m1_read_request_i;
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input  [31:2] m1_addr_i;
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input   [3:0] m1_sel_i;
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output [31:0] m1_dat_o;
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output        m1_ack_o;
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// Interface against masters (blender)
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input         m2_read_request_i;
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input  [31:2] m2_addr_i;
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input   [3:0] m2_sel_i;
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output [31:0] m2_dat_o;
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output        m2_ack_o;
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// Master ins -> |MUX> -> these wires
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wire        rreq_w;
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wire [31:2] addr_w;
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wire  [3:0] sel_w;
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// Slave ins -> |MUX> -> these wires
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wire [31:0] dat_w;
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wire        ack_w;
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// Master select (MUX controls)
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wire [2:0] master_sel;
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assign master_busy_o = m0_read_request_i | m1_read_request_i | m2_read_request_i;
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// priority to wbm1, the blender master
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assign master_sel[0] = m0_read_request_i & !m1_read_request_i & !m2_read_request_i;
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assign master_sel[1] = m1_read_request_i & !m2_read_request_i;
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assign master_sel[2] = m2_read_request_i;
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// Master input mux, priority to blender master
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assign m0_dat_o = dat_i;
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assign m0_ack_o = ack_i & master_sel[0];
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assign m1_dat_o = dat_i;
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assign m1_ack_o = ack_i & master_sel[1];
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assign m2_dat_o = dat_i;
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assign m2_ack_o = ack_i & master_sel[2];
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assign read_request_o = master_sel[2] |
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                        master_sel[1] |
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                        master_sel[0];
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assign addr_o = master_sel[2] ? m2_addr_i :
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                master_sel[1] ? m1_addr_i :
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                                      m0_addr_i;
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assign sel_o  = master_sel[2] ? m2_sel_i :
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                master_sel[1] ? m1_sel_i :
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                                      m0_sel_i;
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endmodule // gfx_wbm_read_arbiter
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