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[/] [orsoc_graphics_accelerator/] [trunk/] [rtl/] [verilog/] [gfx/] [gfx_wbm_write.v] - Blame information for rev 6

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1 6 Orka
/*
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ORSoC GFX accelerator core
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Copyright 2012, ORSoC, Per Lenander, Anton Fosselius.
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The Wishbone master component will interface with the video memory, writing outgoing pixels to it.
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Loosely based on the vga lcds wishbone writer (LGPL) in orpsocv2 by Julius Baxter, julius@opencores.org
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 This file is part of orgfx.
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 orgfx is free software: you can redistribute it and/or modify
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 it under the terms of the GNU Lesser General Public License as published by
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 the Free Software Foundation, either version 3 of the License, or
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 (at your option) any later version.
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 orgfx is distributed in the hope that it will be useful,
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 but WITHOUT ANY WARRANTY; without even the implied warranty of
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 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 GNU Lesser General Public License for more details.
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 You should have received a copy of the GNU Lesser General Public License
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 along with orgfx.  If not, see <http://www.gnu.org/licenses/>.
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*/
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//synopsys translate_off
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`include "timescale.v"
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//synopsys translate_on
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module gfx_wbm_write (clk_i, rst_i,
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                      cyc_o, stb_o, cti_o, bte_o, we_o, adr_o, sel_o, ack_i, err_i, dat_o, sint_o,
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                      write_i, ack_o,
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                      render_addr_i, render_sel_i, render_dat_i);
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  // wishbone signals
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  input         clk_i;    // master clock input
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  input         rst_i;    // Asynchronous active high reset
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  output reg    cyc_o;    // cycle output
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  output        stb_o;    // strobe ouput
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  output [ 2:0] cti_o;    // cycle type id
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  output [ 1:0] bte_o;    // burst type extension
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  output        we_o;     // write enable output
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  output [31:0] adr_o;    // address output
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  output [ 3:0] sel_o;    // byte select outputs
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  input         ack_i;    // wishbone cycle acknowledge
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  input         err_i;    // wishbone cycle error
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  output [31:0] dat_o;    // wishbone data out           /// TEMP reg ///
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  output        sint_o;     // non recoverable error, interrupt host
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  // Renderer stuff
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  input         write_i;
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  output reg    ack_o;
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  input [31:2]  render_addr_i;
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  input [ 3:0]  render_sel_i;
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  input [31:0]  render_dat_i;
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  //
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  // module body
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  //
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  assign adr_o  = {render_addr_i, 2'b00};
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  assign dat_o  = render_dat_i;
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  assign sel_o  = render_sel_i;
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  assign sint_o = err_i;
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  // We only write, these can be constant
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  assign we_o   = 1'b1;
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  assign stb_o  = 1'b1;
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  assign cti_o  = 3'b000;
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  assign bte_o  = 2'b00;
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  // Acknowledge when a command has completed
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  always @(posedge clk_i or posedge rst_i)
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  begin
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    //  reset, init component
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    if(rst_i)
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    begin
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      ack_o <= 1'b0;
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      cyc_o <= 1'b0;
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    end
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    // Else, set outputs for next cycle
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    else
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    begin
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      cyc_o <= ack_i   ? 1'b0 : // TODO: connect to pixel fifo rreq instead
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               write_i ? 1'b1 :
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               cyc_o;
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      ack_o <= ack_i; // TODO: always set when fifo isn't full
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    end
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  end
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endmodule

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