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robotron 


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 * pipelined synchronous pulse counter *

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 fast counter for slowcarry architectures

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 nonmonotonic counting, value calculable by HDL/CPU

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 idea&code by Marek Peca 08/2012

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 Vyzkumny a zkusebni letecky ustav, a.s. http://vzlu.cz/

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 thanks to Michael Vacek for testing

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Pipelined Synchronous Pulse Counter

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===================================

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is a proposal of binary counter, designed to minimize logic path

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length in between flipflops to one gate (MUX/AND) only, at the

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expense of not so straightforward binary counting. The reason for this

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design has emerged while using Actel (MicroSemi) ProASIC/IGLOO

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architecture, lacking any hardwired support for fast carry.

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During our work on Actel FPGAs (basically, 3LUT & DFF only), we were

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aware of following types of faster counters:

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 LFSR counter

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 Johnson counter

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 "RLA counter" (as tailored using Actel's SmartGen core generator)

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Johnson due to its O(2^n) (n as number of bits) can not be used for

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longer counts; LFSR's are hard to invert (table lookup seems to be

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only known method), therefore also impractical for wider counters. RLA

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counter is still too slow and complex for wider counters and moderate

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speeds (e.g. > 24bits @ >100MHz).

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As a consequence, the proposed counter uses synchronous dividebytwo

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blocks, each using 1bit pipeline and carry by singleclock

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pulse. Design is simple and fast, preliminary results from Synplify

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and Actel Designer shows 32bits @200MHz feasible.

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However, output bit lines are nonproportionaly delayed by discrete

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number of clock periods. Therefore, to obtain linear bit word, an

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inversion formula needs to be applied. Fortunately, the inversion is

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simple (unlike LFSR's), in C (pcount.c):

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for (k = 1; k < n; k++)

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if ((y & ((1<

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y = y ^ (1<

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 it may be implemented in VHDL core, or within CPU as shown, depending on

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application requirements.

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Files

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=====

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pdivtwo.vhdl basic building block  1stage pipelined

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flipflop

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pdchain.vhdl counter toplevel entity

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pcount_tb.vhdl GHDL testbench

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pcount.c C language encoder/decoder of counter bitword

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doc/pcounter_4bit_trace.pdf simulated signals of 4bit counter

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doc/pcounter_sch.pdf schematic diagram of the counter

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Results

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=======

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Synthesized within larger circuit for Actel ProASIC3E A3PE1500Std

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as 32bit wide counter, typical frequency: 234MHz

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Comments?

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=========

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***

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* First, if you find this pretty simple idea to be nonoriginal work

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* *please* send me an email with respective pointers; I will then freeze

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* the repository, including link to the reference.

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***

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If you find this idea useful, apply it whenever you want, however,

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share your improvements. E.g.:

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 (fast) HDL implementation of bitword encode/decode

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 preset/reset/match/enable logic

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Testimonials (usage/frequency/bits/architecture) are indeed welcome.

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Greetings by Marek
