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[/] [pcounter/] [trunk/] [pdivtwo.vhdl] - Blame information for rev 2

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1 2 robotron
--
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-- * pipelined synchronous pulse counter *
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--  pdivtwo -- core 1-stage element (pipelined f/2 divider)
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--
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-- fast counter for slow-carry architectures
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-- non-monotonic counting, value calculable by HDL/CPU
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--
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-- idea&code by Marek Peca <mp@duch.cz> 08/2012
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-- Vyzkumny a zkusebni letecky ustav, a.s. http://vzlu.cz/
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-- thanks to Michael Vacek <michael.vacek@vzlu.cz> for testing
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity pdivtwo is
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  port (
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    clock: in std_logic;
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    en: in std_logic;
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    q, p: out std_logic
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  );
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end pdivtwo;
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architecture behavioral of pdivtwo is
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  signal state: std_logic := '1';
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  signal pipe: std_logic := '0';
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  signal next_state, next_pipe: std_logic;
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begin
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  next_state <= not state when en = '1' else state;
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  next_pipe <= state and en;
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  p <= pipe;
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  q <= state;
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  process
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  begin
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    wait until clock'event and clock = '1';
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    state <= next_state;
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    pipe <= next_pipe;
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  end process;
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end behavioral;

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